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M48Z32V
3.3V, 256 Kbit (32 Kbit x8) ZEROPOWER(R) SRAM
FEATURES SUMMARY

INTEGRATED, ULTRA LOW POWER SRAM, AND POWER-FAIL CONTROL CIRCUIT READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) - M48Z32V: 2.7V VPFD 3.0V ULTRA-LOW STANDBY CURRENT
Figure 2. Package
44 1
SOH44 (MT) 44-pin, Hatless SOIC
Figure 1. Logic Diagram
VCC B+
Table 1. Signal Names
8 DQ0-DQ7
A0-A14 DQ0-DQ7 E Address Inputs Data Inputs / Outputs Chip Enable Input Output Enable Input WRITE Enable Input Supply Voltage Ground Positive Battery Pin Not Connected
15 A0-A14
W E G
M48Z32V
G W VCC VSS B+
VSS
AI04787
NC
March 2004
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M48Z32V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.SOH44 - 44-lead Plastic, Hatless, Small Package Outline. . . . . . . . . . . . . . . . . . . . . . . 13 Table 11. SOH44 - 44-lead Plastic, Hatless, Small Package Mechanical Data . . . . . . . . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M48Z32V
SUMMARY DESCRIPTION
The M48Z32V ZEROPOWER(R) RAM is a 32 Kbit x 8, non-volatile static RAM that integrates powerfail deselect circuitry and battery control logic on a single die. The 44-pin, 330mil SOIC provides a battery pin for an external, user-supplied battery. This is all that is required to fully non-volatize the SRAM.
Figure 3. SOIC Connections
A14 A12 A7 A6 A5 A4 NF NC NC NC NC NC NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
44 1 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 M48Z32V 12 33 13 32 14 31 15 30 16 29 17 28 27 18 19 26 20 25 21 24 22 23
VCC W A13 A8 A9 A11 G NC NC NC NC NC NC NC A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 B+
AI04786
Note: NF, Pin 7 must be tied to VSS.
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M48Z32V
Figure 4. Block Diagram
A0-A14
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY
POWER
32K x 8 SRAM ARRAY
DQ0-DQ7
VPFD
E W G
USER SUPPLIED
VCC
VSS
AI04788
OPERATING MODES
The M48Z32V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single power supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree Table 2. Operating Modes
Mode Deselect WRITE 3.0 to 3.6V READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) VIL VIL X X VIL VIH X X VIH VIH X X DOUT High Z High Z High Z Active Active CMOS Standby Battery Back-up Mode VCC E VIH VIL G X X W X VIL DQ0-DQ7 High Z DIN Power Standby Active
of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately VSO, the control circuitry connects the battery which maintains data until valid power returns.
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. Note: 1. See Table 10., page 12 for details.
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M48Z32V
READ Mode The M48Z32V is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 262,144 locations in the static storage array. Thus, the unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be Figure 5. READ Mode AC Waveforms
tAVAV A0-A14 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00925
available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
M48Z32V Symbol Parameter
(1)
-35 Min Max
Unit
tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX
READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
35 35 35 15 5 0 13 13 5 0
ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C or -40 to 85C; VCC = 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 9., page 10).
5/16
M48Z32V
WRITE Mode The M48Z32V is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another
READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A14 VALID tAVWH tWHAX E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI05662
tWHQX
Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI00927
tELEH
tEHAX
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M48Z32V
Table 4. WRITE Mode AC Characteristics
M48Z32V Symbol Parameter
(1)
-35 Min Max
Unit
tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ
(2,3)
WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition
35 0 0 25 25 0 0 12 12 0 0 13 25 25 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tAVWH tAVEH tWHQX(2,3)
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C or -40 to 85C; VCC = 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 9., page 10). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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M48Z32V
Data Retention Mode With valid VCC applied, the M48Z32V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z32V may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO , the control circuit switches power to the external battery which preserves data. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD(min) plus tREC(min). Normal RAM operation can resume tREC after VCC exceeds VPFD(max). For more information on Battery Storage Life refer to the Application Note AN1012. VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (see Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). Figure 8. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z32V
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 5. Absolute Maximum Ratings
Symbol TA TSTG TSLD(1,2) VIO VCC IO PD Parameter Grade 1 Ambient Operating Temperature Grade 6 Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation SOIC -40 to 85 -55 to 125 260 -0.3 to VCC + 0.3 -0.3 to 4.6 20 1 C C C V V mA W Value 0 to 70 Unit C
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. For standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 2. For Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds). CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
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M48Z32V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter(1) Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: 1. Output Hi-Z is defined as the point where data is no longer driven.
M48Z32V 3.0 to 3.6 Grade 1 Grade 6 0 to 70 -40 to 85 50 5 0 to 3 1.5
Unit V C C pF ns V V
Figure 9. AC Measurement Load Circuit
DEVICE UNDER TEST
645
CL = 50pF or 5pF
1.75V
CL includes JIG capacitance
AI04789
Table 7. Capacitance
Symbol CIN CIO(3) Parameter(1,2) Input Capacitance Input / Output Capacitance Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 3.3V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
10/16
M48Z32V
Table 8. DC Characteristics
Sym ILI ILO(2) IBAT Parameter Input Leakage Current Output Leakage Current Battery Current Test Condition(1) 0V VIN VCC 0V VOUT VCC TA = 40C; VCC = 0V VBAT = 3V IO = 0mA; Cycle Time = Min E = 0.2V, other input = VCC - 2V or 0.2V E = VIH E = VCC - 0.2V -0.3 2.2 IOL = 2.1mA IOH = -1mA 0.8VCC 0.2 Min Typ Max 1 1 1.2 Unit A A A
ICC1
Supply Current Supply Current (TTL Standby) Supply Current (CMOS Standby) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
45
mA
ICC2 ICC3 VIL(3) VIH VOL VOH
800 500 0.8 VCC + 0.3 0.4
A A V V V V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C or -40 to 85C; VCC = 3.0 to 3.6V (except where noted). 2. Outputs deselected. 3. Negative spikes of -1V allowed for up to 10ns once per cycle.
11/16
M48Z32V
Figure 10. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tPD INPUTS
RECOGNIZED
tR tRB tDR DON'T CARE tREC
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
Table 9. Power Down/Up AC Characteristics
Symbol tPD tF(2) tFB(3) tR tRB tREC(4) Parameter(1) E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time VPFD (max) to Inputs Recognized Min 0 300 10 10 1 40 200 Max Unit s s s s s ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C or -40 to 85C; VCC = 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. tREC (min) = 20ms for industrial temperature Grade (6) device.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol VPFD VSO Parameter(1,2) Power-fail Deselect Voltage Battery Back-up Switchover Voltage Min 2.7 Typ 2.85 VPFD - 100mV Max 3.0 Unit V V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C or -40 to 85C; VCC = 3.0 to 3.6V (except where noted).
12/16
M48Z32V
PACKAGE MECHANICAL INFORMATION
Figure 11. SOH44 - 44-lead Plastic, Hatless, Small Package Outline
A2 B e
A C CP
D
N
E
H A1 L
1 SOH-C
Note: Drawing is not to scale.
Table 11. SOH44 - 44-lead Plastic, Hatless, Small Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e H L N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 - 11.51 0.41 0 44 0.10 Min Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 - 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 - 0.453 0.016 0 44 0.004 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 - 0.500 0.050 8 inch
13/16
M48Z32V
PART NUMBERING
Table 12. Ordering Information Scheme
Example: M48Z 32V -35 MT 1 F
Device Type M48Z
Supply Voltage and Write Protect Voltage 32V = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V
Speed -35 = 35ns
Package MT = 44-lead, Hatless SOIC
Temperature Range 1 = 0 to 70C 6 = -40 to 85C
Shipping Method blank = Tubes (Not for New Design - Use E) E = Lead-free Package (ECO F = Lead-free Package (ECO PACK(R)), Tubes PACK(R)), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
14/16
M48Z32V
REVISION HISTORY
Table 13. Revision History
Date October 2002 07-Nov-02 22-Mar-04 Rev. # 1.0 1.1 2.0 First Issue Update Absolute Maximum Ratings, DC Characteristics (Table 5, 8) Reformatted; updated Lead-free information (Table 5, 12) Revision Details
15/16
M48Z32V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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