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| Ordering number : ENN5841 Monolithic Linear IC LA7615 Single-Chip NTSC Color TV IC Overview The LA7615 is an NTSC color TV IC that supports computer control over an I2C bus. In addition to improved quality and increased functionality in color TV products, this IC supports the development of a TV set product line in software and the simplification of end product design. The provision of an I2C bus means that this product can also respond to desires for increased total manufacturing productivity, including improved automation of computer controlled production lines. Package Dimensions unit: mm 3071-DIP64S [LA7615] 64 33 19.05 16.8 Functions * I2C bus control, VIF, SIF, Y, C, and deflection circuits integrated on a single chip. 1 57.2 32 Features * Pursuit of higher integration levels The LA7615 integrates VIF, SIF, luminance, chrominance, and deflection (horizontal and vertical synchronization) circuits, A/V switching, and power supply control on a single chip. * Bus control for reduced external component counts and mechanical adjustment points All the LA7615 signal-processing circuits can be controlled and adjusted digitally over the I2C bus. All adjustments, both those required during manufacture and the user controls, can be controlled over the I2C bus, and both function selection and characteristics settings can be performed in software over the I 2 C bus. This increases flexibility in designing a product line of TV sets and also enhances productivity by allowing mixed production runs. While this device supports multifunction and good performance, it is also economical in that it achieves reduced power and reduced pin count. 0.95 0.48 1.78 1.01 SANYO: DIP64S Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 91799RM (OT) No. 5841-1/39 0.51min 3.2 5.0max 4.0 0.25 LA7615 Specifications Maximum Ratings at Ta = 25C Parameter Symbol V2 max Maximum supply voltage V17 max V32 max V60 max Maximum supply current Allowable power dissipation Operating temperature Storage temperature I24 max Pd max Topr Tstg Ta 65C Conditions Ratings 9.6 9.6 9.6 9.6 30 1.5 -10 to +65 -55 to +150 Unit V V V V mA W C C Operating Conditions at Ta = 25C Parameter Symbol V2 Recommended supply voltage V17 V32 V60 Recommended supply current I24 V2 op Operating supply voltage range V17 op V32 op V60 op Operating supply current range I24 op Conditions Ratings 7.6 7.6 7.6 7.6 24 7.3 to 7.9 7.3 to 7.9 7.3 to 7.9 7.3 to 7.9 20 to 30 Unit V V V V mA V V V V mA Functional Description No. 5841-2/39 LA7615 Furthermore, this IC also supports high image quality systems and responds to needs from a diverse range of end products. * Two independent inputs for the luminance and chrominance signals and switching between the Y1/C1 and Y2/C2 inputs * Video muting on/off switch * Built-in filters (The filter f0 adjustment function can be used to select the filter characteristics.) Chrominance system: Bandpass filter (symmetric and asymmetric types) Luminance system: Color trap and delay line Mode f0 = Trap f0 0 1 2 3 3.58 MHz 4.2 MHz 5.0 MHz 10.0 MHz Y signal *Total delay 500 ns 510 ns 520 ns 265 ns BPF Asymmetric (peaking type) Symmetric Bypass Chroma signal *Total 500 ns delay 515 ns 535 ns 265 ns *: Reference values No. 5841-3/39 LA7615 No. 5841-4/39 LA7615 Bus Control General Functions ON/OFF SW Video muting switch VIF/SIF Video signal switching RF AGC delay IF AGC SW PLL tuning APC detector adjustment AFT defeat switch Noise inverter defeat switch Video level Sound 4.5 MHz trap FM level F0 fast (FM detection speed) Luminance/Chrominance Systems Y/C input selection (one of two inputs) switch Luminance (Y) F0 adjustment (filter control) Chrominance signal bandpass filter mode switch Chrominance signal bandpass filter bypass switch Black stretch on/off switch Peaking (sharpness) control Coring on/off switch Auro flesh on/off Overload switch Contrast control Brightness control Tint control Saturation control RGB bias adjustment RGB bias adjustment Sub-brightness control Brightness ABL operating point control Brightness ABL mode defeat switch Emergency ABL defeat switch Deflection System AFC gain (sync killer) APC gain Horizontal duty adjustment Horizontal phase adjustment Geometrical distortion correction EAST-WEST DC EAST-WEST AMPLITUDE East-west corner 1/2 Tilt adjustment Vertical linearity adjustment Vertical S-curve correction Vertical size adjustment Vertical DC adjustment Standard/nonstandard mode switch VERTICAL KILL V-COMP adjustment DAC REF. (+B TRIM) Others: Status Register POWER ON RESET X-ray protection switch Horizontal lock detection AFT and RF AGC status discrimination 1 bit 1 bit 1 bit 2 bits each 5 bits 4 bits 3 bits each 4 bits 4 bits 4 bits 7 bits 6 bits 1 bit 1 bit 3 bits 4 bits 2 bits 2 bits 2 bits 4 bits 1 bit 2 bits 1 bit 1 bit 1 bit 5 bits 1 bit 1 bit 1 bit 6 bits 6 bits 7 bits 7 bits 6 bits each 7 bits each 2 bits each 3 bits 1 bit each 1 bit 1 bit 6 bits 1 bit 7 bits 6 bits 1 bit 1 bit 3 bits 4 bits 4 bits 1 bit 1 bit 1 bit No. 5841-5/39 LA7615 Vertical Linearity Wide Narrow Narrow Wide A10048 Vertical S-Curve Correction Wide Narrow Narrow Wide Wide Narrow A10049 Tilt A10050 East-West Amp A10051 Corner Pin East-west corner 1 East-west corner 2 The distortion correction operation is symmetric left to right. A10052 No. 5841-6/39 LA7615 Bus : Control Register Bit Allocation Map Control Register Bit Allocations IC address IC Add7 Add0 1011 1010 Sub address Add7 Add0 0000 0000 MSB Bit 7 1 Bit 6 Bit 5 Bit 4 On/Off Data bits Bit 3 Bit 2 Video mute 0001 1 APC gain (b1) 0010 1 Hor duty cycle (b1) 0011 1 BNI defeat 0100 1 IF AGC defeat 0101 1 VCO free running (b6) 0110 1 4.5 MHz trap (b3) 0111 1 Video switch 1000 1 Vertical kill 1001 1 Countdown mode (b1) 1010 1 (b0) (b2) (b1) (b0) (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) RF AGC delay (b5) AFT defeat (b4) FM level (b4) (b3) (b2) (b1) (b0) (b3) (b2) (b1) (b0) (b0) (b0) B+ trim (b3) Horizontal phase (b3) (b2) (b1) (b0) (b2) (b1) (b0) Bit 1 LSB Bit 0 AFC gain/sync kill (b1) (b0) IF APC offset adjust. (b5) Vertical DC (b5) (b4) East-west DC (b4) (b3) East-west amp (b3) (b2) (b1) (b0) (b2) (b1) (b0) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) 1011 1 Vertical comp. (b2) (b1) (b0) East-west tilt (b3) (b2) (b1) (b0) 1100 1 Vertical size (b6) (b5) (b4) (b3) Vertical linearity (b3) (b2) (b1) (b0) (b2) (b1) (b0) 1101 1 1110 1 FM mode switch Vertical S-correction (b3) (b2) (b1) (b0) 1111 1 East-west bottom corner (b2) (b1) (b0) East-west top corner (b2) (b1) (b0) Bits are transmitted in this order No. 5841-7/39 LA7615 Bus : Control Register Bit Allocation Map Control Register Bit Allocations (cont) IC address IC Add7 0 1011 1010 Sub address Add7 Add0 0001 0000 MSB Bit 7 1 Bit 6 Red bias (b6) 0001 1 Green bias (b6) 0010 1 Blue bias (b6) 0011 1 (b5) Red drive (b5) 0100 1 Green drive (b5) 0101 1 Blue drive (b5) 0110 1 Blue sub bias (b1) 0111 1 (b0) Brightness control (b5) 1000 1 Pix control (b5) 1001 1 Coring switch 1010 1 F0 select (b1) 1011 1 Tint control (b6) 1100 1 Color control (b6) 1101 1 (b5) ABL defeat 1110 1 Test register 1 (b3) 1111 1 Test regster 3 (b3) (b2) (b1) (b0) (b2) (b1) (b0) (b4) Mid Stp defeat (b3) EMG defeat (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) (b0) (b4) Peaking control (b4) (b3) Chroma BPF (b2) Auto flesh (b1) Chrom bypass (b0) Over load (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) (b4) Red sub bias (b1) (b0) (b3) (b2) Green sub bias (b1) (b0) (b1) (b0) Y/C switch (b4) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) Bit 5 Bit 4 Data bits Bit 3 Bit 2 Bit 1 LSB Bit 0 Bright ABL threshold (b2) Test register 2 (b2) Black Stretch defeat (b1) Blanking defeat (b0) Reserved (b1) (b0) Bits are transmitted in this order Table 8 : Status Register Bit Allocation Map Status Register Bit Allocations IC address IC Add7 Add0 1011 1010 Sub address Add7 Add0 0001 0000 MSB Bit 7 Pon Bit 6 XRay Bit 5 Horiz lock 0001 1 1 1 1 1 1 1 1 Bit 4 On/off Data bits Bit 3 AFT status Bit 2 Bit 1 RF AGC status LSB Bit 0 No. 5841-8/39 LA7615 Bus : Control Register Truth Table Control Register Truth Table Register On/off Video mute AFC gain/sync Kill BNI defeat IF AGC defeat AFT defeat Video switch Vertical Kill Countdown mode FM mode switch Y/C switch Coring switch F0 select Chrom BPF Autoflesh Chroma bypass Over load Bright ABL defeat Bright mid stop defeat Emergency ABL defeat Black Str defeat Blanking defeat 0 HEX Off Active Sync Kill Enable BNI Enable AGC Enable AFT IF video Vertical active Standard Normal Y1/C1 IN Defeat 3.58 Trap Symmetrical Off BPF Off Enable Enable Enable Enable Enable 1 HEX On Mute Low gain (auto mode) Defeat Defeat Defeat Aux video Vertical Killed Non-standard Fast Y2/C2 IN Enable 4.20 Trap Peaker On Bypass Active Defeat Defeat Defeat Defeat Defeat 2 HEX na na Mid gain na na na na na 50 Hz na na na 5.00 APF na na na na na na na na na 3 HEX na na High gain na na na na na 48 Hz na na na 10.0 APF na na na na na na na na na Bus : Status Register Truth Table Status Register Truth Table Register POR XRP Horizontal lock On/off AFT RF AGC 0 HEX Inactive Inactive Locked Off IF frequency in high RF AGC voltage is Low. 1 HEX Low standby detected XRP fault detected Unlocked On IF frequency in range RF AGC voltage is in range. 2 HEX na na na na na na 3 HEX na na na na IF frequency is low RF AGC voltage is High. No. 5841-9/39 LA7615 Initial Condition Function On/off Video mute AFC gain & sync Kill APC gain B+ trim Horizontal duty Horizontal phase BNI defeat RF AGC delay IF AGC defeat AFT defeat FM level IF VCO free running 4.5 trap Video level Video switch IF APC offset Vertical Kill Vertical DC Countdown mode East/west DC East/west amplitude Vertical comp. East/west tilt Vertical size Vertical linearity FM mode switch Vertical S-correction East/west bottom East/west top corner Red bias Green bias Blue bias Red drive Green drive Blue drive Blue sub bias Red sub bias1 Green sub bias Y/C switch Brightness control Pix control Coring switch Peaking control F0 select Chroma BPF Autoflesh Chroma bypass Over load Tint control Color control Bright ABL defeat Bright mid stop Emergency ABL defeat Bright ABL threshold Test registers 1, 2, 3 Black strech defeat Blanking defeat 1 HEX 0 HEX 1 HEX 3 HEX 8 HEX 1 HEX 8 HEX 0 HEX 20 HEX 0 HEX 0 HEX 10 HEX 40 HEX 8 HEX 4 HEX 0 HEX 20 HEX 0 HEX 20 HEX 0 HEX 10 HEX 8 HEX 0 HEX 8 HEX 40 HEX 8 HEX 0 HEX 8 HEX 0 HEX 0 HEX 00 HEX 00 HEX 00 HEX 3F HEX 3F HEX 3F HEX 2 HEX 2 HEX 2 HEX 0 HEX 20 HEX 20 HEX 0 HEX 00 HEX 1 HEX 0 HEX 0 HEX 0 HEX 0 HEX 40 HEX 40 HEX 0 HEX 0 HEX 0 HEX 0 HEX 0 HEX 1 HEX 0 HEX No. 5841-10/39 Standby Vcc 6.3VDC 3.0VDC Power Up Sequence ON/OFF BIT Registers (TR1-TR2) Video.Mute BIT LA7615 XRP BIT (STATUS) Pon BIT (STATUS) 7.3VDC Run.Vcc stable Registers (TR3-TR31) time 2ms ON/OFF =0 Initialize TR1 to TR2 ON/OFF =1 Initialize TR3 to TR31 Mute =0 A10053 No. 5841-11/39 After Standby Vcc reaches 3.0VDC, the microcontroller has to wait 2ms in order to intitialize the HC Interface in LA7615. LA7615 Electrical Characteristics at Ta = 25C, VCC = V2 = V17 = V32 = V60 = 7.6 V, ICC = I24 = 24 mA Parameter [Circuit Voltages and Currents] Horizontal supply voltage IF power supplly current (V2) Vertical supply current (V17) Video/chrominance supply current (V32) FM supply current (V60) [VIF Block] No signal AFT output voltage No signal video output voltage APC pull-in range (U) APC pull-in range (L) Maximum RF AGC voltage Minimum RF AGC voltage RF AGC Delay Pt (@DAC = 0) RF AGC Delay Pt (@DAC = 63) Maximum AFT output voltage Minimum AFT output voltage AFT detection sensitivity 4.5 MHz attenuation Video output amplitude Synchronizing signal tip level Input sensitivity Vide/sync ratio (@100 dB) Differential gain Differential phase Video signal-to-noise ratio 920 kHz beat level [SIF Block] [1st.SIF] 4.5 MHz conversion gain 4.5 MHz output level First SIF maximum input [SIF Block] FM detection output voltage FM limiting sensitivity FM detector output bandwidth FM detector output distortion AM rejection ratio SIF. Signal-to-noise ratio [Chrominance Block] ACC amplitude characteristics 1 ACC amplitude characteristics 2 B-Y/Y amplitude ratio Color control characteristics 1 Color control characteristics 2 Color control sensitivity Tint center Tint control max Tint control min Tint control sensitivity Demodulated output ratio: B-Y/R-Y Demodulated output ratio: G-Y/R-Y ACCM1 ACCM2 CLRBY CLRMN CLRMN CLRSE TINCEN TINMAX TINMIN TINSE BR GR TINT NOM TINT max TINT min Color: max/normal Color: max/min Input: +6 dB/0 dB, 0 dB = 40 IRE Input: -14 dB/0 dB 0.8 0.8 75 1.7 33 1 -10 30 -60 0.7 1.06 0.34 1.19 0.40 45 -45 1.0 1.0 100 2.0 40 2 1.2 1.1 120 2.3 50 4 +5 60 -30 2.0 1.32 0.46 times times % times dB %/bit deg deg deg deg/bit SOADJ SLS SF STHD SAMR SSN 40 74 50 414 424 434 50 100k 1 mVrms dB Hz % dB dB SGG SVO SVM 21 91 -1 26 96 0 31 101 +1 dB dB dB V14 V53 fPU fPL V4H V4L RFAGC0 RFAGC63 V14H V14L Sf TRAP VO53 V53TIP VIN V/S DG DP S/N I920 With no input signal With no input signal After APC, PLL, and D/A converter adjustment After APC, PLL, and D/A converter adjustment CW = 91 dB, DAC = 0 CW = 91 dB, DAC = 63 DAC = 0 DAC = 63 CW = 93 dB, frequency change CW = 93 dB, frequency change CW = 93 dB, frequency change V100 kHz/V4.5 MHz 93 dB, 87.5% Video MOD 93 dB, 87.5% Video MOD Output -3 dB 100 dB, 87.5% Video MOD 93 dB, 87.5% Video MOD 93 dB, 87.5% Video MOD CW = 93 dB V3.58 MHz/V920 kHz 55 2.4 1.8 2.4 6.2 0.5 33 6.5 0.9 25 -35 2 2.6 43 2.5 2 2 58 -57 -50 2.8 4.7 1 1 7.7 0 96 86 7.6 1.2 17 -32 2.2 2.8 46 3 10 10 % deg dB dB 8.2 0.2 9.0 0.4 3.8 4.9 4.8 5.1 Vdc Vdc MHz MHz Vdc Vdc dB dB Vdc Vdc mV/kHz dB Vp-p Vdc dB HVCC I2 (IFICC) I17 (DEFICC) I32 (YCICC) I60 (FMICC) IF AGC : 5 V 7.2 28 10 65 5.5 7.6 43 13 85 8.5 8 58 16 105 11.5 V mA mA mA mA Symbol Conditions Ratings min typ max Unit Continued on next page. No. 5841-12/39 LA7615 Continued from preceding page. Parameter Demodulation angle B-Y/R-Y Demodulation angle G-Y/R-Y Killer operating point Chrominance VCO free-running frequency Chrominance pull-in range (+) Chrominance pull-in range (-) Auto Flesh characteristics: 73 Auto Flesh characteristics: 118 Auto Flesh characteristics: 163 Overload characteristics 1 Overload characteristics 2 Overload characteristics 3 [Chrominance Bandpass Filter Block] Peaking amplitude characteristics: 3.08 MHz Peaking amplitude characteristics: 3.88/3.28 MHz Peaking amplitude characteristics: 4.08/3.08 MHz Bandpass amplitude characteristics: 3.08 MHz Bandpass amplitude characteristics: 3.88/3.28 MHz Bandpass amplitude characteristics: 4.08/3.08 MHz [Video Block] Video overall gain (at maximum contrast) Contrast adjustment characteristics (normal/max) Contrast adjustment characteristics (min/max) Video frequency characteristics: f0 = 3 Chrominance trap level: f0 = 0 DC restoration Luminance delay: f0 = 1 Maximum black stretch gain Black stretch threshold (40 IRE black) Sharpness variation range (normal) (max) (min) Horizontal/vertical blanking output level [OSD Block] OSD fast switch threshold RGB output level: red RGB output level: green RGB output level: blue Analog OSD output level Gain matching Linearity FSTH ROSDH GOSDH BOSDH RRGB LRRGB 1.7 120 70 85 1.12 45 1.9 165 120 120 1.4 50 2.2 200 140 155 1.68 60 V IRE IRE IRE Ratio % CONT63 CONT32 CONT0 Yf03 Ctrap ClampG YDLY BKSTmax BKSTTH Sharp16 Shaprp31 Shapr0 RGBBLK 95 480 12 -2 4 9.0 -6.0 1.4 10 -7.5 -15 -6.0 12 -6.0 -12 -3.5 -23 100 505 16 0 6 11.5 -3.5 1.7 14 -4.5 -9 0.0 -15 105 530 20 +2 8 14.0 -1.0 2.0 dB dB dB dB dB % ns IRE IRE dB dB dB V CPE308 CPE CPE05 CBP308 CBP CBP05 Referenced to 3.48 MHz Referenced to 3.28 MHz Referenced to 3.08 MHz Referenced to 3.48 MHz Referenced to 3.28 MHz Referenced to 3.08 MHz -5 -0.5 -5.0 -5 -2 -2.5 -3 +1.5 2.5 -3 0 0 -1 +3.5 -1 -1 +2 +2.5 dB dB dB dB dB dB Symbol ANGBR ANGGR KILL CVCOF PULIN+ PULIN- AF073 AF118 AF163 OVL1 OVL2 OVL3 8 -7 -30 3.2 4.2 4.5 20 0 -20 0 dB = 40IRE Deviation from 3.579545 MHz Conditions Ratings min 99 -146 -32 -250 350 -350 30 +7 -8 4.7 6.8 8.5 typ 104 -136 -26 max 109 -127 -22 +250 Unit deg deg dB Hz Hz Hz deg deg deg Continued on next page. No. 5841-13/39 LA7615 Continued from preceding page. Parameter Analog OSD green output level Gain matching Linearity Analog OSD blue output level Gain matching Linearity [RGB Output (cutoff and drive) Block] Brightness control (normal) High brightness (max) Low brightness (min) Cutoff control (min) BRT32 BRT63 BRT60 Vbias0 Vbias128 Vbiassns Vsbiassns RGBout63 RGBout0 2.0 15 -25 1.6 2.8 3 160 2.4 7 2.35 20 -20 2.0 3.2 4 220 3.0 9 2.7 25 -5 2.4 3.6 6 280 3.6 11 V IRE IRE V V mV/bit mV/bit Vp-p dB Symbol GRGB LGRGB BRGB LBRGB Conditions Ratings min 0.8 45 0.8 45 typ 1.0 50 1.0 50 max 1.2 60 1.2 60 Unit Ratio % Ratio % (bias control) (max) Cutoff contrad Resolution Sub-bias control resolution Drive adjustment: maximum output Output attenuation [Deflection Block] Sync separator circuit sensitivity Horizontal free-running frequency deviation Horizontal pull-in range Horizontal output pulse width @0 Horizontal output pulse width @1 Horizontal output pulse width @2 Horizontal output pulse width @3 Horizontal output pulse saturation voltage Horizontal output pulse phase Horizontal position adjustment range Horizontal position adjustment maximum variation X-ray protection circuit operating voltage POR circuit operating voltage [Vertical Screen Size Adjustment] Vertical ramp output amplitude @64 Vertical ramp output amplitude @0 Vertical ramp output amplitude @127 Ssync fH fH PULL Hduty0 Hduty1 Hduty2 Hduty3 VHsat HPHCEN HPHrange HPHstep VXRAY VPOR Vsize64 Vsize0 Vsize127 VSIZE : 1000000 VSIZE : 0000000 VSIZE : 1111111 VCOMP : 11 VDC : 1000000 VDC : 0000000 VDC : 1111111 VLIN : 1000 VLIN : 0000 VLIN : 1111 VS : 1000 VS : 0000 VS : 1111 2.7 5.5 4 bits 9.5 ON time, Hduty : 0 ON time, Hduty : 1 ON time, Hduty : 2 ON time, Hduty : 3 15.634 400 36.0 34.3 32.5 30.5 10 15.734 15 15.834 IRE kHz Hz 37.5 35.8 34.0 32.0 39.0 37.5 35.5 33.5 0.4 s s s s V s s 10.5 2 11.5 350 3.0 6.3 3.3 6.7 ns V V 1.44 0.72 2.14 1.74 1.02 2.44 2.04 1.32 2.64 Vp-p Vp-p Vp-p [High Voltage Dependency Vertical Size Correction] Vertical size correction @3 [Vertical Screen Position Adjustment] Vertical ramp DC voltage @32 Vertical ramp DC voltage @0 Vertical ramp DC voltage @63 Vertical linearity @8 Vertical linearity @0 Vertical linearity @15 Vertical S-curve correction @8 Vertical S-curve correction @0 Vertical S-curve correction @15 Vdc32 Vdc0 Vdc63 Vlin8 Vlin0 Vlin15 VScor8 VScor0 VScor15 3.686 3.344 4.104 0.93 0.77 1.13 0.77 0.92 0.62 3.876 3.557 4.294 0.985 0.84 1.18 0.84 1.00 0.72 4.484 3.762 4.484 1.04 0.92 1.25 0.92 1.08 0.78 Vdc Vdc Vdc ratio ratio ratio ratio ratio ratio Vsizecomp 0.96 0.97 0.98 ratio Continued on next page. No. 5841-14/39 LA7615 Continued from preceding page. Parameter [Horizontal Size Adjustment] East/west DC voltage @16 East/west DC voltage @0 East/west DC voltage @31 [Pin cushion Distortion Correction] East/west parabola amplitude @8 East/west parabola amplitude @0 East/west parabola amplitude @15 [Trapezoidal Distortion Correction] East/west parabola tilt @8 East/west parabola tilt @0 East/west parabola tilt @15 [Corner Distortion Correction] East/west parabola corner, top East/west parabola corner, bottom [Sandcastle Output] Burst gate pulse peak value Burst gate pulse phase Burst gate pulse width Blanking pulse peak value [D/A Converter Output] Pin 30 D/A converter voltage @0 Pin 30 D/A converter voltage @8 Pin 30 D/A converter voltage @15 VDAC0 VDAC8 VDAC15 +B TRIM : 0000 +B TRIM : 1000 +B TRIM : 1111 2.75 3.15 3.55 3.00 3.40 3.80 3.25 3.65 4.05 V V V VBGP TdBGP PWBGP VBLK 5.0 4.6 2.35 3.4 5.7 5.1 2.85 3.9 6.5 5.6 3.35 4.4 V s s V EWcorTOP EWcorTOP CORTOP : 111-000 CORBOTTOM : 111-000 0.15 0.15 0.25 0.25 0.35 0.35 V V EWtilt4 EWtilt0 EWtilt7 EWTILT : 1000 EWTILT : 0000 EWTILT : 1111 -0.14 -0.37 0.09 0 -0.23 0.23 +0.14 -0.09 0.37 V V V EWamp8 EWamp0 EWamp15 EWAMP : 1000 EWAMP : 0000 EWAMP : 1111 0.58 0.15 0.95 0.73 0.30 1.15 0.88 0.45 1.35 Vp-p Vp-p Vp-p EWdc16 EWdc0 EWdc31 EWDC : 10000 EWDC : 00000 EWDC : 11111 3.60 2.70 4.80 4.00 3.05 5.10 4.40 3.40 5.40 Vdc Vdc Vdc Symbol Conditions Ratings min typ max Unit Circuit Voltage and Current Test Conditions at Ta = 25C, VCC = V2 = V17 = V32 = V60 = 7.6 V, ICC = I24 = 24 mA Parameter [Circuit Voltage and Current] Horizontal supply voltage HVCC I2 (IFICC) Symbol Test point Input signal Test procedure Bus condition 24 2 17 32 60 No signal No signal Apply a 24-mA current to pin 24 and measure Initial the voltage on pin 24 at that time. Apply 7.6 V to pin 2 and measure the DC current (in mA) that flows into the IC. (With 5 V applied to the IF AGC) Apply 7.6 V to pin 17 and measure the DC current (in mA) that flows into the IC. Apply 7.6 V to pin 32 and measure the DC current (in mA) that flows into the IC. Apply 7.6 V to pin 60 and measure the DC current (in mA) that flows into the IC. Initial IF current drain (pin 2) Vertical current drain (pin 17) Video, chrominance, current drain (pin 32) FM power supply current (pin 60) I17 (DEFICC) I32 (YCVCC) I60 (FMVCC) Initial Initial Initial No. 5841-15/39 LA7615 VIF Block - Input Signals and Test Conditions 1. All input signals are input to VIF IN in the test circuit diagram. 2. The input signal voltages are all taken to be the voltage at VIF IN in the test circuit diagram. 3. The signals and their levels are as follows. Input signal Input signal SG1 Waveform 45.75 MHz Condition CW A10054 SG2 42.17 MHz CW A10055 SG3 41.25 MHz CW A10056 SG4 Variable frequency CW A10057 SG5 45.75 MHz 87.5% video modulation 10-step waveform (subcarrier: 3.58 MHz) A10058 SG6 45.75 MHz 40 IRE 50 IRE 87.5% video modulation Sweep signal (APL: 50 IRE, sweep signal level: 40 IRE) A10059 SG7 45.75 MHz 87.5% video modulation 100 IRE Flat field signal A10060 4. Before testing, adjust the D/A converter in the order presented below. Parameter APC DAC PLL DAC Video level DAC Trap Test point Input signal No signal, with pin 11 connected to ground SG1, 93 dB SG7, 93 dB SG6, 93 dB Adjustment Set the pin 14 DC voltage to be as close to 3.8 V as possible. Set the pin 14 DC voltage to be as close to 3.8 V as possible. Set the pin 53 output level to be 2.0 0.2 Vpp. Lower the D/A converter from its maximum (15) and set the circuit so that the 4.5 MHz component is at least -32 dB below the 100 kHz component. 14 14 53 53 No. 5841-16/39 LA7615 (Test Conditions) Parameter [VIF Block] No signal AFT output voltage No signal video output voltage V14 V53 Symbol Test point Input signal Test procedure Connect the pin 11 to ground and measure the pin 14 DC voltage. Connect the pin 11 to ground and measure the pin 53 DC voltage. Monitor pin 53 with an oscilloscope, and modify SG4 to have a frequency higher than 45.75 MHz so that the PLL goes to the unlocked state. (Beating should appear at this point.) Gradually decrease the SG4 frequency until the PLL circuit locks, and measure the lock frequency. Also, and modify SG4 to have a frequency lower than 45.75 MHz so that the PLL goes to the unlocked state. Gradually increase the SG4 frequency until the PLL circuit locks, and measure the lock frequency. Bus condition The adjusted values from item 4. The adjusted values from item 4. 14 53 No signal No signal APC pull-in range (U), (L) fPU, fPL 53 SG4 93 dB The adjusted values from item 4. Maximum RF AGC voltage Minimum RF AGC voltage Video output amplitude RF AGC Delay Pt (@DAC = 0) RF AGC Delay Pt (@DAC = 63) V4H V4L VO53 RFAGC0 4 4 53 4 4 SG1 91 dB SG1 91 dB SG7 93 dB SG1 Set the RF AGC D/A converter to 0 and measure the The adjusted values pin 4 DC voltage. from item 4. Set the RF AGC D/A converter to 63 and measure the pin 4 DC voltage. Monitor the pin 53 with an oscilloscope, and measure the peak-to-peak value of the waveform. Set the RF AGC D/A converter to 0 and determine the input level such that the pin 4 DC voltage becomes 3.8 0.5 V. Set the RF AGC D/A converter to 63 and determine the input level such that the pin 4 DC voltage becomes 3.8 0.5 V. The adjusted values from item 4. The adjusted values from item 4. The adjusted values from item 4. The adjusted values from item 4. RFAGC63 SG1 Input sensitivity VIN 53 SG7 Monitor the pin 53 with an oscilloscope, and measure the peak-to-peak value of the waveform. The adjusted values Gradually decrease the input level and determine the from item 4. input level such that the output goes down to a level lower than the video amplitude (VO 53) by -3 dB. Monitor the pin 53 with an oscilloscope, and measure the peak-to-peak values of the sync waveform (Vs) and the luminance signal (Vy) to determine the ratio Vy/Vs. Measure the pin 53 with a vectorscope. Measure the pin 53 with a vectorscope. The adjusted values from item 4. The adjusted values from item 4. The adjusted values from item 4. Video/Sync ratio (@100 dB) V/S 53 53 53 53 53 53 SG7 100 dB SG5 93 dB SG5 93 dB SG1 93 dB SG1 93 dB SG6 93 dB Differential gain Differential phase DG DP Video signal-to-noise ratio S/N Pass the noise voltage signal generated at pin 53 The adjusted values through a 4 to 10 MHz bandpass filter and measure that signal(Vsn) with an rms voltmeter. Determine the from item 4. value of the formula 20log(1.43/Vsn). Measure the pin 53 DC voltage. Measure the values of the 100 kHz and 4.5 MHz components and determine their ratio. The adjusted values from item 4. The adjusted values from item 4. Synchronizing signal tip level 4.5 MHz attenuation V53 TIP TRAP 920 kHz beat level I920 53 SG1 SG2 SG3 Input the 93 dB SG1 signal, and measure the pin 11 DC voltage (V11). Mix the three signals SG1 = 87 dB, SG2 = 82 dB, and SG3 = 63 dB, and input The adjusted values that signal to VIF IN. Apply the voltage V11 to pin 11 from item 4. using an external power supply. Measure the difflerence of the 3.58 MHz and 920 kHz components using a spectrum analyzer. Measure the pin 14 DC voltage. Maximum AFT output voltage V14H 14 14 SG4 93 dB 44.75 MHz SG4 93 dB 46.75 MHz SG4 93 dB Minimum AFT output voltage V14L Measure the pin 14 DC voltage. Gradually change the SG4 frequency and determined the frequency change f required to change the pin 14 DC voltage from 2.5 V to 5.0 V. Sf = 2500/f [mV/kHz] AFT detection sensitivity Sf 14 No. 5841-17/39 LA7615 First SIF Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. PIF.IN: 45.75 MHz, 93 dB, CW 2. Bus control conditions: Set the following 4 items to their adjusted values. (See the VIF block test description for details on the adjustment procedure.) * APC DET.ADJ * PLL tuning * 4.5 MHz trap * Video level 3. Apply the input signal to the pin 12, using a signal with a frequency of 41.25 MHz CW. Parameter Symbol Test point Input signal Test procedure Measure the pin 59 output 4.5 MHz component (mV rms). Let SV1 be this measured value and perform the following calculation. SCG = 20 x log(SV1 x 1000) - 60 [dB] Measure the pin 59 output 4.5 MHz component (mV rms). Let SV2 be this measured value and perform the following calculation. SCO = 20 x log(SV2 x 1000) [dB] Measure the pin 59 output 4.5 MHz component (mV rms). Let SV3 be this measured value and perform the following calculation. SCM = 20 x log(SV3/SV1) [dB] Bus condition 4.5 MHz conversion gain SCG 59 60 dB 4.5 MHz output level SVO 59 88 dB First SIF maximum input SVM 59 96 dB SIF Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. Connect pin 13 (SIF AGC) to ground. 2. Bus control conditions: IF.AGC.SW = 1. 3. SW:IF1 = off 4. Apply the input signal to pin 61. The carrier frequency should be 4.5 MHz. Parameter Symbol Test point Input signal 90 dB, fm = 1 kHz, FM = 25 kHz Test procedure Adjust the D/A converter (FM.LEVEL) so that the pin 5 FM detector output 1 kHz component is as close to 424 mV rms as possible. Measure the output (mV rms) at that time. Let SV1 be the measured value at this time. Determine the input level (dB) such that the pin 5 FM detector output 1 kHz component is down -3 dB from SV1. Determine the modulation frequency bandwidth (Hz) for a -3 dB drop in the pin 5 FM detector output 1 kHz component with respect to SV1. Determine the distortion in the pin 5 FM detector output 1 kHz component. Measure (in mV rms) the pin 5 FM detector output 1 kHz component. Let SV2 be the measured value at this time and perform the following calculation. SAMR = 20 x log(SV1/SV2) [dB] Set the SW:IF1 switch to the on state. Measure the noise level (mV rms) on pin 5. Let SV3 be the measured value at this time and perform the following calculation. SSN = 20 x log(SV1/SV3) [dB] FM.LEVEL = adjusted value. FM.LEVEL = adjusted value. FM.LEVEL = adjusted value. Bus condition FM detector output voltage SOADJ 5 FM limiting sensitivity SLS 5 5 5 fm = 1 kHz, FM = 25 kHz 90 dB, FM 25 kHz 90 dB, fm = 1 kHz, FM 25 kHz 90 dB, fm = 1 kHz, AM = 30% FM detector output bandwidth SF FM detector output distortion STHD AM rejection ratio SAMR 5 FM.LEVEL = adjusted value. SIF signal-to-noise ratio SSN 5 90 dB, CW FM.LEVEL = adjusted value. No. 5841-18/39 LA7615 Video Block - Input Signals and Test Conditions [Input Signals] [ 100 IRE : 714 mV ] Pedestal level H SYNC 4.7 s (H/V SYNC : 40 IRE : 286 mV) A10061 X IRE signal (L-X) X IRE (X = 0 to 100) 0 IRE A10062 CW signal (L-CW) 20 IRE CW signal 50 IRE A10063 Black stretch 0 IRE signal (L-BK) 50 s 100 IRE 5 s (Point A) A10064 20 s each 0.7 V A B 0.35 V 0.0 VDC A10065 RGB input signal 2 (O-2) 20 s 30 s 1.0 VDC 0.0 VDC A10066 No. 5841-19/39 LA7615 (Test Conditions) Parameter [Video Block] Overall video gain (at maximum contrast) Contrast adjustment characteristics (normal/max) Contrast adjustment characteristics (normal/max) Video frequency characteristics f0 = 1 (sharp 0) CONT63 Symbol Test point Input signal Test procedure Bus bits/input signal 38 38 38 L-50 Measure the output signal 50 IRE amplitude (CNTHB TR24: Contrast Vp-p) and calculate CONT63 = 20log(CNTHB/0.357). 111111 Measure the output signal 50 IRE amplitude (CNTCB Vp-p) and calculate CONT32 = 20log(CNTCB/0.357). Measure the output signal 50 IRE amplitude (CNTLB Vp-p) and calculate CONT0 = 20log(CNTLB/0.357). With the input signal CW = 100 kHz, measure the amplitude of the CW signal in the output signal (PEAKDC Vp-p). With the input signal CW = 10 MHz, measure the amplitude of the CW signal in the output signal (F03 Vp-p). Calculate Yf3 = 20log(F03/PEAKDC). TR24: Contrast 000000 CONT32 L-50 CONT0 L-50 Yf03 L-CW TR26: F0 Adjust 01 TR26: F0 Adjust 11 TR25: Sharpness 01111 38 f0 = 3 (sharp 15) Chrominance trap level f0 = 0 (sharp 0) Ctrap 38 L-CW With the input signal CW = 3.58 MHz, measure the amplitude of the CW signal in the output signal (F00 Vpp). Calculate Ctrap = 20*log(F00/PEAKDC). Measure the output signal 0 IRE DC level (BRTPL (V)). Measure the output signal 0 IRE DC level (DRVPH (V)) and the 100 IRE amplitude (DRVH Vpp). Calculate ClampG = 100 x (1 + (DRVPH - BRTPL)/DRVH)). Measure the time difference (amount of delay) between the rise of the input signal 50 IRE amplitude, and rise of the output signal 50 IRE amplitude. Measure the 0 IRE DC level at point A in the output signal when the black stretch function is defeated (black stretch off). (BKST1 (V)) TR26: F0 Adjust 00 L-0 DC restoration ClampG 38 L-100 TR23: Brightness 000000 TR24: Contrast 111111 TR23: Brightness 000000 TR24: Contrast 111111 Luminance delay f0 = 1 YDLY 38 L-50 TR31: BKST Defeat 1 TR31: BKST Defeat 0 Maximum black stretch gain BKSTmax 38 L-BK Measure the 0 IRE DC level at point A in the output signal when the black stretch function is on. (BKST2 (V)) Calculate BKSTmax = 2 x 50 x (BKST1 - BKST2)/CNTHB. Measure the 40 IRE DC level in the output signal when the black stretch function is on. (BKST3 (V)) TR31: BKST Defeat 0 TR31: BKST Defeat 1 Black stretch threshold black(40 IRE black) BKSTTH 38 L-40 Measure the 40 IRE DC level in the output signal when the black stretch function is defeated (black stretch off). (BKST4 (V)) Calculate BKSTTH = 50 x (BKST4 - BKST3)/CNTHB. Sharpness (peaking) variability characteristics (normal) Sharp16 L-CW With the input signal CW = 2.2 MHz, measure the amplitude of the CW signal in the output signal (F00S16 Vp-p). Calculate Sharp16 = 20log(F00S16/PEAKDC). With the input signal CW = 2.2 MHz, measure the amplitude of the CW signal in the output signal (F00S31 Vp-p). Calculate Sharp31 = 20log(F00S31/PEAKDC). With the input signal CW = 2.2 MHz, measure the amplitude of the CW signal in the output signal (F00S0 Vp-p). Calculate Sharp0 = 20log(F00S0/PEAKDC). TR26: F0 Adjust 00 TR25: Sharpness 10000 (maximum) Sharp31 38 L-CW TR25: Sharpness 11111 (minimum) Sharp0 L-CW TR25: Sharpness 00000 Horizontal/vertical blanking output level RGBBLK 38 L-100 Measure the DC level of the output signal during the blanking period (RGBBLK (V)). Continued on next page. No. 5841-20/39 LA7615 Continued from preceding page. Parameter [OSD Block] OSD fast switching threshold FSTH Symbol Test point Input signal Test procedure Bus bits/input signal 38 L-0 O-2 L-50 Gradually increase the pin 39 voltage starting at 1.5 V, and determine the pin 39 voltage at the point where the output signal switches to the OSD signal. Measure the 50 IRE amplitude in the output signal. (CNTCR Vp-p). Measure the OSD output amplitude (OSDHR Vp-p). Calculate ROSDH = 50 x (OSDHR/CNTCR). Pin 42: Apply signal O-2. RGB red output level ROSDH 36 L-0 O-2 Pin 39: Apply 3.5 V. Pin 40: Apply signal O-2. L-50 RGB green output level GOSDH Measure the 50 IRE amplitude in the output signal. (CNTCG Vp-p). Measure the OSD output amplitude (OSDHG Vpp). Calculate GOSDH = 50 x (OSDHG/CNTCG). Pin 39: Apply 3.5 V. Pin 41: Apply signal O-2. 37 L-0 O-2 L-50 RGB blue output level BOSDH Measure the 50 IRE amplitude in the output signal. (CNTCB Vp-p). Measure the OSD output amplitude (OSDHB Vp-p). Calculate BOSDH = 50 x (OSDHB/CNTCB). Measure the amplitudes at point A (the 0.35 V component of the input signal O-1) and point B (the 0.7 V component of the input signal O-1) in the output signal and record these as RGBLR and RGBHR (Vp-p) respectively. Calculate RRGB = RGBLR/CNTCR. Calculate LRRGB = 100 x (RGBLR/RGBHR). Measure the amplitudes at point A (the 0.35 V component of the input signal O-1) and point B (the 0.7 V component of the input signal O-1) in the output signal and record these as RGBLG and RGBHG (Vp-p) respectively. Calculate GRGB = RGBLG/CNTCG. Calculate LGRGB = 100 x (RGBLG/RGBHG). Measure the amplitudes at point A (the 0.35 V component of the input signal O-1) and point B (the 0.7 V component of the input signal O-1) in the output signal and record these as RGBLB and RGBHB (Vp-p) respectively. Calculate BRGB = RGBLB/CNTCB. Calculate LBRGB = 100 x (RGBLB/RGBHB). Pin 39: Apply 3.5 V. Pin 41: Apply signal O-1. Pin 39: Apply 3.5 V. Pin 34: Apply signal O-1. Pin 39: Apply 3.5 V. Pin 40: Apply signal O-1. Pin 39: Apply 3.5 V. Pin 42: Apply signal O-2. 38 L-0 O-2 Analog OSD red output level 36 RRGB LRRGB L-0 O-1 Gain matching Linearity Analog OSD green output level 37 GRGB LGRGB L-0 O-1 Gain matching Linearity Analog OSD blue output level 38 BRGB LBRGB L-0 O-1 Gain matching Linearity [RGB Output Block] (Cutoff and Drive Blocks) Brightness control (normal) 36 BRT32 L-0 37 38 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as BRTPCR, BRTPCG, and BRTPCB (V), respectively. Calculate BRT63 = (BRTPCR + BRTPCG + BRTPCB)/3. Measure the output signal 0 IRE DC level of the B output (pin 38) (BRTPHB). Calculate BRT63 = 50 x (BRTPHB - BRTPCB) / CNTHB. Measure the output signal 0 IRE DC level of the B output (pin 38) (BRTPLB). Calculate BRT0 = 50 x (BRTPLB - BRTPCB) / CNTHB. TR24: Contrast 111111 (maximum) BRT63 TR23: Brightness 111111 38 (minimum) BRT0 TR23: Brightness 000000 Continued on next page. No. 5841-21/39 LA7615 Continued from preceding page. Parameter [RGB Output Block] (Cutoff and Drive Blocks) Bias (cutoff) control (minimum) Vbias0 L-50 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as Vbias0* (V), where * : R, G, and B, respectively. TR24: CONTRAST 111111 TR22: SUB-BIAS R, G, B 000000 TR16: R BIAS 111111 TR: G BIAS 111111 TR18: B BIAS 111111 TR24: CONTRAST 111111 TR22: SUB-BIAS R, G, B 111111 TR16: R BIAS 1010000 TR17: G BIAS 1010000 TR18: B BIAS 1010000 TR24: CONTRAST 111111 TR16: R BIAS 0110000 TR17: G BIAS 0110000 TR18: B BIAS 0110000 TR24: CONTRAST 11111 Symbol Test point Input signal Test procedure Bus bits/input signal (maximum) Vbias128 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as Vbias128* (V), where * : R, G, and B, respectively. 36 37 38 Bias (cutoff) control resolution Vbiassns Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as BAS48* (V), where * : R, G, and B, respectively. Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as BAS80* (V), where * : R, G, and B, respectively. Vbiassns * = (BAS80 * - BAS48 *)/32 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as SBTPM* (V), where * : R, G, and B, respectively. Vsbiassns * = (BRTPC * - SBTPM *) Maximum drive adjustment output Measure the output signal 100 IRE DC amplitudes of TR24: CONTRAST 111111 the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as DRVH* (Vpp), where * : TR23: Brightness 000000 R, G, and B, respectively. TR22: SUB-BIAS R, G, B 101010 Sub-bias control resolution Vsbiassns L-50 RGBout63 36 37 Output attenuation RGBout0 L-100 38 TR24: CONTRAST 111111 TR23: Brightness 000000 Measure the output signal 100 IRE DC amplitudes of the R output (pin 36), G output (pin 37), and B output TR19: R DRIVE 000000 (pin 38) and record these as DRVL* (Vpp), where * : TR20: G DRIVE R, G, and B, respectively. 000000 TR21: B DRIVE 000000 RGBout0 * = 20 log(DRVH */DRVL *) No. 5841-22/39 LA7615 Chrominance Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. VIF and SIF blocks: No signal 2. Deflection block: Input a horizontal/vertical composite sync signal and verify that the deflection block is locked on the synchronizing signal. (See the section on input signals and test conditions for the deflection block.) 3. Bus control conditions: All conditions set to their initial values, unless otherwise specified. 4. Connect a crystal oscillator circuit to pin 16. Adjust the impedance (Z) of the series capacitance and resistance as shown below. Z = 0 deg @ 3.579545 MHz 10 Hz -40 1 deg @3.579345 MHz 5. Luminance (Y) input: No signal 6. Chrominance (C) input: Input the signal to the C1IN pin (pin 51). 7. The method for calculating the demodulation angle is shown below. B-Y axis angle = tan - 1 (B(0)/B(270)) + 270 R-Y axis angle = tan - 1 (R(180)/R(90)) + 90 G-Y axis angle = tan - 1 (G(270)/G(180)) + 180 R-Y axis 90 R (90) R (180) B (270) 180 G (180) G (270) B (0) 0 B-Y axis 270 G-Y axis A10067 8. The method for calculating the AF angle is shown below. BR * * * * The B-Y/R-Y demodulation output ratio * * * * * * ANGBR: the B-Y/R-Y demodulation angle AFXXX = tan - 1 R - Y/B - Y x BR - Cos ---------------------- Sin No. 5841-23/39 LA7615 [Input Signal] C-1 Burst 0 90 180 270 3.58 MHz 40 IRE A10068 77IRE X IRE signal (L-X) 0 IRE A10069 40IRE C-2 Burst 62.5IRE 3.58 MHz 364 A10070 C-3 Burst 40 IRE 3.48 MHz (However, when a frequency is specified, that frequency is to be used.) CW A10071 C-4 28 73 118 163 40 IRE A10072 35 s C-5 Burst 3.48 MHz Chroma A10073 No. 5841-24/39 LA7615 (Test Conditions) Parameter [Chrominance Block] Bout ACC amplitude characteristics 1 ACCM1 C-1 0 dB +6 dB Measure the output amplitude when the chrominance input is set to 0 dB and the output amplitude when the input is reduced by - 6 dB, and calculate the ratio. ACCM1 = 20log(+6 dB data/0 dB data) Measure the output amplitude when the chrominance input is set to -14 dB and calculate the ratio. ACCM2 = 20log(-14 dB data/0 dB data) Measure the luminance (Y) output level(V1). Next, apply a signal to the CIN input (with only a sync applied to the Y input) and measure the output level (V2). Calculate the following formula. CLRBY = 100 x (V2/V1) +15% Measure V1: the output amplitude when the color control is maximum, and V2: the output amplitude when the color control is normal (Color control: 1000000) and calculate CLRMN = V1/V2. Measure V3: the output amplitude when the color control is minimum and calculate CLRMM = 20*log(V1/V3). Measure V4: the output amplitude when the color control is 90, and V5: the output amplitude when the color control is 38. Calculate the following formula. CLRSE = 100 x (V4 - V5) / (V2 x 52) Measure each section of the output waveform and calculate the angle of the B-Y axis. Measure each section of the output waveform and calculate the angle of the B-Y axis. Calculate the following formula. TINMAX = (the B-Y axis angle) - TINCEN Measure each section of the output waveform and calculate the angle of the B-Y axis. Calculate the following formula. TINMIN = (the B-Y axis angle) - TINCEN Measure A1: the angle when the tint control is 85, and A2: the angle when the tint control is 42. Calculate the following formula. TINSE = (A1 - A2)/43 Measure Vb: the BOUT output amplitude and Vr: the ROUT output amplitude, and calculate BR = Vb/Vr. Measure Vg: the GOUT output amplitude and calculate GR = Vg/Vr. TR28: Color Control 1111111 1000000 TR28: Color Control 0000000 TR28: Color Control 1011010 Color Ctontrol 0100110 TR27: TINT 0111111 TR27: TINT 1111111 Symbol Test point Input signal Test procedure Bus condition 38 Bout ACC amplitude characteristics 2 ACCM2 38 C-1 -14 dB YIN: L77 C-1: No signal B-Y/Y amplitude ratio CLRBY 38 C-2 Color control characteristics 1 CLRMN 38 C-3 Color control characteristics 2 CLRMM 38 C-3 Color control sensitivity CLRSE 38 38 38 C-3 Tint center TINCEN C-1 Tint control (max) TINMAX C-1 Tint control (min) TINMIN 38 C-1 TR27: TINT 0000000 Tint control sensitivity TINSE 38 38 C-1 TR27: TINT 1010101 0101010 Demodulation output ratio B-Y/R-Y Demodulation output ratio G-Y/R-Y BR C-3 36 GR TR28: Color Control 1000000 TR28: Color Control 1000000 37 C-3 Continued on next page. No. 5841-25/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Measure the BOUT and ROUT output levels and calculate the angle between the B-Y and R-Y axes. Calculate ANGBR = (R-Y angle) - (B-Y angle). Measure the GOUT output level and calculate the angle between the G-Y and R-Y axes. Calculate ANGGR = (R-Y angle) - (G-Y angle). Gradually decrease the amplitude of the input signal and measure the input level when the output level falls less than 150 mVpp. Measure the oscillator frequency f and calculate the following formula. CVCOF = f - 3579545 (Hz) Gradually decrease the input signal subcarrier frequency starting at 3.579545 MHz + 1000 Hz, and measure frequency at the point the output waveform locks. Gradually raise the input signal subcarrier frequency starting at 3.579545 MHz - 1000 Hz, and measure frequency at the point the output waveform locks. With Auto Flesh = 0, measure the level that corresponds to a BOUT and ROUT output waveform of 73 and calculate TR26: Auto Flesh : the angle AF073A. **** 0 ** With Auto Flesh = 1, measure the angle AF073B in the TR26: Auto Flesh : same manner. **** 1 ** Calculate the following formula. AF073 = AF073B - AF073A With Auto Flesh = 0, measure the level that corresponds to a BOUT and ROUT output waveform of 118 and calculate the angle AF118A. With Auto Flesh = 1, measure the angle AF118B in the same manner. Calculate the following formula. AF118 = AF118B - AF118A With Auto Flesh = 0, measure the level that corresponds to a BOUT and ROUT output waveform of 163 and calculate the angle AF163A. With Auto Flesh = 1, measure the angle AF163B in the same manner. Calculate the following formula. AF163 = AF163B - AF163A Measure V1: the output amplitude when the input signal burst level is set to 40 IRE and the chrominance level is set to 8 IRE, and V2: the output amplitude when the input signal burst level is set to 40 IRE and the chrominance level is set to 40 IRE. Calculate the following formula. OVL1 = V2/V1 Bus condition 38 Demodulation angle B-Y/R-Y ANGBR C-1 36 37 C-1 Demodulation angle G-Y/R-Y ANGGR Killer operating point KILL 38 16 38 38 C-3 Chrominance VCO free-running frequency Chrominance pull-in range (+) CVCOF PULIN+ CIN No signal C-1 Chrominance pull-in range (-) PULIN- C-1 38 Auto Flesh characteristics 73 AF073 C-4 36 38 Auto Flesh characteristics 118 AF118 C-4 36 TR26: Auto Flesh : **** 0 ** TR26: Auto Flesh : **** 1 ** 38 Auto Flesh characteristics 163 AF163 C-4 36 TR26: Auto Flesh : **** 0 ** TR26: Auto Flesh : **** 1 ** Overload characteristics 1 OVL1 36 C-5 TR26: OverLoad : ****** 1 Continued on next page. No. 5841-26/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Measure V3: the output amplitude when the input signal burst level is set to 40 IRE and the chrominance level is set to 80 IRE. Calculate the following formula. OVL2 = V3/V1 Measure V4: the output amplitude when the input signal burst level is set to 20 IRE and the chrominance level is set to 80 IRE. Calculate the following formula. OVL3 = V4/V1 Bus condition Overload characteristics 2 OVL2 36 C-5 TR26: Overload ******1 Overload characteristics 3 OVL3 36 C-5 TR26: Overload ******1 [Chrominance Bandpass Filter Characteristics] Measure V0: the output amplitude. Next, set the input chrominance signal (CW) frequency to 3.08 MHz and measure V1: the output amplitude. Calculate the following formula. CPE308 = 20log(V1/V0) Measure V2: the output amplitude when the input chrominance signal (CW) frequency is 3.28 MHz, and V3: the output amplitude when the input chrominance signal (CW) frequency is 3.88 MHz. Calculate the following formula. CPE = 20log(V3/V2) Measure V4: the output amplitude when the input chrominance signal (CW) frequency is 4.08 MHz. Calculate the following formula. CPE05 = 20log(V4/V1) Measure V5: the output amplitude. Next, measure V6: the output amplitude when the input chrominance signal (CW) frequency is set to 3.08 MHz. Calculate the following formula. CPE308 = 20log(V6/V5) Measure V7: the output amplitude when the input chrominance signal (CW) frequency is 3.28 MHz, and V8: the output amplitude when the input chrominance signal (CW) frequency is 3.88 MHz. Calculate the following formula. CPE = 20log(V8/V7) Measure V9: the output amplitude when the input chrominance signal (CW) frequency is set to 4.08 MHz. Calculate the following formula. CPE05 = 20log(V9/V6) Peaking amplitude characteristics: 3.08 MHz CPE308 38 C-3 TR26: CHR.BPF: ***1*** Peaking amplitude characteristics: 3.88/3.28 MHz CPE 38 C-3 TR26: CHR.BPF: ***1*** Peaking amplitude characteristics: 4.08/3.08 MHz CPE05 38 C-3 TR26: CHR.BPF: ***1*** Bandpass amplitude characteristics: 3.08 MHz CBE308 38 C-3 TR26: CHR.BPF: ***0*** Bandpass amplitude characteristics: 3.88/3.28 MHz CBE 38 C-3 TR26: CHR.BPF: ***0*** Bandpass amplitude characteristics: 4.08/3.08 MHz CBE05 38 C-3 TR26: CHR.BPF: ***0*** No. 5841-27/39 LA7615 Deflection Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. VIF and SIF blocks: No signal 2. Luminance (Y) input and chrominance (C) input: No signal 3. Sync input: Horizontal/vertical composite sync signal (DC offset: 3.8 V, 40 IRE. Other timing and other parameters must conform to the FCC broadcast standards.) Caution: There must be no burst or chrominance signal under the pedestal level. Signal inappropriate for use as a sync input Signal appropriate for use as a sync input Chrominance signal Burst signal A10074 4. Bus control conditions: All conditions set to their initial values, unless otherwise specified. 5. The delay time from the rise of the horizontal output (the pin 26 output) to the rise of the F.B.P IN (pin 27 input) must be 9 s. 6. The pin 18 (the vertical size correction circuit input pin) voltage must be VCC (7.6 V). 7. Pin 28 (the x-ray protection circuit input pin) must be connected to ground. Notes: Perform the following operations if the horizontal output pulse signal was stopped. 1. Set the bus on/off bit to off (0) temporarily, and then set it to on (1) again. (If the x-ray protection circuit and/or the PON-RES circuit operate, an IC internal latch circuit will be set. The on/off bit must be set to off (0) to reset that latch circuit, even if the horizontal output signal is not output. Since the PONRES circuit operates when the horizontal supply voltage rises, the on/off bit must be set to off (0).) 2. Note on video muting If the horizontal output pulse signal was stopped, after performing the operation described in paragraph 1 above, clear the video muting bit to 0. (This is because the video muting bit is forcibly set to 1 when the on/off bit is set to 0 or when either the x-ray protection circuit or the PON-RES circuit operate. This also applies at power on.) No. 5841-28/39 LA7615 Parameter [Deflection Block] SYNC IN: horizontal and vertical synchronizing signal Gradually decrease the level of the synchronizing signal input to SYNC IN (pin 44) and measure the level of the synchronizing signal when the synchronization is unlocked. Connect the pin 26 output (Hout) to a frequency counter and measure the horizontal free-running frequency. Calculate the following formula. fH = Sync separator circuit sensitivity Ssync 44 Horizontal free-running frequency deviation fH 26 SYNC IN: no signal Horizontal pull-in range fH PULL 44 SYNC IN: horizontal and vertical synchronizing signal SYNC IN: horizontal and vertical synchronizing signal SYNC IN: horizontal and vertical synchronizing signal SYNC IN: horizontal and vertical synchronizing signal SYNC IN: horizontal and vertical synchronizing signal SYNC IN: horizontal and vertical synchronizing signal Horizontal output pulse width @0 Hduty 0 26 Measure the low-level period in the pin 26 horizontal pulse waveform. HDUTY: 00 Horizontal output pulse width @1 Hduty 1 26 Measure the low-level period in the pin 26 horizontal pulse waveform. HDUTY: 01 Horizontal output pulse width @2 Hduty 2 26 Measure the low-level period in the pin 26 horizontal pulse waveform. Horizontal output pulse width @3 Hduty 3 26 Measure the low-level period in the pin 26 horizontal pulse waveform. HDUTY: 11 Horizontal output pulse saturation voltage VHsat 26 Measure the voltage during low-level period in the pin 26 horizontal pulse waveform. Measure the delay time from the rise of the pin 26 horizontal output pulse waveform to the fall of the SYNC IN horizontal synchronizing signal. Horizontal output pulse phase HPHCEN 26 44 SYNC IN: horizontal and vertical synchronizing signal HPHCEN 20 IRE Horizontal output 3.8V A10075 Continued on next page. No. 5841-29/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Measure the delay time from the rise of the pin 26 horizontal output pulse to the fall of SYNC IN horizontal synchronizing signal with HPHASE set to both 0 and 15 and calculate the difference with respect to HPHCEN. Measurement Horizontal position adjustment range SYNC IN: horizontal and vertical synchronizing signal Bus condition 26 HPHrange 44 20 IRE HPHASE: 0000 HPHASE: 1111 Horizontal output 3.8V A10076 Measure the delay time from the rise of the pin 26 horizontal output pulse to the fall of SYNC IN horizontal synchronizing signal while varying HPHASE from 0 to 15, and measure the amount of variation at each step. Find the step with the largest value of the data. SYNC IN: horizontal and vertical synchronizing signal Measurement HPHASE: 0000 to HPHASE: 1111 Maximum horizontal position adjustment variability HPHstep 26 44 20 IRE Horizontal output A10077 X-ray protection circuit operating VXRAY voltage 26 28 24 SYNC IN: horizontal and vertical synchronizing signal SYNC IN: horizontal and vertical synchronizing signal Connect a DC voltage source to pin 28, and gradually increase that voltage starting at 0 V. Measure the pin 28 DC voltage at the point the pin 26 horizontal output pulse stops. Replace the current source connected to pin 24 with a DC voltage source, and gradually decrease the voltage starting at 7.3 V. Measure the pin 24 DC voltage at the point the pin 26 horizontal output pulse stops. Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate the following formula. Vsize64 = Vline262 - Vline22 Vertical ramp output 262nd line POR circuit operating voltage VPOR 26 [Vertical Screen Size Adjustment] Vertical ramp output amplitude @64 Vsize64 19 SYNC IN: horizontal and vertical synchronizing signal 22nd line A10078 Continued on next page. No. 5841-30/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate the following formula. Vsize0 = Vline262 - Vline22 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output VSIZE: 0000000 262nd line Bus condition Vertical ramp output amplitude @0 Vsize0 19 22nd line A10079 Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate the following formula. Vsize0 = Vline262 - Vline22 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output VSIZE: 1111111 262nd line Vertical ramp output amplitude @127 Vsize127 19 22nd line [High-Voltage Dependency Vertical Size Correction] A10080 Vertical size correction @7 (maximum) Vsizecomp 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate Va from the following formula. Va = Vline262 - Vline22 Next, apply 3.8 V to pin 18, and once again measure the voltages at the 22nd line and at the 262nd line. Calculate Vb from the following formula. Vb = Vline262 - Vline22 Finally, calculate Vsizecomp from the following formula. Vsizecomp = (Va - Vb)/Va x 100 Monitor the pin 19 vertical ramp output and measure the voltage at the 142nd line. VCOMP: 111 [Vertical Screen Position Adjustment] Vertical ramp DC voltage @32 Vdc32 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output 142nd line A10081 Monitor the pin 19 vertical ramp output and measure the voltage at the 142nd line. SYNC IN: horizontal and vertical synchronizing signal Vertical ramp DC voltage @0 Vdc0 19 Vertical ramp output VDC: 000000 142nd line A10082 Continued on next page. No. 5841-31/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Monitor the pin 19 vertical ramp output and measure the voltage at the 142nd line. SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output VDC: 111111 Bus condition Vertical ramp DC voltage @63 Vdc63 19 142nd line A10083 Vertical linearity @8 Vlin8 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line, the 142nd line, and the 262nd line. Let Va, Vb, and Vc be these measurements, and calculate the following formula. Vline8 = (Vb - Va)/(Vc - Va) 262nd line Vertical ramp output 142nd line 22nd line A10084 Vertical linearity @0 Vlin0 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line, the 142nd line, and the 262nd line. Let Va, Vb, and Vc be these measurements, and calculate the following formula. Vline0 = (Vb - Va)/(Vc - Va) 262nd line Vertical ramp output VLIN: 0000 142nd line A10085 22nd line Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line, the 142nd line, and the 262nd line. Let Va, Vb, and Vc be these measurements, and calculate the following formula. Vline15 = (Vb - Va)/(Vc - Va) 262nd line Vertical ramp output VLIN: 1111 Vertical linearity @15 Vlin15 19 SYNC IN: horizontal and vertical synchronizing signal 142nd line 22nd line A10086 Continued on next page. No. 5841-32/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Monitor the pin 19 vertical ramp output and measure the voltages at the 32nd line, the 52nd line, the 132nd line, the 152nd line, the 232nd line, and the 252nd line. Let Va, Vb, Vc, Vd, Ve, and Vf be these measurements, and calculate the following formula. VScor8 = 0.5[(Vb - Va) + (Vf - Ve)] / (Vd - Vc) SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output 252nd line 232nd line 152nd line Bus condition Vertical S-curve correction @8 VScor8 19 VS: 1000 132nd line 52nd line 32nd line A10087 Monitor the pin 19 vertical ramp output and measure the voltages at the 32nd line, the 52nd line, the 132nd line, the 152nd line, the 232nd line, and the 252nd line. Let Va, Vb, Vc, Vd, Ve, and Vf be these measurements, and calculate the following formula. VScor0 = 0.5[(Vb - Va) + (Vf - Ve)] / (Vd - Vc) SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output 252nd line 232nd line 152nd line Vertical S-curve correction @0 VScor0 19 132nd line 52nd line 32nd line A10088 Vertical S-curve correction @15 VScor15 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 32nd line, the 52nd line, the 132nd line, the 152nd line, the 232nd line, and the 252nd line. Let Va, Vb, Vc, Vd, Ve, and Vf be these measurements, and calculate the following formula. VScor15 = 0.5[(Vb - Va) + (Vf - Ve)] / (Vd - Vc) Vertical ramp output 252nd line 232nd line 152nd line VS: 1111 132nd line 52nd line 32nd line A10089 Continued on next page. No. 5841-33/39 LA7615 Parameter [Horizontal Size Adjustment] Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 142nd line. SYNC IN: horizontal and vertical synchronizing signal East/west output 142nd line Symbol Test point Input signal Test procedure Bus condition East/west DC voltage @16 EWdc16 21 A10090 Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 142nd line. SYNC IN: horizontal and vertical synchronizing signal East/west output 142nd line EWDC: 00000 East/west DC voltage @0 EWdc0 21 A10091 Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 142nd line. SYNC IN: horizontal and vertical synchronizing signal East/west output 142nd line EWDC: 11111 East/west DC voltage @31 EWdc31 21 A10092 [Pin-Cushion Distortion Correction] Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 142nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp8 = Vb - Va East/west output 142nd line East/west parabola amplitude @8 EWamp8 21 SYNC IN: horizontal and vertical synchronizing signal 22nd line A10093 East/west parabola amplitude @0 EWamp0 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 142nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp0 = Vb - Va East/west output EWAMP: 0000 142nd line 22nd line A10094 Continued on next page. No. 5841-34/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 142nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp15 = Vb - Va East/west output EWAMP: 1111 142nd line Bus condition East/west parabola amplitude @15 EWamp15 21 SYNC IN: horizontal and vertical synchronizing signal 22nd line A10095 [Trapezoidal Distortion Correction] Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 262nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp8 = Va - Vb East/west output 262nd line East/west parabola tilt @8 EWtilt8 21 SYNC IN: horizontal and vertical synchronizing signal 22nd line A10096 East/west parabola tilt @0 EWtilt0 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 262nd line. Let Va and Vb be these measurements, and calculate the following formula. EWtilt0 = Va - Vb East/west output 262nd line EWTILT: 0000 22nd line A10097 East/west parabola tilt @15 EWtilt15 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 262nd line. Let Va and Vb be these measurements, and calculate the following formula. EWtilt15 = Va - Vb East/west output 262nd line EWTILT: 1111 22nd line A10098 Continued on next page. No. 5841-35/39 LA7615 Continued from preceding page. Parameter [Corner Distortion Correction] Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 22nd line under the conditions with CORTOP set to 111 and to 000. Let Va and Vb be these measurements. Calculate the following formula. EWcortop = Va - Vb East/west output CORTOP: 111-000 Symbol Test point Input signal Test procedure Bus condition East/west parabola corner: Top EWcortop 21 SYNC IN: horizontal and vertical synchronizing signal 22nd line A10099 East/west parabola corner: Bottom EWcorbot 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 262nd line under the conditions with CORBOT set to 111 and to 000. Let Va and Vb be these measurements. Calculate the following formula. EWcorbot = Va - Vb East/west output CORBOTTOM: 111-000 262nd line A10100 [Sandcastle Output] Measure the pin 29 output burst gate pulse peak value. SYNC IN: horizontal and vertical synchronizing signal Pin 29 output VBGP Burst gate pulse peak value VBGP 29 BGP A10101 Measure the delay time from the rise of the horizontal synchronizing signal to the rise of the pin 29 burst gate pulse. Burst gate pulse phase TdBGP 29 44 SYNC IN: horizontal and vertical synchronizing signal Horizontal synchronizing signal Pin 29 output TdBGP BGP A10102 Measure the width of the pin 29 burst gate pulse. Burst gate pulse width PWBGP 29 SYNC IN: horizontal and vertical synchronizing signal Pin 29 output BGP PWBGP A10103 Continued on next page. No. 5841-36/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Measure the peak value of the pin 29 output blanking pulse. Bus condition Blanking pulse peak value VBLK 29 SYNC IN: horizontal and vertical synchronizing signal Pin 29 output VBLK Blanking pulse A10104 [D/A Converter Output] Pin 30 D/A converter output voltage @0 Pin 30 D/A converter output voltage @8 Pin 30 D/A converter output voltage @15 VDAC0 VDAC8 VDAC15 30 30 30 Measure the pin 30 D/A converter output DC voltage. Measure the pin 30 D/A converter output DC voltage. Measure the pin 30 D/A converter output DC voltage. +BTRIM: 0000 +BTRIM: 1111 No. 5841-37/39 61 60 59 56 55 54 53 51 50 48 47 46 44 42 41 40 39 38 37 36 R69 100 R68 R53 R52 R51 75 75 75 R49 R74 0.01 F C55 1 F R65 R70 R64 R61 75 R59 75 24 k 75 75 C58 50 0.01 F C56 Test Circuit Diagram R57 R63 100 100 C43 C59 1 F 100 pF + + 1 F +7.6 V 1 F 1 F 47 pF R48 R47 C41 C40 C39 R46 C37 16 k 16 k 16 k + 1100 +7.6 V R62 15 k 1 F R58 C50 R50 M C52 +7.6 V R60 470 k L102 100 pF 560 C53 R56 75 + 100 10 F C48 C45 C49 1 F 10 k 100 pF C44 1 F C36 0.01 F 100 pF R67 2 k 100 pF + R62 C42 15 k C47 22 F R54 64 63 62 VCO VCO F0 TANK1 TANK2 FILTER 51 C1 IN 50 Y1 IN 49 CHROMA KILLER 48 C2 IN 47 46 45 44 Y2 SELECTED SYNC IN Y ADAPTIVE IN OUT CORING 43 BLACK LEVEL DET 42 BLU IN 41 GRN IN 40 RED IN 39 FAST SWITCH IN 38 BLU OUT 37 GRN OUT 2.2 F C46 680 k + + 1 F C38 + + + + 61 SND IF IN 60 FM VCC 59 SND IF OUT 58 BUS GND 57 56 EQ VIDEO FILTER OUT 55 BUS DATA 54 53 52 BUS SELECTED TEST IT CLOCK VIDEO OUT FILTER 36 RED OUT 35 34 33 BRT CONTRAST VID/ ABL (PIX) CHROMA FILT GND ABL FILT LA7615 PIF AGC1 10 +7.6 V +7.6 V +9 V + FM DISCRI 1 0.01 F C10 0.022 F R16 R13 0.033 F C25 R26 1 k 0.47 F R27 R28 10 k C24 0.47 F 10 k + IF VCC 2 PIF AGC2 11 SIZE COMP 18 E-W OUT 21 SIF IN 12 SIF AGC 13 AFT CHROMA XTAL OUT APC 14 15 16 VERT VCC 17 VERT OUT 19 HORIZ RES 22 AUX VIDEO IN 3 RF AGC OUT 4 PIF WB AUDIO APC OUT FILTER 5 6 RAMP ALC FILTER 20 IF GND 7 PIF IN1 8 PIF IN2 9 HORIZ HORIZ STANDBY AFC HORIZ X VCC FILTER OUT FLYBACK RAY GND 23 24 25 26 27 28 +7.6 V + SAND CASTLE OUT 29 DAC OUT 30 IB IN 31 +7.6 V VID CHROMA VCC 32 + LA7615 C3 C8 1 F R4 C7 R5 1 F R10 + 7.5 k 0.01 F C9 + R75 50 k C29 R40 C22 R42 C118 10 k C34 2.2 k 100 F C35 R36 0.033 F R43 R41 C27 10 F C28 100 k 0.01 F C2 0.01 F C19 R2 R3 100 150 C11 0.047 F 820 R11 C12 50 C13 R12 0.01 F R18 R1 IF1 C1 C4 75 100 F R7 0.47 F 16 R9 50 1T363 C14 C21 100 F C23 10 F 0.01 F C6 CHR1 R25 0.01 F R15 3.3 k R6 C119 0.01 F 16 R8 68 750 +9 V 7.5 k C117 0.01 F Tr1 0.01 F R22 1744 2 16 17 1.6 k 3 18 R17 R21 470 4 5 6 9 11 12 13 14 C16 19 21 +7.6 V R33 5 k 24 26 R38 DELAY2 (9US) R32 8.2 k 1 k 0.01 F + 1 k * 10 F 3.9 k C26 + + 28 29 30 31 1 k R76 + + +9 V +7.6 V + 6.2 k 10 F C17 V101 766-2 1.8 k 1 F C31 T101 M 1 F + + R14 100 k 100 k C15 3 k 16 pF 0.01 F CSB503F (44) 32 VIF IN *: Used for adjusting the characteristics of the crystal oscillator. +7.6 V C30 1500 pF 1 2 3 4 5 NC 6 7 8 LC4528B +7.6 V 16 C22 15 14 13 12 11 10 9 NC R34 5 k WIDTH (12US) R37 2200 pF 8.2 k (Includes two monostable multivibrators.) A10105 0.01 F + 1.5 F + + C51 No. 5841-38/39 LA7615 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1999. Specifications and information herein are subject to change without notice. PS No. 5841-39/39 |
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