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| CCD Linear Image Sensor MN3674 Color CCD Linear Image Sensor with 512 Pixels for R and B Colors/1024 Pixels for G Color s Overview The MN3674 is a high responsivity CCD color linear image sensor with 512 pixels each for R and B and 1024 G pixels, and having low dark output floating photodiodes in the photodetector region and CCD analog shift registers for read out. It can read a 64mm-width color document with a high quality and a maximum pseudo resolution of 400dpi. In addition to being used as a color sensor, this device can also be used as a black and white sensor if only the G row is used, and in this case, it is possible to read a 64mm-width document with a full resolution of 400dpi. Since a one line delay analog memory is built in so as to compensate for the difference in the positions of reading out between the R, B rows and the G row, the configuration of the signal processing circuit becomes simpler. s Pin Assignments 1 NC NC OS1 DS1 VSS oR o1 o SG1 VSS VSS NC 1 2 3 4 5 6 7 8 9 10 11 1024 (Top View) C26 22 21 20 19 18 17 16 15 14 13 12 NC NC OS 2 DS 2 VDD NC o2 o SG2 oV NC NC s Features * 2048 floating photodiodes and n-channel buried type CCD shift registers for read out are integrated in a single chip. * RGB primary colors type on chip color filters are used for color separation. * In order to compensate for the distance between the photodiode rows for the R, B colors and the G color, the device has a built in analog memory that can store the signals of one line of the R-B colors row. * All clock inputs can be driven by 5V CMOS logic. * Use of photodiodes with a new structure has made the dark output voltage very low. * Large signal output of typically 0.8V at saturation can be obtained. WDIP022-G-0470B s Application * Color graphic read out in color image scanners, color fax machines, etc. CCD Linear Image Sensor s Block Diagram OS2 20 MN3674 DS 2 19 VDD 18 o2 16 o SG2 15 oV 14 1 12 1212 121212121212 121212121 1-line delay analog memory B2 B4 B1 B3 12 1212 B32 D2 D4 R1 B1 R2 B31 D1 D3 G1 G2 G3 121212121212 R B 512 512 GG 1023 1024 D6 D8 D5 D7 121212121 1 D B1 to B32 : Black reference pixels D1 to D8 : Dummy invalid pixels 7 8 9 10 3 4 5 6 OS1 DS1 VSS o R o1 o SG1 VSS VSS s Absolute Maximum Ratings (Ta=25C, VSS=0V) Parameter Power supply voltage Input pulse voltage Operating temperature range Storage temperature range Symbol VDD VI Topr Tstg Rating - 0.3 to + 15 - 0.3 to + 15 0 to + 60 -2 5 to + 85 Unit V V C C s Operating Conditions * Voltage conditions (Ta=0 to + 60C, VSS=0V) Parameter Power supply voltage CCD shift register clock High level CCD shift register clock Low level Vertical transfer clock High level Vertical transfer clock Low level Shift gate clock High level Shift gate clock Low level Reset gate clock High level Reset gate clock Low level Symbol VDD Vo H Vo L VVH VVL VSH VSL VRH VRL (o1, o2) (oV) (oSG1, oSG2) (oR) Condition min 11.4 4.5 0 4.5 0 4.5 0 4.5 0 typ 12.0 5.0 0.2 5.0 0.2 5.0 0.2 5.0 0.2 max 13.0 VDD 0.5 VDD 0.5 VDD 0.5 VDD 0.5 Unit V V V V V V V V V MN3674 * Timing conditions (without 1-line delay operation) (Ta=0 to + 60C) Parameter Shift register clock frequency Reset clock frequency (=data rate) Shift register clock rise time Shift register clock fall time Vertical transfer clock rise time Vertical transfer clock fall time Vertical transfer clock pulse width Shift clock 1 rise time Shift clock 1 fall time Shift clock 1 set up time Shift clock 1 pulse width Shift clock 2 rise time Shift clock 2 fall time Shift clock 2 set up time Shift clock 2 pulse width Shift clock 2 hold time Reset clock rise time Reset clock fall time Reset clock set up time Reset clock pulse width Reset clock hold time Symbol fC fR t Cr t Cf t Vr t Vf t VW t SG1r t SG1f t SG1s t SG1w t SG2r t SG2f t SG2s t SG2w t SG2h t Rr t Rf t Rs t Rw t Rh See drive timing diagram (3) See drive timing diagram (1) See drive timing diagram (1) Condition See drive timing diagram (3) fC=1/2T See drive timing diagram (3) fR=1/2T See drive timing diagram (3) o SG1 and oV should be the same timing. See drive timing diagram (1) CCD Linear Image Sensor min 0.1 0.1 0 0 0 0 5 0 0 0.5 5 0 0 0.5 5 0 0 0 0.7T 100 10 typ 1.0 1.0 20 20 15 15 10 15 15 1.0 10 15 15 1.0 10 1 10 10 -- 200 125 max 3.0 3.0 50 50 50 50 50 50 50 2.0 50 50 50 2.0 50 2 20 20 -- -- -- Unit MHz MHz ns ns ns ns s ns ns s s ns ns s s s ns ns ns ns ns * Timing conditions (during 1-line delay operation) (Ta=0 to + 60C) Parameter Shift register clock frequency Reset clock frequency (=data rate) Shift register clock rise time Shift register clock fall time Vertical transfer clock rise time Vertical transfer clock fall time Vertical transfer clock set up time Vertical transfer clock pulse width Vertical transfer clock hold time Shift clock 1 rise time Shift clock 1 fall time Shift clock 1 pulse width Shift clock 2 rise time Shift clock 2 fall time Shift clock 2 set up time Shift clock 2 pulse width Reset clock rise time Reset clock fall time Reset clock set up time Reset clock pulse width Reset clock hold time Symbol fC fR t Cr t Cf t Vr t Vf t Vs t Vw t Vh t SG1r t SG1f t SG1w t SG2r t SG2f t SG2s t SG2w t Rr t Rf t Rs t Rw t Rh See drive timing diagram (3) See drive timing diagram (2) See drive timing diagram (2) o SG1 and oV should be the same timing. See drive timing diagram (2) Condition See drive timing diagram (3) fC=1/2T See drive timing diagram (3) fR=1/2T See drive timing diagram (3) min 0.1 0.1 0 0 0 0 0.5 5 0 0 0 5 0 0 0.5 5 0 0 0.7T 100 100 200 125 typ 1.0 1.0 20 20 15 15 1.0 10 1 15 15 10 15 15 1.0 10 10 10 max 3.0 3.0 50 50 50 50 2.0 50 2 50 50 50 50 50 2.0 50 20 20 -- -- -- Unit MHz MHz ns ns ns ns s s s ns ns s ns ns s s ns ns ns ns ns CCD Linear Image Sensor s Electrical Characteristics * Clock input capacitance (Ta=-20 to + 60C) Parameter CCD Shift register clock input capacitance Vertical transfer clock input capacitance Reset clock input capacitance Shift clock input capacitance Symbol C1 , C 2 CV C RS C SG1, C SG2 VIN =5V f=1MHz Condition min -- -- -- -- typ 200 100 20 100 MN3674 max -- -- -- -- Unit pF pF pF pF * DC characteristics Parameter Power supply current Symbol IDD VDD = +12V Condition min -- typ 10 max 20 Unit mA * AC characteristics Parameter Signal output delay time Symbol t OS Condition (a reference value) min -- typ 50 max -- Unit ns s Optical Characteristics to F=10). * Load resistance = 100k Ohms * These specifications apply to the 512 valid R and G pixels and the 1024 valid G pixels excluding the dummy pixels D1 to D8. Parameter Responsivity Photo response non-uniformity Saturation output voltage Saturation exposure Symbol RR RG RB PRNU VSAT SER SEG SEB VDRK1 Dark signal output voltage Dark signal output non-uniformity Shift register total transfer efficiency Dynamic range VDRK2 DSNU1 DSNU2 STTE DR Note 7 Note 1 Note 1 Note 1 Note 2 Note 3 Note 4 Note 4 Note 4 OS1, Dark condition, see Note 5 OS2, Dark condition, see Note 5 OS1, Dark condition, see Note 6 OS2, Dark condition, see Note 6 Condition min 0.70 1.40 0.90 -- 650 0.67 0.36 0.53 -- -- -- -- 92 -- typ 0.95 1.80 1.20 6 800 0.84 0.44 0.67 0.5 1.0 0.1 0.2 99 800 max 1.20 2.20 1.50 15 -- -- -- -- 1.0 2.0 2.0 4.0 -- -- mV mV % lx * s % mV V/lx * s Unit Note 1) Responsivity (R) This is the value obtained by dividing the average output voltage (V) of the all pixels by the exposure (lx* s). The exposure (lx* s) is the product of the illumination intensity (lx) and the accumulation time (s). Since the responsivity changes with the spectral distribution of the light source used, care should be taken when using a light source other than the daylight type fluorescent lamp specified in the inspection conditions. Note 2) Photo response non-uniformity (PRNU) This is defined by the following equation where Xave is the average output voltage of the valid pixels of each of the colors R, G, and B, and x is the difference between the output voltage of the maximum (or minimum) output pixel and Xave, when the photodetector region is illuminated with light of a uniform illumination intensity distribution. x x100 (%) PRNU= Xave The incident light intensity shall be 50% of the standard saturation llight intensity. MN3674 s Optical Characteristics (continued) CCD Linear Image Sensor Note 3) Saturation output voltage: This is the output voltage at the point beyond which it is not possible to maintain the linearity of the photoelectric conversion characteristics as the exposure is increased. (The exposure at this point is called the saturation exposure.) Note 4) Saturation Exposure (SE) This is the exposure beyond which it is not possible to maintain the linearity of the output voltage as the exposure is increased. When designing the equipment using these devices, make sure that the incident light exposure is set with sufficient margin so that the CCD never gets saturated. Note 5) Dark signal output voltage (VDRK) This is defined as the average of the output from all the valid pixels in the dark condition at Ta=25C, Tint=10ms. Normally, the dark signal output voltage gets doubled for every 8 to 10C increase in Ta and is proportional to Tint. The dark signal output voltage (VDRK2) on the OS2 side will be larger than the dark signal output voltage (VDRK1) on the OS1 side because there is a delay memory on the OS2 side. Note 6) Dark signal non-uniformity (DSNU) This is defined as the difference between the maximum value among the output voltages of the all valid pixels at Ta=25Cand Tint=10ms and VDRK. VDRK DSNU Note 7) Dynamic range (DR) This is defined by the following equation. DR= VSAT VDRK Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the accumulation time is shorter. s Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Symbol NC NC OS1 DS1 V SS oR o1 oSG1 VSS VSS NC NC NC oV oSG2 o2 NC VDD DS 2 OS 2 NC Pin name Non connection Non connection Signal output 1 Compensation output 1 Ground Reset clock CCD clock (Phase 1) CCD shift register clock 1 Ground Ground Non connection Non connection Non connection Vertical transfer clock Shift clock gate 2 CCD clock (Phase 2) Non connection Power supply Compensation output 2 Signal output 2 Non connection Red and Blue pixel output Green pixel output Condition Non connection NC 22 Note) Connect all NC pins externally to VSS (GND). CCD Linear Image Sensor s Construction of the Image Sensor MN3674 The MN3674 can be made up of the three sections of--a) photo detector region, b) CCD transfer region (shift register), and c) output region. a) Photo detector region * The photoelectric conversion device consists of an 11m floating photodiode and a 3m channel stopper (isolation region) per pixel, and such pixels are arranged in a linear row with a pitch of 14m along the main scanning direction. * The R-B row has 512 pixels each of the red and blue colors arranged alternatingly, and the G row has1024 pixels. The R-B row and G row are placed with a spacing of one line (14m) along the sideways scanning direction. The pixels of the G row are displaced by half the pixel pitch (7m) relative to the pixels of the R-B row in the main scanning direction. 1 1 2 2* * * * * * * 512 512 RBRB ****** RB GGGG ******GG 1 2 3 4 * * * * * * 1023 1024 14m 14m 14m 14m * A one line analog delay memory is built in the chip in order to compensate for the difference in the positions of the R-B and G rows in the sideways scanning direction. * The photodetector window is a rectangle of dimensions 9m (Horizontal) x 11m (Vertical), and the areas other than the photodetector window are optically shielded. * The photodetector region has a total of 32 optically shielded (black reference) pixels that can be used as the black level reference, with 16 pixels each for the R-B row and the G row. b) CCD Transfer region (shift register) * The signal charges obtained by photoelectric conversion are transferred to the CCD transfer regions of the respective colors during the period when the shift gate (oSG) is at the High level. The signal charges transferred to this analog shift register are successively transferred to the output region. * A buried type CCD that can be driven by a two phase clock (o1, o2) is used for the analog shift register. c) Output region * The signal charge transferred to the output region is first sent to the charge to voltage conversion region where it is converted into a voltage level corresponding to the amount of the signal charge, and then output after impedance conversion in a two stage source follower amplifier. * The DC level component not containing the optical signal and the clock noise component are output at the DS pin. * It is possible to obtain a signal with a high S/N ratio with reduced clock noise, etc., by carrying out differential amplification of the OS and DS outputs externally. s 1-Line delay analog memory * In order to compensate for the distance between the photodiode rows for the R, B colors and the G color, the device has a built in analog memory that can store the signals of one line. It is possible to select either to use or not use the delay memory by the timings of the pulses oV, oSG1, and oSG2, and the two types of read out operation of 512 pixel operation and pseudo 1024 pixel operation can be obtained accordingly. (1) 512-pixel operation (no delay memory) RB GG is taken as one pixel thereby making this device a 512-pixel color CCD. (Each pixel of the color sensor will be a parallelogram of 28m (horizontal) x 28m (vertical).) Sideways scanning direction (2) Pseudo 1024-pixel operaation (delay memory is used) 2 4 1022 A 1-line delay operation and interpolation signal processing 1 3 5 * * * * * * 1023 shown in the figure at left are made for the R-B colors. R B R B R B *** B R B G G G G G G *** G G G 1 2 3 4 5 6 * * * 1022 1024 1023 BR RB G G or becomes one pixel during color sensing operation. * Since the signal from the R-B row gets delayed, configure the optical system and mechanisms so that the sideways scanning is done first from the R-B row. The R-B row and the G row of the same line will be read out due to the one line delay. The weighted center of one color pixel can be considered to be at the position of the G pixel. MN3674 s Timing Diagram * I/O timing (1) (without 1-line delay operation) o SG1 oV o SG2 o1 o2 oR 0 1 2 17 18 19 20 21 22 1041 1043 1045 1042 1044 1046 CCD Linear Image Sensor DS1 OS1 B1 B29 B31 D1 D 3 G1 G2 G3 D G1022 G1024 5 D7 G1021 G1023 Blank feed level DS2 OS2 B2 B30 B32 D2 D 4 B511 B512 D6 D8 Note) Repeat the transfer R511 R512 pulses (o1 , o2) for more than 1046 periods. B1 to B32 : Black reference pixels R1 B1 R2 D1 to D8 : Dummy invalid pixels * I/O timing (2) (during 1-line delay operation) o SG1 oV o SG2 o1 o2 oR 0 1 2 17 18 19 20 21 22 1041 1043 1045 1042 1044 1046 DS1 OS1 B1 B29 B31 D1 D3 G1 G2 G 3 D G1022 G1024 5 D7 G1021 G1023 Blank feed level DS2 OS2 B2 B30 B32 D2 D 4 B 511 B 512 D6 D8 R 511 R 512 Note) Repeat the transfer pulses (o1 , o2) for more than 1046 periods. B1 to B32 : Black reference pixels R1 B1 R2 D1 to D8 : Dummy invalid pixels * OS 2 outputs the previous line signal. CCD Linear Image Sensor MN3674 * Drive timing (1) (read-out during no 1-line delay operation) t SG1r 90% o SG1 50% 10% t Vr oV 90% 50% 10% t Vw o SG2 t SG2s t SG2w t SG1w t Vf t SG2r t SG2f t SG1f 90% 50% 10% o1 50% 50% t SG1s t SG2h Note) Make sure that the timings of o SG and o V are identical. (If these are not identical, the accumulation time gets shifted and hence the data on the same line cannot be obtained.) * Drive timing (2) (read-out during 1-line delay operation) t SG1r o SG1 t Vr oV t SG2r t SG2f t SG1w t Vf 90% 50% 10% t Vs t Vw t SG1f 90% 50% 10% o SG2 90% 50% 10% o1 50% 50% t SG2s t SG2w t Vh Note) Make sure that the timings of o SG and o V are identical. (If these are not identical, the accumulation time gets shifted and hence the data on the same line cannot be obtained.) MN3674 * Drive timing (3) (during repeated pattern) 90% o2 t Cr o1 t RS 10% t Cf 90% 50% 10% t RW CCD Linear Image Sensor t Rh 90% 50% 10% oR t Rr DS 1 (DS2) t Rf t OS 2T t Oh Reference level 50% OS 1 (OS 2) Effective signal output period s Graphs and Characteristics Spectral Response Characteristics 100 Relative responsivity (%) 80 60 40 20 0 Blue Green Red 400 500 600 700 Wavelength (nm) 800 |
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