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65A
CYM1465A
512K x 8 PDIP Static RAM
Features
* * * * * * * * 4.5V-5.5V operation CMOS SRAM for optimum speed and power Low active power (165 mW max.) Low standby power (L Version)--(110 W max) 2V data retention (L Version) JEDEC-compatible pinout 32-pin, 0.6-inch-wide DIP package TTL-compatible inputs and outputs an automatic power-down feature that reduces power consumption by more than 99% when deselected. Writing to the SRAM is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input/output pins (I/O0 through I/O7) of the device is then written into the memory location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip select (CE) and output enable (OE) LOW while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins (A0 through A18) will appear on the eight appropriate data input/output pins (I/O0 through I/O7).The eight input/output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CYM1465A is available in a 32-pin 600-mil wide body PDIP package.
Functional Description
The CYM1465A is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has
Logic Block Diagram
Pin Configuration
DIP Top View
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1S 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
I/O0
INPUT BUFFER
A0 A1 A4 A5 A6 A7 A12 A14 A16 A17
I/O1
ROW DECODER
I/O2
SENSE AMPS
512 x 256 x 8 ARRAY
I/O3 I/O4 I/O5
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
CE WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Selection Guide
CYM1465A-70 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (A) 70 20 20 CYM1465A-85 85 20 20
Cypress Semiconductor Corporation Document #: 38-05269 Rev. **
A2 A3 A 15 A18 A13 A8 A9 A11 A 10
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised March 15, 2002
CYM1465A
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ................................. -55C to +150C Ambient Temperature with Power Applied............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V Range Commercial Industrial DC Input Voltage .............................................-0.5V to +7.0V
Operating Range
Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
CYM1465A Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current Automatic CS Power-Down Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CS < VIL Max. VCC, CE > VIH, Min. Duty Cycle = 100% Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Test Conditions VCC = Min., IOH = - 1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 20 1.5 20 Max. Unit V V V V A A mA mA A
Capacitance[1]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 10 Unit pF pF
AC Test Loads and Waveforms
1.847 k 5V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: OUTPUT
[2]
1.847 k 5V OUTPUT 1 k INCLUDING JIG AND SCOPE 5 pF 1 k GND < 10 ns 3.0V
ALL INPUT PULSES 90% 10% 90% 10% <10 ns
(a)
(b)
THEVENIN EQUIVALENT 648 1.76V
Notes: 1. Tested on a sample basis. 2. Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance for 85-, 100-, 120-, and 150-ns speeds. CL = 30 pF for 70-ns speed.
Document #: 38-05269 Rev. **
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CYM1465A
Switching Characteristics Over the Operating Range[2]
CYM1465A-70 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCS tHZCS tPU tPD WRITE CYCLE[4] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[3] 70 60 60 0 0 55 30 0 5 25 85 75 75 0 0 65 35 0 5 30 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
[3] [3]
CYM1465A-85 Min. 85 Max. Unit ns 85 10 85 45 5 30 10 30 0 85 ns ns ns ns ns ns ns ns
Description
Min. 70
Max.
70 10 70 35 5 25 10 25 0 70
CE LOW to Power Down CE HIGH to Power Down
Data Retention Characteristics Over the Operating Range (L Version Only)
Commercial Parameter VDR ICCDR3 tCDR tR[5]
[5]
Industrial Min. 2 Max. 20 0 tRC Unit V A ns ns
Description VCC for Retention Data Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Test Conditions No Input may exceed Vcc+0.3V VDR = 3.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V
Min. 2
Max. 20
0 tRC
Notes: 3. CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 4. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 5. Guaranteed, not tested.
Document #: 38-05269 Rev. **
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CYM1465A
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR VDR CE VIH VIH VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1
ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
[6,7]
tRC
Read Cycle No. 2 [6,8]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS DATA VALID tHZOE tHZCE HIGH IMPEDANCE tRC
Notes: 6. WE is HIGH for read cycle. 7. Device is continuously selected, CE= VIL. 8. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05269 Rev. **
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CYM1465A
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[4]
tWC ADDRESS tSCE CE tAW tPWE tHA
tSA WE
tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
tHD
tLZWE HIGH IMPEDANCE
[4,9]
Write Cycle No. 2 (CE Controlled)
tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED HIGH IMPEDANCE tHD tHA tSCE
Note: 9. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
Inputs CE H L L L WE X H L H OE X L X H Output High Z Data Out Data In High Z Mode Deselect/Power-Down Read Word Write Word Deselect
Document #: 38-05269 Rev. **
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CYM1465A
Ordering Information
Speed (ns) 70 70 85 85 Ordering Code CYM1465ALPD-70C CYM1465ALPD-70I CYM1465ALPD-85C CYM1465ALPD-85I Package Name P19 P19 P19 P19 Package Type 32-Pin DIP Module 32-Pin DIP Module 32-Pin DIP Module 32-Pin DIP Module Operating Range Commercial Industrial Commercial Industrial
Package Diagram
32-Lead (600-Mil) Molded DIP P19
51-85018-*A
Document #: 38-05269 Rev. **
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYM1465A
Revision History
Document Title: CYM1465A 512K x 8 PDIP Static RAM Document Number: 38-05269 REV. ** ECN NO. 114171 ISSUE DATE 3/19/02 ORIG. OF CHANGE DSG DESCRIPTION OF CHANGE Change from Spec number: 38-M-00036 to 38-05269
Document #: 38-05269 Rev. **
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