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Features
* 1.65V - 1.95V Read/Write * High Performance
- Random Access Time - 70 ns - Page Mode Read Time - 20 ns - Synchronous Burst Frequency - 66 MHz - Configurable Burst Operation Sector Erase Architecture - Sixteen 4K Word Sectors with Individual Write Lockout - Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: 32K Word Sectors - 500 ms; 4K Word Sectors - 100 ms Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one Planes not Being Programmed/Erased Suspend/Resume Feature for Erase and Program - Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 30 mA Active - 10 A Standby VPP Pin for Write Protection and Accelerated Program/Erase Operations RESET Input for Device Initialization CBGA and TSOP Packages Seventeen 128-bit Protection Registers (2,176 Bits) Common Flash Interface (CFI)
* * * *
* * * * * *
128-megabit (8M x 16) Burst/Page Mode 1.8-volt Flash Memory AT49SN12804 AT49SV12804
Description
The AT49SN/SV12804 is a 1.8-volt 128-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The AT49SN/SV12804 is organized as 8,388,608 x 16 bits. The device can be read or reprogrammed off a single 1.8V power supply, making it ideally suited for In-System programming. The device can be configured to operate in the asynchronous/page read (default mode) or burst read mode (not available for the AT49SV12804). The burst read mode is used to achieve a faster data rate than is possible in the asynchronous/page read mode. If the AVD and the CLK signals are both tied to GND and the burst configuration register is configured to perform asynchronous reads, the device will behave like a standard asynchronous Flash memory. In the page mode, the AVD signal can be tied to GND or can be pulsed low to latch the page address. In both cases the CLK can be tied to GND. The AT49SN/SV12804 is divided into thirty-two memory planes. A read operation can occur in any of the thirty-one planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane. The VPP pin provides data protection and faster programming and erase times. When the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase operations can be performed. With VPP at 12.0V, the program (Dual-word Program command) and erase operations are accelerated.
Preliminary
Rev. 3314A-FLASH-4/04
1
AT49SN/SV12804: Pin Configurations
Pin Name I/O0 - I/O15 A0 - A22 CE OE WE AVD
(1)
Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Address Latch Enable Clock Reset Write Protect Write Protection and Power Supply for Accelerated Program Operations WAIT Output Power Supply
CLK(1) RESET WP
(1)
VPP WAIT(1) VCCQ Note:
1. These signals are not available for use with the AT49SV12804. The AT49SV12804 can only be used in the asynchronous/page mode.
AT49SN12804: CBGA - Top View
1 2 3 4 5 6 7 8
AT49SV12804: TSOP - Top View Type 1
A21 NC A20 A19 A18 A17 A16 A15 VCC A14 A13 A12 A11 CE VPP RST A10 A9 A8 A7 VSS A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC WE OE NC I/O15 I/O7 I/O14 I/O6 VSS I/O13 I/O5 I/O12 I/O4 VCCQ VSS I/O11 I/O3 I/O10 I/O2 VCC I/O9 I/O1 I/O8 I/O0 NC NC A22 NC
A B C D E F G
A11 A12
A8 VSS VCC VPP A18 A9 A20 CLK RESET A17
A6 A5 A7
A4 A3 A2 A1 A0
A13 A10 A21 AVD WE A19
A15 A14 WAIT A16 I/O12 WP A22 VCCQ I/O15 I/O6 I/O4 I/O2 I/O1 CE
VSS I/O14 I/013 I/O11 I/O10 I/O9 I/O0 OE I/O7 VSS I/O5 VCC I/O3 VCCQ I/O8 VSS
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AT49SN/SV12804 [Preliminary]
Device Operation
COMMAND SEQUENCES: When the device is first powered on, it will be in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on the AVD signal. If the AVD is not pulsed low, the address will be latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences. BURST CONFIGURATION COMMAND: The Program Burst Configuration Register command is used to program the burst configuration register. The burst configuration register determines several parameters that control the read operation of the device. Bit B15 determines whether synchronous burst reads are enabled or asynchronous reads are enabled. Since the page read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to enable the page read feature. Bit B14 determines whether a four-word page or an eight-word page will be used. The rest of the bits in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency for the burst mode. The latency can be set to two, three, four, five or six cycles. The clock latency versus input clock frequency table is shown on page 20. The "Burst Read Waveform" as shown on page 31 illustrates a clock latency of four; the data is output from the device four clock cycles after the first valid clock edge following the high-to-low AVD edge. The B10 bit of the configuration register determines the polarity of the WAIT signal. The B9 bit of the burst configuration register determines the number of clocks that data will be held valid (see Figure 4). The Hold Data for 2 Clock Cycles Read Waveform is shown on page 31. The clock latency is not affected by the value of the B9 bit. The B8 bit of the burst configuration register determines when the WAIT signal will be asserted. When synchronous burst reads are enabled, a linear burst sequence is selected by setting bit B7. Bit B6 selects whether the burst starts and the data output will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of the burst configuration register determine whether a continuous or fixed-length burst will be used and also determine whether a four-, eight- or sixteen-word length will be used in the fixed-length mode. When a four-, eight- or sixteen-word burst length is selected, Bit B3 can be used to select whether burst accesses wrap within the burst length boundary or whether they cross word length boundaries to perform linear accesses (see Table 5). All other bits in the burst configuration register should be programmed as shown on page 20. The default state (after power-up or reset) of the burst configuration register is also shown on page 20. ASYNCHRONOUS READ: There are two types of asynchronous reads - AVD pulsed and standard asynchronous reads. The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. The data at the address location defined by A0 - A22 and captured by the AVD signal will be read when CE and OE are low. The address location passes into the device when CE and AVD are low; the address is latched on the low-to-high transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of the device. The access time is measured from stable address, falling edge of AVD or falling edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are shown on page 28. PAGE READ: The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input is ignored during a page read operation and should be tied to GND. The page size can be four words (default value) or eight words depending on what value bit B14 of the burst configuration register is programmed to. During a page read, the AVD signal can transition low and then transition high, transition low and remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1, the 3
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page address is latched by the low-to-high transition of the AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (determined by A22 - A3 for an eight word page and A22 - A2 for a four-word page) cannot change during a page read operation. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 90 ns. Once the first word is read, toggling A0 and A1 (fourword page mode) or toggling A0, A1, and A2 (eight word page mode) will result in subsequent reads within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to GND, the device will behave like a standard asynchronous Flash memory. The page read diagrams are shown on page 22. SYNCHRONOUS READS: Synchronous reads (not available on the AT49SV12804) are used to achieve a faster data rate that is possible in the asynchronous/page read mode. The device can be configured for continuous or fixed-length burst access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs. The initial read location is determined as for the AVD pulsed asynchronous read operation; it can be any memory location in the device. In the burst access, the address is latched on the rising edge of the first clock pulse when AVD is low or the rising edge of the AVD signal, whichever occurs first. The CLK input signal controls the flow of data from the device for a burst operation. After the clock latency cycles, the data at the next burst address location is read for each following clock cycle. Figure 1. Word Boundary
Word D0 - D3 D0 D1 D2 Word D4 - D7 D5 D6 D7 Word D8 - D11 Word D12 - D15
D3 D4
D8 D9 D10 D11 D12 D13 D14 D15
16-word Boundary
CONTINUOUS BURST READ: During a continuous burst read, any number of addresses can be read from the memory. When operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory (see Figure 1). If the starting address is D0 - D12, there is no delay. If the starting address is D13 - D15, an output delay equal to the initial clock latency is incurred. The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated when the CE or OE signal is high. In the "Burst Read Waveform" as shown on page 31, the valid address is latched at point A. For the specified clock latency of three, data D13 is valid within 13 ns of clock edge B. The low-to-high transition of the clock at point C results in D14 being read. The transition of the clock at point D results in a burst read of D15. The clock transition at point E does not cause new data to appear on the output lines because the WAIT signal goes low (B10 and B8 = 0) after the clock transition, which signifies that the first boundary in the memory has been crossed and that new data is not available. After a clock latency of three, the clock transition at point F does cause a burst read of data D16 because the WAIT signal goes high (B10 and B8 = 0) after the clock transition indicating that new data is available. Additional clock transitions, like at point G, will continue to result in burst reads.
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AT49SN/SV12804 [Preliminary]
FIXED-LENGTH BURST READS: During a fixed-length burst mode read, four, eight or sixteen words of data may be burst from the device, depending upon the configuration. The device supports a linear burst mode. The burst sequence is shown on page 21. When operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory. If the starting is D0 - D12, there is no delay. If the starting address is D13 - D15, an output delay equal to the initial clock latency is incurred. The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated when the CE or OE signal is high. The "Four-word Burst Read Waveform" on page 32 illustrates a fixed-length burst cycle. The valid address is latched at point A. For the specified clock latency of four, data D0 is valid within 13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read. Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the read cycle. There is no output delay in the burst access wrap mode (B3 = 0). BURST SUSPEND: The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the Flash address and data bus for other purposes. Burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. Burst Suspend occurs when CE is asserted, the current address has been latched (either rising edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be halted when it is at VIH or VIL. To resume the burst access, OE is reasserted and the CLK is restarted. Subsequent CLK edges resume the burst sequence where it left off. Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT signal reverts to a high-impedance state when OE is deasserted. See "Burst Suspend Waveform" on page 32. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read mode. ERASE: Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical "1". The entire memory can be erased by using the Chip Erase command or individual planes can be erased by using the Plane Erase command or individual sectors can be erased by using the Sector Erase command.
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CHIP ERASE: Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset during chip erase will stop the erase, but the data will be of an unknown state. PLANE ERASE: As an alternative to a full Chip Erase, the device is organized into thirty-two planes that can be individually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address is valid at the second rising edge of WE will be erased. The Plane Erase command does not alter the data in the protected sectors. SECTOR ERASE: The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected. WORD PROGRAMMING: The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second cycle. The device will automatically generate the required internal programming pulses. Please note that a "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. FLEXIBLE SECTOR PROTECTION: The AT49SN/SV12804 offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a twobus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector. HARDLOCK AND WRITE PROTECT (WP): The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden. * When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. * When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command.
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AT49SN/SV12804 [Preliminary]
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled. Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP
Hardlock 0 0 Softlock 0 1 Erase/ Prog Allowed? Yes No
VPP VCC VCC
WP 0 0
Comments No sector is locked Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is enabled. The sector cannot be unlocked. No sector is locked. Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is overridden and the sector is not locked. Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. Erase and Program Operations cannot be performed.
VCC
0
1
1
No
VCC VCC
1 1
0 0
0 1
Yes No
VCC
1
1
0
Yes
VCC
1
1
1
No
VIL
x
x
x
No
Figure 2. Sector Locking State Diagram
UNLOCKED LOCKED
[000]
A
C
B
[001]
WP = VIL = 0
C
[011]
Power-Up/Reset Default
Hardlocked
[110]
A C A B
B
[111]
Hardlocked is disabled by WP = VIH
WP = VIH = 1
C
Power-Up/Reset Default
[100]
[101]
A = Unlock Command B = Softlock Command C = Hardlock Command
Note:
1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP and the two bits of the sector-lock status D[1:0].
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SECTOR PROTECTION DETECTION: A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked. Table 2. Sector Protection Status
I/O1 0 0 1 1 I/O0 0 1 0 1 Sector Protection Status Sector Not Locked Softlock Enabled Hardlock Enabled Both Hardlock and Softlock Enabled
READ STATUS REGISTER: The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the memory, issue a Read command. The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H when a Read Status Register command is issued. The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE (whichever occurs last), which prevents possible bus errors that might occur if status register contents change while being read. CE or OE must be toggled with each subsequent status read, or the status register will not indicate completion of a Program or Erase operation. When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 3).
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AT49SN/SV12804 [Preliminary]
READ STATUS REGISTER IN THE BURST MODE: The waveform below shows a status register read during a program operation. The two-bus cycle command for a program operation is given followed by a read status register command. Following the read status register command, the AVD signal is pulsed low to latch the valid address at point A. With the OE signal pulsed low and for the specified clock latency of three, the status register output is valid within 13 ns from clock edge B. The same status register data is output on successive clock edges. To update the status register output, the AVD signal needs to be pulsed low and the next data is available after a clock latency of three. The status register output is also available after the chosen clock latency during an erase operation. Figure 3. Read Status Register in the Burst Mode
A CLK CE B
OE
AVD
WE
A0 - A22
XX
ADDRESS
I/O0 - I/O15
40H/10H
DATA
70H
00H
80H
WAIT
(1)
Note:
1. The WAIT signal is for a burst configuration setting of B10 and B8 = 0.
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Table 3. Status Register Bit Definition
WSMS 7 ESS 6 ES 5 PRS 4 VPPS 3 PSS 2 Notes SR7 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR6 = ERASE SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR5 = ERASE STATUS (ES) 1 = Error in Sector Erase 0 = Successful Sector Erase SR4 = PROGRAM STATUS (PRS) 1 = Error in Programming 0 = Successful Programming SR3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK Check Write State Machine bit first to determine Word Program or Sector Erase completion, before checking program or erase status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1" - ESS bit remains set to "1" until an Erase Resume command is issued. When this bit is set to "1", WSM has applied the max number of erase pulses to the sector and is still unable to verify successful sector erasure. When this bit is set to "1", WSM has attempted but failed to program a word SLS 1 PLS 0
The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP is also checked before the operation is verified by the WSM. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1". PSS bit remains set to "1" until a Program Resume command is issued. If a Program or Erase operation is attempted to one of the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. Indicates program or erase status of the addressed plane.
SR2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR1 = SECTOR LOCK STATUS 1 = Prog/Erase attempted on a locked sector; Operation aborted. 0 = No operation to locked sectors SR0 = Plane Status (PLS) Note:
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
Table 4. Status Register Device WSMS and Write Status Definition
WSMS (SR7) 0 0 1 PLS (SR0) 0 1 x Description The addressed plane is performing a program/erase operation. A plane other than the one currently addressed is performing a program/erase operation. No program/erase operation is in progress in any plane. Erase and Program suspend bits (SR6, SR2) indicate whether other planes are suspended.
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AT49SN/SV12804 [Preliminary]
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector erase or plane erase operation. The erase suspend command does not work with the Chip Erase feature. Using the erase suspend command to suspend a sector erase operation, the system can program or read data from a different sector within the same plane. Since this device is organized into thirty-two planes, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in another plane. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address. Read, Read Status Register, Product ID Entry, Clear Status Register, Program, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector Unlock are valid commands during an erase suspend. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. After the programming operation has been suspended, the system can then read from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid commands during a Program Suspend. 128-BIT PROTECTION REGISTERS: The AT49SN/SV12804 contains seventeen (PR0 PR16) 128-bit registers that can be used for security purposes in system design. Please see the Protection Register Addressing Table on page 19 for the address locations within each protection register. The first protection register (PR0) is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. The other 16 registers (PR1 - PR16) have 128 bits (16 words) each that are all user programmable. To program block B in PR0 or to program PR1 - PR16 register, a two-bus cycle command must be used as shown in the Command Definition table on page 18. To lock out block B in PRO or to lock out PR1 - PR16, a two-bus cycle command must also be used as shown in the Command Definition table. To lock out block B in PRO, the address used in the second bus cycle is 080h and data bit D1 must be zero during the second bus cycle. All other data bits during the second bus cycle are don't cares. To lock out PR1 - PR16, the address used in the second bus cycle is 089h and sixteen bits of data are programmed. If any of these bits is programmed to a zero, the appropriate register is locked. After being locked, the protection register cannot be unlocked. To determine whether block B in PRO or PR1 - PR16 is locked out, the Product ID Entry command is given followed by a read operation from address 80H or address 89H, respectively. (This command is shown as status of protection in the Command Definition table). For block B in PRO, if data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. For PR1 - PR16, sixteen bits of data are read out. Each bit represents the protection status of a particular register. If the bit is a zero, the register is locked. If the bit is a one, the register can be reprogrammed. To read a protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether a register is protected or not or reading the protection register, the Read command must be given to return to the read mode. 11
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CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to any address. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in Table on page 31. To return to the read mode, the read command should be issued. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49SN/SV12804 in the following ways: (a) VCC sense: if VCC is below 1.2V (typical), the device is reset and the program and erase functions are inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP. INPUT LEVELS: While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 2.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V. OUTPUT LEVELS: For the AT49SN/SV12804, output high levels are equal to VCCQ - 0.1V (not VCC). VCCQ must be regulated between 1.8V - 2.25V.
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AT49SN/SV12804 [Preliminary]
Word Program Flowchart
Start
Word Program Procedure
Bus Operation Write Command Program Setup Data None None Comments Data = 40 Addr = Location to program Data = Data to program Addr = Location to program Status register data: Toggle CE or OE to update status register Check SR7 1 = WSM Ready 0 = WSM Busy
Write 40, Word Address
(Setup)
Write
(Confirm)
Write Data, Word Address Read Status Register
Read
Program Suspend Loop
No
Idle
SR7 =
1
0
Suspend?
Yes
Full Status Check (If Desired)
Repeat for subsequent Word Program operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to set to the Read state.
Program Complete
Full Status Check Flowchart
Read Status Register
Full Status Check Procedure
Bus Operation Idle Command None None None Comments Check SR3: 1 = VPP Error Check SR4: 1 = Data Program Error Check SR1: 1 = Sector locked; operation aborted
SR3 =
0
1
VP P Range Error
Idle Idle
SR4 =
0
1
Program Error
SR1 =
0
1
Device Protect Error
SR3 MUST be cleared before the Write State Machine allows further program attempts. If an error is detected, clear the status register before continuing operations - only the Clear Status Register command clears the status register error bits.
Program Successful
13
3314A-FLASH-4/04
Program Suspend/Resume Flowchart
Start
Program Suspend/Resume Procedure
Bus Operation Write Command Program Suspend Read Status None Comments Data = B0 Addr = Sector address to Suspend (SA) Data = 70 Addr = Any address within the Same Plane Status register data: Toggle CE or OE to update status register Addr = Any address Check SR7 1 = WSM Ready 0 = WSM Busy Check SR2 1 = Program suspended 0 = Program completed Data = FF Addr = Any address within the Suspended Plane Read data from any sector in the memory other than the one being programmed Data = D0 Addr = Any address
Write B0 Any Address
(Program Suspend)
Write 70 Any Address (Read Status) within the Same Plane Read Status Register
Write Read
Idle
SR7 =
1 0
None
Idle
SR2 =
1 0
None
Program Completed
Write FF Suspend Plane
Write
(Read Array)
Read Array
Read Data
Write FF
(Read Array)
Read Write
None Program Resume
Done Reading
Yes
No
Read Data
Write D0 Any Address
If the Suspend Plane was placed in Read mode:
(Program Resume)
Write
Read Status
Program Resumed
Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane
Write 70H Any Address within the Same Plane
(Read Status)
14
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Erase Suspend/Resume Flowchart
Start
Erase Suspend/Resume Procedure
Bus Operation Write Command Erase Suspend Read Status None Comments Data = B0 Addr = Any address within the Same Plane Data = 70 Addr = Any address Status register data: Toggle CE or OE to update status register Addr = Any address within the Same Plane Check SR7 1 = WSM Ready 0 = WSM Busy Check SR6 1 = Erase suspended 0 = Erase completed Data = FF or 40 Addr = Any address Read or program data from/to sector other than the one being erased Data = D0 Addr = Any address
Write B0, Any Address
(Erase Suspend)
Write 70, Any Address Read Status Register
Write
(Read Status)
Read
SR7 =
1
0
Idle
None
SR6 =
1
0
Erase Completed
Idle
None
Read or Program? Read
No Program Loop
Write Read or Write Write
Read or Program None Program Resume
Done?
Yes (Erase Resume)
Write D0, Any Address Erase Resumed
Write FF
(Read Array)
If the Suspended Plane was placed in Read mode or a Program loop:
Read Array Data
Write
Read Status
Write 70H Any Address within the Same Plane
Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane
(Read Status)
15
3314A-FLASH-4/04
Sector Erase Flowchart
Start
Sector Erase Procedure
Bus Operation Write Command Sector Erase Setup Erase Confirm None None Comments Data = 20 Addr = Sector to be erased (SA) Data = D0 Addr = Sector to be erased (SA) Status register data: Toggle CE or OE to update status register data Check SR7 1 = WSMS Ready 0 = WSMS Busy
Write 20, Sector Address
(Sector Erase)
Write D0, (Erase Confirm) Sector Address Read Status Register
No
Write
Suspend Erase Loop
Read Idle
SR7 =
1
0
Suspend Erase
Yes
Full Erase Status Check (If Desired)
Sector Erase Complete
Repeat for subsequent sector erasures. Full status register check can be done after each sector erase, or after a sequence of sector erasures. Write FF after the last operation to enter read mode.
Full Erase Status Check Flowchart
Read Status Register
1
Full Erase Status Check Procedure
Bus Operation Command None None None None Comments Check SR3: 1 = VPP Range Error Check SR4, SR5: Both 1 = Command Sequence Error Check SR5: 1 = Sector Erase Error Check SR1: 1 = Attempted erase of locked sector; erase aborted.
SR3 =
0
SR4, SR5=
VP P Range Error Command Sequence Error
Idle Idle Idle
1,1
0
SR5 =
0
1
Sector Erase Error
Idle
1
SR1 =
0
Sector Locked Error
Sector Erase Successful
SR1, SR3 must be cleared before the Write State Machine allows further erase attempts. Only the Clear Status Register command clears SR1, SR3, SR4, SR5. If an error is detected, clear the status register before attempting an erase retry or other error recovery.
16
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Protection Register Programming Flowchart
Start
Protection Register Programming Procedure
Bus Operation Write Command Program PR Setup Protection Program None None Comments Data = C0 Addr = First Location to Program Data = Data to Program Addr = Location to Program Status register data: Toggle CE or OE to update status register data Check SR7 1 = WSMS Ready 0 = WSMS Busy
Write C0, PR Address
(Program Setup)
Write
(Confirm Data)
Write PR Address & Data
Read Idle
Read Status Register
SR7 =
1
0
Full Status Check (If Desired)
Program Complete
Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to return to the Read mode.
Full Status Check Flowchart
Read Status Register Data
Full Status Check Procedure
Bus Operation Command None None None Comments Check SR1, SR3, SR4: 0,1,1 = VPP Range Error Check SR1, SR3, SR4: 0,0,1 = Programming Error Check SR1, SR3, SR4: 1, 0,1 = Sector locked; operation aborted
SR3, SR4 =
0
1, 1
Idle
VP P Range Error
Idle
0, 1
SR1, SR4 =
Program Error
Idle
0
SR1, SR4 =
0
1, 1
Register Locked; Program Aborted
Program Successful
SR3 must be cleared before the Write State Machine allows further program attempts. Only the Clear Status Register command clears SR1, SR3, SR4. If an error is detected, clear the status register before attempting a program retry or other error recovery.
17
3314A-FLASH-4/04
Command Definition in Hex(1)
Command Sequence Read Chip Erase Plane Erase Sector Erase Word Program Dual Word Program
(9)
Bus Cycles 1 2 2 2 2 3 1 1 1 2 2 2 2 1 2 2 2 2 2 2 2 1
1st Bus Cycle Addr PA
(2)
2nd Bus Cycle Addr Data FF 21 22 20 Addr Addr SA
(3) (14)
3rd Bus Cycle Addr Data
Data
XX XX SA Addr
(14)
D0 D0 D0 DIN DIN0 Addr1 DIN1
40/10 E0 B0 D0 90 60 60 60 70 50 C0 C0 C0 90 90 60 90 98
Addr
Addr0 XX PA PA SA SA SA PA XX XX
(8)
Addr0
Erase/Program Suspend Erase/Program Resume Product ID Entry Sector Softlock Sector Hardlock Sector Unlock Read Status Register Clear Status Register Program PR0 (Block B) or PR1-PR16 Lock Protection PR0 - Block B Lock Protection PR1-PR16 Status of Protection PR0 (Block B) Status of Protection PR1-PR16 Program Burst Configuration Register Read Burst Configuration Register CFI Query
Notes:
(13)
SA(3) SA
(3) (3)
01 2F D0 DOUT(4) DIN FFFD DIN(11) DOUT(5) DOUT(12) 03 DOUT
(7)
SA
XX Addr(10) 80 89 80 89 Addr(6) PAX005
80 XX PA PA Addr(6) PA XX
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don't care. The ADDRESS FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A22 through A8 are don't care. 2. PA is the plane address (A22 - A18). Any address within a plane can be used. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 22 - 25 for details). 4. The status register bits are output on I/O7 - I/O0. 5. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed. 6. See "Burst Configuration Register" on page 20. Bits B15 - B0 of the burst configuration register determine A15 - A0. Addresses A16 - A22 can select any plane. 7. The plane address has to be the same as the plane address in the second bus cycle. 8. Any address within the user programmable protection register region. 9. This fast programming option enables the user to program two words in parallel only when VPP = 12V. The addresses, Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only. 10. Address locations are shown on next page. 11. DIN represents 16 bits of data. If any bit is programmed to a "0", the appropriate protection register is locked. 12. DOUT represents 16 bits of data. Each bit corresponds to the protection status of a given register. The most significant bit read out corresponds to PR16, and the last significant bit corresponds to PR0. If the data bit is a "0", the register is locked. If the data bits is a "1", the register can be programmed. 13. The manufacturer code is read from address 0000H, and the device code is read from address 0001H. 14. The first bus cycle address should be the same as the word address to be programmed.
18
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages Except VPP (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V VPP Input Voltage with Respect to Ground ......................................... 0V to 12.5V All Output Voltages with Respect to Ground ...........................-0.6V to VCCQ + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Protection Register Addressing Table
Address 81 82 83 PRO 84 85 86 87 88 Use Factory Factory Factory Factory User User User User Block A A A A B B B B A8 0 0 0 0 0 0 0 0 A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
8A PR1
* * *
User
0
* * *
1
0
0
0
1
0
1
0
91
User
0
1
0
0
1
0
0
0
1
92 PR2
* * *
User
0
* * *
1
0
0
1
0
0
1
0
A1
User
* * *
0
1
0
1
* * *
0
0
0
* * *
0
1
102 PR16
* * *
User
1
* * *
0
0
0
0
0
0
1
0
109 Note:
User
1
0
0
0
0
1
0
0
1
1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A22 - A9 = 0.
19
3314A-FLASH-4/04
Burst Configuration Register
B15 B14 B13 - B11: 0 1(1) 0(1) 1 010(2) 011 100 101 110(1) 0 1(1)(3) 0 1(1) 0 1(1) 1(1) 0 1(1) 00(1) 0 1(1) 001 010 011 111(1) Synchronous Burst Reads Enabled Asynchronous Reads Enabled Four-word Page Eight-word Page Clock Latency of Two Clock Latency of Three Clock Latency of Four Clock Latency of Five Clock Latency of Six WAIT Signal is Asserted Low WAIT Signal is Asserted High Hold Data for One Clock Hold Data for Two Clocks WAIT Asserted during Clock Cycle in which Data is Valid WAIT Asserted One Clock Cycle before Data is Valid Linear Burst Sequence Burst Starts and Data Output on Falling Clock Edge Burst Starts and Data Output on Rising Clock Edge Reserved for Future Use Wrap Burst Within Burst length set by B2 - B0 Don't Wrap Accesses Within Burst Length set by B2 - B0 Four-word Burst Eight-word Burst Sixteen-word Burst Continuous Burst
B10 B9 B8 B7 B6 B5 - B4 B3 B2 - B0
Notes:
1. Default State 2. Burst configuration setting of B13 - B11 = 010 (clock latency of two), B9 = 1 (hold data for two clock cycles) and B8 = 1 (WAIT asserted one clock cycle before data is valid) is not supported. 3. Data is not ready when WAIT is asserted.
Clock Latency versus Input Clock Frequency
Minimum Clock Latency (Minimum Number of Clocks Following Address Latch) 5, 6 4 2, 3 Input Clock Frequency 66 MHz 61 MHz 40 MHz
Figure 4. Output Configuration
CLK 1 CLK Data Hold (B9 = 0) 2 CLK Data Hold (B9 = 1) I/00 - I/015 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
I/00 - I/015
20
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Table 5. Sequence and Burst Length
Burst Addressing Sequence (Decimal) 4-word Burst Length B2 - B0 = 001 Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-word Burst Length B2 - B0 = 010 Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... ... ... 16-word Burst Length B2 - B0 = 011 Linear 0-1-2...14-15 1-2-3...14-15-0 2-3-4...15-0-1 3-4-5...15-0-1-2 4-5-6...15-0-1-2-3 5-6-7...15-0-1...4 6-7-8...15-0-1...5 7-8-9...15-0-1...6 ... 14-15-0-1...13 15-0-1-2-3...14 ... 1 1 1 1 1 1 1 1 ... ... 1 1 ... ... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 ... 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... 0-1-2...14-15 1-2-3...15-16 2-3-4...16-17 3-4-5...17-18 4-5-6...18-19 5-6-7...19-20 6-7-8...20-21 7-8-9...21-22 ... 14-15...28-29 15-16...29-30 Continuous Burst B2 - B0 = 111 Linear 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20 15-16-17-18-19-20-21 ... 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20 15-16-17-18-19-20-21
Start Addr. (Decimal) 0 1 2 3 4 5 6 7 ... 14 15 ... 0 1 2 3 4 5 6 7 ... 14 15
Wrap B3 = 0 0 0 0 0 0 0 0 0 ... 0 0 ...
Wrap B3 = 1
21
3314A-FLASH-4/04
Memory Organization - AT49SN/SV12804
Plane Plane Size (Bits) Sector SA0 SA1 SA2 SA3 1 SA4 SA5 SA6 4M SA7 SA8 SA9 Size Words 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K x16 Address Range (A22 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF
* * *
1 2
* * *
SA13 SA14 SA15 4M
* * *
32K 32K 32K
* * *
30000 - 37FFF 38000 -3FFFF 40000 - 47FFF
* * *
2 3
* * *
SA22 SA23
* * *
32K 32K
* * *
78000 - 7FFFF 80000 - 87FFF
* * *
3 4
4M
* * *
SA30 SA31
* * *
32K 32K
* * *
B8000 - BFFFF C0000 - C7FFF
* * *
4 5
4M
* * *
SA38 SA39
* * *
32K 32K
* * *
F8000 - FFFFF 100000 - 107FFF
* * *
5 6
4M
* * *
SA46 SA47
* * *
32K 32K
* * *
138000 - 13FFFF 140000 - 147FFF
* * *
6 7
4M
* * *
SA54 SA55
* * *
32K 32K
* * *
178000 - 17FFFF 180000 - 187FFF
* * *
7
4M
* * *
SA62
* * *
32K
* * *
1B8000 - 1BFFFF
22
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Memory Organization - AT49SN/SV12804 (Continued)
Plane 8 Plane Size (Bits) Sector SA63 4M Size Words 32K x16 Address Range (A22 - A0) 1C0000 - 1C7FFF
* * *
8 9
* * *
SA70 SA71
* * *
32K 32K
* * *
1F8000 - 1FFFFF 200000-207FFF
* * *
9 10
4M
* * *
SA78 SA79
* * *
32K 32K
* * *
238000 - 23FFFF 240000 - 247FFF
* * *
10 11
4M
* * *
SA86 SA87
* * *
32K 32K
* * *
278000 - 27FFFF 280000 - 287FFF
* * *
11 12
4M
* * *
SA94 SA95
* * *
32K 32K
* * *
2B8000 - 2BFFFF 2C0000 - 2C7FFF
* * *
12 13
4M
* * *
SA102 SA103
* * *
32K 32K
* * *
2F8000 - 2FFFFF 300000 - 307FFF
* * *
13 14
4M
* * *
SA110 SA111
* * *
32K 32K
* * *
338000 - 33FFFF 340000 - 347FFF
* * *
14 15
4M
* * *
SA118 SA119
* * *
32K 32K
* * *
378000 - 37FFFF 380000 - 387FFF
* * *
15 16
4M
* * *
SA126 SA127
* * *
32K 32K
* * *
3B8000 - 3BFFFF 3C0000 - 3C7FFF
* * *
16
4M
* * *
SA134
* * *
32K
* * *
3F8000 - 3FFFFF
23
3314A-FLASH-4/04
Memory Organization - AT49SN/SV12804 (Continued)
Plane 17 Plane Size (Bits) Sector SA135 4M Size Words 32K x16 Address Range (A22 - A0) 400000 - 407FFF
* * *
17 18
* * *
SA142 SA143
* * *
32K 32K
* * *
438000 - 43FFFF 440000 - 447FFF
* * *
18 19
4M
* * *
SA150 SA151
* * *
32K 32K
* * *
478000 - 47FFFF 480000 - 487FFF
* * *
19 20
4M
* * *
SA158 SA159
* * *
32K 32K
* * *
4B8000 - 4BFFFF 4C0000 - 4C7FFF
* * *
20 21
4M
* * *
SA166 SA167
* * *
32K 32K
* * *
4F8000 - 4FFFFF 500000 - 507FFF
* * *
21 22
4M
* * *
SA174 SA175
* * *
32K 32K
* * *
538000 - 53FFFF 540000 - 547FFF
* * *
22 23
4M
* * *
SA182 SA183
* * *
32K 32K
* * *
578000 - 57FFFF 580000 - 587FFF
* * *
23 24
4M
* * *
SA190 SA191
* * *
32K 32K
* * *
5B8000 - 5BFFFF 5C0000 - 5C7FFF
* * *
24 25
4M
* * *
SA198 SA199
* * *
32K 32K
* * *
5F8000 - 5FFFFF 600000 - 607FFF
* * *
25
4M
* * *
SA206
* * *
32K
* * *
638000 - 63FFFF
24
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Memory Organization - AT49SN/SV12804 (Continued)
Plane 26 Plane Size (Bits) Sector SA207 4M Size Words 32K x16 Address Range (A22 - A0) 640000 - 647FFF
* * *
26 27
* * *
SA214 SA215
* * *
32K 32K
* * *
678000 - 67FFFF 680000 - 687FFF
* * *
27 28
4M
* * *
SA222 SA223
* * *
32K 32K
* * *
6B8000 - 6BFFFF 6C0000 - 6C7FFF
* * *
28 29
4M
* * *
SA230 SA231
* * *
32K 32K
* * *
6F8000 - 6FFFFF 700000 - 707FFF
* * *
29 30
4M
* * *
SA238 SA239
* * *
32K 32K
* * *
738000 - 73FFFF 740000 - 747FFF
* * *
30 31
4M
* * *
SA246 SA247
* * *
32K 32K
* * *
778000 - 77FFFF 780000 - 787FFF
* * *
31 32
4M
* * *
SA254 SA255 SA256
* * *
32K 32K 32K
* * *
7B8000 - 7BFFFF 7C0000 - 7C7FFF 7C8000 - 7CFFFF
* * *
4M
* * *
SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
* * *
32K 4K 4K 4K 4K 4K 4K 4K 4K
* * *
7F0000 - 7F7FFF 7F8000 - 7F8FFF 7F9000 - 7F9FFF 7FA000 - 7FAFFF 7FB000 - 7FBFFF 7FC000 - 7FCFFF 7FD000 - 7FDFFF 7FE000 - 7FEFFF 7FF000 - 7FFFFF
32
25
3314A-FLASH-4/04
DC and AC Operating Range
AT49SN/SV12804-70 Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 1.65V - 1.95V
Operating Modes
Mode Read Burst Read Program/Erase(3) Standby/Program Inhibit CE VIL VIL VIL VIH X Program Inhibit X X Output Disable Reset Product Identification Software
Notes: 1. 2. 3. 4. 5. 6.
OE VIL VIL VIH X(1) X VIL X VIH X
WE VIH VIH VIL X VIH X X X X
RESET VIH VIH VIH VIH VIH VIH X VIH VIL
VPP(4) X X VIHPP(5) X X X VILPP(6) X X
Ai Ai Ai Ai X
I/O DOUT DOUT DIN High Z
X X
High Z X High Z
VIH
A0 = VIL, A1 - A22 = VIL A0 = VIH, A1 - A22 = VIL
Manufacturer Code(3) Device Code(3)
X can be VIL or VIH. Refer to AC programming waveforms. Manufacturer Code: 001FH; Device Code: 00BBH The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 12.0V 0.5V. VIHPP (min) = 0.9V. VILPP (max) = 0.4V.
26
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
DC Characteristics
Symbol ILI ILO ISB1 ICC
(1)
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current VCC Read While Erase Current VCC Read While Write Current Input Low Voltage Input High Voltage Output Low Voltage
Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCCQ - 0.3V to VCC f = 66 MHz; IOUT = 0 mA f = 66 MHz; IOUT = 0 mA f = 66 MHz; IOUT = 0 mA
Min
Max 1 1 20 30 50 50 0.4
Units A A A mA mA mA V V
ICCRE ICCRW VIL VIH VOL VOH Note:
VCCQ - 0.2 IOL = 100 A IOL = 2.1 mA IOH = -100 A IOH = -400 A VCCQ - 0.1 1.4 0.1 0.25
V
Output High Voltage 1. In the erase mode, ICC is 30 mA.
V
Input Test Waveforms and Measurement Level
1.4V AC DRIVING LEVELS 0.4V 0.9V AC MEASUREMENT LEVEL
tR, tF < 5 ns
Output Test Load
VCCQ 1.8K OUTPUT PIN 1.3K
30 pF
Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
27
3314A-FLASH-4/04
AC Asynchronous Read Timing Characteristics
Symbol tACC1 tACC2 tCE tOE tAHAV tAVLP tAVHP tAAV tDF tOH tRO Parameter Access, AVD To Data Valid Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid Address Hold from AVD AVD Low Pulse Width AVD High Pulse Width Address Valid to AVD CE, OE High to Data Float Output Hold from OE, CE or Address, Whichever Occurred First RESET to Output Delay 150 9 10 10 7 25 Min Max 70 70 70 20 Units ns ns ns ns ns ns ns ns ns ns ns
AVD Pulsed Asynchronous Read Cycle Waveform(1)(2)
tCE CE tDF I/O0-I/O15 tACC2 A2 -A22 tAAV tAHAV tACC2 A0 -A1 tAAV tAVHP tAVLP tACC1 OE tRO RESET tOE tAHAV DATA VALID tDF
AVD
(1)
Notes:
1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable. 2. CLK may be static high or static low.
Asynchronous Read Cycle Waveform(1)(2)(3)(4)
tRC A0 - A22 ADDRESS VALID
CE
tCE OE tOE tDF tACC2 tRO HIGH Z OUTPUT VALID tOH
RESET
I/O0 - I/O15
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. AVD and CLK should be tied low.
28
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
AC Asynchronous Read Timing Characteristics
Symbol tACC1 tACC2 tCE tOE tAHAV tAVLP tAVHP tAAV tDF tRO tPAA Parameter Access, AVD To Data Valid Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid Address Hold from AVD AVD Low Pulse Width AVD High Pulse Width Address Valid to AVD CE, OE High to Data Float RESET to Output Delay Page Address Access Time 9 10 10 7 25 150 20 Min Max 70 70 70 20 Units ns ns ns ns ns ns ns ns ns ns ns
Page Read Cycle Waveform 1(1)
tCE CE tDF I/O0-I/O15 tACC2 A2 -A22 tAAV tAHAV tACC2 A0 -A1 tAAV tAVHP tAVLP tACC1 OE tRO RESET tOE tAHAV tPAA DATA VALID tDF
AVD
(1)
Note:
1. After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable.
Page Read Cycle Waveform 2(1)
tCE CE tDF I/O0-I/O15 tACC2 A2 -A22 tPAA tACC2 A0 -A1 DATA VALID tDF
AVD
(1)
VIL tOE tRO RESET
OE
Note:
1. AVD may remain low as long as the page address is stable.
29
3314A-FLASH-4/04
AC Burst Read Timing Characteristics
Symbol tCLK tCKH tCKL tCKRT tCKFT tACK tAVCK tCECK tCKAV tQHCK tAHCK tCKRY tCESAV tAAV tAHAV tCKQV tCEQZ Parameter CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Address Valid to Clock AVD Low to Clock CE Low to Clock Clock to AVD High Output Hold from Clock Address Hold from Clock Clock to WAIT Delay CE Setup to AVD Address Valid to AVD Address Hold From AVD CLK to Data Delay CE High to Output High-Z 10 10 9 13 10 7 7 7 3 3 8 13 Min 15 4 4 3.5 3.5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Burst Read Cycle Waveform
tCLK CLK tAHCK tCECK CE tCE tCESAV tAVCK AVD
(2)
tCKH ... ... tCKL
...
tACK
tCKAV tAAV
tAHAV tQHCK D13 ... D14
tCKQV
tCEQZ
I/O0-I/O15
D15
D16
D17
A0-A21
OE tCKRY WAIT (1) tCKRY
Notes:
1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. After the high-to-low transition on AVD, AVD may remain low.
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AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Burst Read Waveform (Clock Latency of 3)
A CLK B C D E F G
CE
AVD
OE
A0-A21
VALID
I/O0-I/O15
D13
D14
D15
D16
D17
D18
WAIT
(1)
HIGH Z
HIGH Z
Note:
1. Dashed line reflects a B10 and B8 setting of 0 in the configuration register. Solid line reflects a B10 setting of 0 and B8 setting of 1 in the configuration register.
Hold Data for 2 Clock Cycles Read Waveform (Clock Latency of 3)
AVD
CLK
CE
OE
A0-A21
A9
I/O0-I/O15
D13
D14
D15
D16
WAIT(1)
Note:
1. Dashed line reflects a burst configuration register setting of B10 and B8 = 0, B9 = 1. Solid line reflects a burst configuration register setting of B10 = 0, B9 and B8 = 1
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3314A-FLASH-4/04
Four-word Burst Read Waveform (Clock Latency of 4)
A CLK B C
CE
AVD
OE
A0-A21
VALID
I/O0-I/O15
(1)
D0 HIGH Z
D1
D2
D3 HIGH Z
WAIT
Note:
1. The WAIT signal shown is for a burst configuration register of B10 and B8 = 1.
Burst Suspend Waveform
tCLK CLK
(2)
tCKH tCKL
... tAHCK tCECK
CE tCE tCEAV tAVCK AVD tACK tCKAV tAAV I/O0-I/O15 tAHAV tQHCK D0 D1 D1 D2 tCKQV tCEQZ
A0-A21 tDF OE tOE
WAIT (2)
Notes:
1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. During Burst Suspend, CLK signal can be held low or high.
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AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
AC Word Load Characteristics 1
Symbol tAAV tAHAV tAVLP tDS tDH tCESAV tWP tWPH tWEAV tCEAV Parameter Address Valid to AVD High Address Hold Time from AVD High AVD Low Pulse Width Data Setup Time Data Hold Time CE Setup to AVD CE or WE Low Pulse Width CE or WE High Pulse Width WE High Time to AVD Low CE High Time to AVD Low Min 10 9 10 50 0 10 35 25 25 25 Max Units ns ns ns ns ns ns ns ns ns ns
AC Word Load Waveforms 1
WE Controlled(1)
CE
I/O0-I/O15
DATA VALID
A0 -A22 tAAV tAHAV AVD tAVLP tDS tDH tWEAV tWP WE
Note:
1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle.
CE Controlled(1)
WE
I/O0-I/O15
DATA VALID
A0 -A22 tAAV tAHAV AVD tAVLP tCESAV CE tWP tDS tDH tCEAV
Note:
1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle.
33
3314A-FLASH-4/04
AC Word Load Characteristics 2
Symbol tAS tAH tDS tDH tWP tWPH Parameter Address Setup Time to WE and CE High Address Hold Time Data Setup Time Data Hold Time CE or WE Low Pulse Width CE or WE High Pulse Width Min 50 0 50 0 35 25 Max Units ns ns ns ns ns ns
AC Word Load Waveforms 2
WE Controlled(1)
CE
I/O0 - I/O15
DATA VALID
A0 - A22
WE
AVD
VIL
Note:
1. The CLK input should not toggle.
CE Controlled(1)
WE
I/O0 - I/O15
DATA VALID
A0 - A22
CE
AVD
VIL
Note:
1. The CLK input should not toggle.
34
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Program Cycle Characteristics
Symbol tBP tSEC1 tSEC2 tES tPS tERES Parameter Word Programming Time Sector Erase Cycle Time (4K word sectors) Sector Erase Cycle Time (32K word sectors) Erase Suspend Time Program Suspend Time Delay between Erase Resume and Erase Suspend 500 Min Typ 22 200 700 15 10 Max Units s ms ms s s s
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tBP
WE
tAS
tWPH tDH tAH
(1)
A0 - A22
XX
ADDRESS
tWC
tDS
INPUT DATA
I/O0 - I/O15
Note 3
AVD
VIL
Sector, Plane or Chip Erase Cycle Waveforms
OE
(2)
CE
tWP
WE
tAS
tWPH tDH tAH
(1)
A0 - A22
XX
Note 4
tWC
tDS
tSEC1/2
D0
I/O0 - I/O15
Note 5 WORD 0
WORD 1
AVD
VIL
Notes:
1. 2. 3. 4.
Any address can be used to load data. OE must be high only when WE and CE are both low. The data can be 40H or 10H. For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector is to be erased. 5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should be 20H.
35
3314A-FLASH-4/04
Table 6. Common Flash Interface Definition for AT49SN/SV12804
Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h AT49SN/SV12804 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 00B5h 00C5h 0004h 0000h 0009h 0011h 0004h 0000h 0003h 0003h 0018h 0001h 0000h 0000h 0000h 0003h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0007h 0000h 0020h 0000h Typ block erase - 500 ms Typ chip erase - 131,000 ms Max word write/typ time n/a Max block erase/typ block erase Max chip erase/ typ chip erase Device size x16 device x16 device Multiple byte write not supported Multiple byte write not supported 3 regions, x = 3 64K bytes, Y = 253 64K bytes, Y = 253 64K bytes, Z = 256 64K bytes, Z = 256 8K bytes, Y = 7 8K bytes, Y = 7 8K bytes, Z = 32 8K bytes, Z = 32 8K bytes, Y = 7 8K bytes, Y = 7 8K bytes, Z = 32 8K bytes, Z = 32 VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write - 16 s Comments "Q" "R" "Y"
36
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Table 6. Common Flash Interface Definition for AT49SN/SV12804 (Continued)
Address AT49SN/SV12804 Comments
VENDOR SPECIFIC EXTENDED QUERY 41h 42h 43h 44h 45h 46h 0050h 0052h 0049h 0031h 0030h 00BFh "P" "R" "I" Major version number, ASCII Minor version number, ASCII Bit 0 - chip erase supported, 0 - no, 1 - yes Bit 1 - erase suspend supported, 0 - no, 1 - yes Bit 2 - program suspend supported, 0 - no, 1 - yes Bit 3 - simultaneous operations supported, 0 - no, 1 - yes Bit 4 - burst mode read supported, 0 - no, 1 - yes Bit 5 - page mode read supported, 0 - no, 1 - yes Bit 6 - queued erase supported, 0 - no, 1 - yes Bit 7 - protection bits supported, 0 - no, 1 - yes 47h 0002h Bit 8 - top ("0"), bottom ("1"), or both top and bottom ("2") boot block device Undefined bits are "0" Bit 0 - 4 word linear burst with wrap around, 0 - no, 1 - yes Bit 1 - 8 word linear burst with wrap around, 0 - no, 1 - yes Bit 2 - 16 word linear burst with wrap around, 0 - no, 1 - yes Bit 3 - continuos burst, 0 - no, 1 - yes Undefined bits are "0" Bit 0 - 4 word page, 0 - no, 1 - yes Bit 1 - 8 word page, 0 - no, 1 - yes Undefined bits are "0" Location of protection register lock byte, the section's first byte # of bytes in the factory prog section of prot register - 2*n # of bytes in the user prog section of prot register - 2*n - 132 Number of planes - 32 planes
48h
000Fh
49h 4Ah 4Bh 4Ch 4Dh
0003h 0080h 0003h 0007h 0020h
37
3314A-FLASH-4/04
AT49SN/SV12804 Ordering Information
tACC (ns) 70 70 ICC (mA) Active 30 30 Standby 0.01 0.01 Ordering Code AT49SN12804-70CI AT49SV12804-70TI Package 56C3 56T Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C)
Package Type 56C3 56T 56-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 56-lead, Plastic Thin Small Outline Package (TSOP)
38
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Packaging Information
56C3 - CBGA
D
0.12 C
C Seating Plane
E
Side View
Top View
A
A1
1.375 mm Ref
87 6
D1
5 4 3 21
A B C D E F G
E1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A MIN - 0.21 7.90 NOM - - 8.00 5.25 TYP 9.90 10.00 4.50 TYP 0.75 TYP 0.35 TYP 10.10 MAX 1.00 - 8.10 NOTE
e
2.75 mm Ref
e Ob
A1 D D1
Bottom View
E E1 e
Ob
1/9/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 56C3, 56-ball (8 x 7 Array), 8 x 10 x 1.0 mm Body, 0.75 mm Ball Pitch Ceramic Ball Grid Array Package (CBGA) DRAWING NO. 56C3 REV. A
R
39
3314A-FLASH-4/04
56T - TSOP
PIN 1 0 ~ 8 c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation EC. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.20 13.80 0.50 NOM - - 1.00 20.00 18.40 14.00 0.60 0.25 BASIC 0.10 0.10 0.15 - 0.50 BASIC 0.20 0.21 MAX 1.20 0.15 1.05 20.20 18.60 14.20 0.70 Note 2 Note 2 NOTE
10/23/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 56T, 56-lead (14 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 56T REV. C
R
40
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
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3314A-FLASH-4/04 xM

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