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om Shenzhen HB Science & Technology Co,. Ltd .c 4U Inspection Specification et he aS at : To .D : w Date w w CPT TFT-LCD ACCEPTED BYG m o CLAA170EA03 .c U t4 e e h S ta a .D w w w APPROVED BY CHECKED BY PREPARED BY TFT-LCD Plant Application Div. Prepared by : Product Planning Management General Division TFT Business Unit Doc.No: CPT Confidential om .c Shenzhen HB Science & Technology Co,. Ltd 4U BLOCK 1, LONGWU INDUSTRIAL ESTATE SHANGTANG VILLEGE, LONGHUA TOWN et BAOAN DISTRICT, SHENZHEN CITY he GUANG TONG PROVINCE,P.R.CHINA aS TEL: +86-755-28115516 FAX: +86-755-28115795 t a D . Issue Date: w w 0/18 CLAA170EA03- -2003/03/11 w 1. OVERVIEW CLAA170EA03 is 17" color TFT-LCD (Thin Film Transistor Liquid Crystal Display) module composed of LCD panel, RSDS driver ICs, control circuit and backlight. By applying 6 bit digital data, 1280 N 1024, 262K color(6Bit) images are displayed on the 17.0" diagonal screen. Input power voltage is 12.0V for LCD driving. Inverter for backlight is not included in this module. General specification are summarized in the following table: ITEM Display Area(mm) Number of Pixels Pixel Pitch(mm) Color Pixel Arrangement Display Mode Number of Colors Brightness(cd/m^2) Viewing Angle Wide Viewing Angle Technology Surface Treatment Electrical Interface Total Module Power(W) Optimum Viewing Angle Module Size(mm) Module Weight(g) Backlight Unit SPECIFICATION 337.920 (H)x270.336 (V) (17.0-inch diagonal) 1280(H)x1024(V) 0.264(H)x0.264(V) RGB vertical stripe normally white, TN 262144colors(6bit) 300cd/m2(Typ.)(Center point,lamp current:7mA) 140/130(Typ.) Optical Compensation Film Anti-glare RSDS (2 pixel/clock) 20(Typ.) 6 o'clock 358.5(W)x296.5(H)x17.0(D) 1800(typ.) CCFL, 4 tables, edge-light(top*2/bottom*2) The LCD Products listed on this document are not suitable for use of aerospace equipment, submarine cables, nuclear reactor control system and life support systems. If customers intend to use these LCD products for above application or not listed in "Standard" as follows, please contact our sales people in advance. Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tool, Industrial robot, Audio and Visual equipment, Other consumer products. 2. ABSOLUTE MAXIMUM RATINGS ITEM Power Supply Voltage for LCD Logic Input Voltage Static Electricity ICC Rush Current IDD Rush Current Lamp Voltage Lamp Current Lamp Frequency Operation Temperature Storage Temperature SYMBOL V CC VD DD Vt ESD Vc ESD I RU c SH I RU d SH V L IL FL Top Tstg MIN. - 0. 3 - 0. 3 - 200 - 8000 0 0 0 - 20 MAX. 20.0 5.0 200 8000 3.0 0.75 2500 10.0 100 50 60 UNIT V V V V A A Vm rs m rm As kH z J J Note: Test Condition: IEC 1000-4-2 , VESDt G Contact discharge to input connector VESDcG Contact discharge to module 50g sec , If Vcc rise time increase then IRUSH decrease. HumidityG HumiditO 85%RH without condensation. Relative Humidity O 95% (TaO 40J ) Wet Bulb Temperature O 39J (TaU 40J ) HumidityO40J: Relative HumidityO 90MRH without condensation. Top B Tstg Top B Tstg HumidityO40J:40 JA Absolute HumidityO 90MRH without condensation. 3. ELECTRICAL CHARACTERISTICS (a)TFT-LCD ITEM Power Supply Voltage for Logic Power Supply Current for Logic Permissive Ripple Voltage for Logic Power Supply Voltage Power Supply Current Permissive Ripple Voltage Differential impendence High Input Threshold Voltage Low SYMBOL VDDD IDDD VDRP VCC ICC VCRP Zm VIH VIL MIN 3.0 --10.8 -90 2.5 0 TYP 3.3 40 -12.0 100 100 3.3 -MAX 3.6 100 30 13.2 250 100 110 3.6 0.8 UNIT Remark V mA mVp-p V=+3.3V V mA mVp-p V=+12.0V [ V V [Note 1] Power sequence 0 DATA 90% 90% VDDD VCC BackLight T1 T2 T3 T4 T5 T6 VCC-dip conditions 1)When 8.64VO Vin(min)<10.8V tdO 10 ms 2)When VCCO 8.64V VCC-dip conditions should also follow the VCC-turn-on conditions. Vin=12V 10.8V td [Note 2] Typical current situation : 64-gray-bar pattern, 1280 line mode VCC=12.0 VA fH=64 kHzA fV=60 HzA fCLK=54 MHz VDDD=3.3 VA fH=64 kHzA fV=60 HzA fCLK=54 MHz 8.64V (b)Backlight ITEM Lamp Voltage Lamp Current Interter Frequency Starting Lamp Voltage SYMBOL VL IL FL VS MIN -5. 0 45 1350 1080 -Lamp life Time LT -40, 000 -hr TYP 710 7. 0 50 50, 000 MAX -8. 0 70 -UNIT V mA kHz V V hr REMARK IL=7.0mA Note1 Note2 Tb=0JA Note3 Ta=25JA Note3 IL=6.0mA Continuous Operation IL=7.0mA Continuous Operation [Note 1] Lamp Current measurement method ( The current meter is inserted in cold line) CTL A CTH CTH CTL Power Supply LCD Module A CTH CTH INVERTER [Note 2] Lamp frequency of inverter may produce interference with horizontal synchronous frequency,and this may cause horizontal beat on the display.Therefore,please adjust lamp frequency,and keep inverter as far from module as possible or use electronic shielding between inverter and module to avoid the interference. The degrees of unbalance: less than 10% The ratio of wave height: less than O 2 O 10% Ip IpGhi gh side peak I-p I-pGlow side peak AGThe degrees of unbal = Ip - I-pW/ Irms x100 (%) ance W BGThe ratio of wave hei ht = Ip (or I-p) / Irms g [Note 3] Definition of the lamp life time Luminance: L under 50% of specification CPT (C) RSDS CHARACTERISTICS ITEM RSDS Input high voltage high level RSDS Input high voltage low level RSDS common mode Input voltage range RSDS leakage of input current [Note] Disallow Disclosure, Reproduction or Distribution SYMBOL CONDICTION MIN 100 1.0 -10 TYP 200 -200 - MAX UNIT -100 1.4 10 mV mV V uA VIHRSD VCMRSDS=+1.2V S VILRSDS VCMRSDS=+1.2V VCMRS VDIFFRSDS (2) = 200 mV (minimum value) DS IDL DxxP,DxxN,CLKP,CL KN 1. VCMRSDS = (VCLKP + VCLKN) / 2 or VCMRSDS = (VDxxP + VDxxN) / 2 2. VDIFFRSDS = VCLKP - VCLKN or VDIFFRSDS = VDxxP - VDxxN RSDS Standard V-p to Vp value is 400mV from-200mV to +200mV. VRSDSN VIHRSDS VILRSDS VCMRSDS VRSDSP GND (VRSDSP)-(VRSDSN) VIHRSDS VILRSDS 0V RSDS signal definition CPT Disallow Disclosure, Reproduction or Distribution 4. INTERFACE PIN CONNECTION (a)CN1(Data Signal and Power Supply) Used connector:IL-FHR-B30S-HF(JAE) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 symbol GND B2P_B B2N_B GND B1P_B B1N_B GND B0P_B B0N_B GND G2P_B G2N_B GND G1P_B G1N_B GND G0P_B G0N_B GND CLKP_B CLKN_B GND R2P_B R2N_B GND R1P_B R1N_B GND R0P_B R0N_B Function Ground RSDS Blue Data(+)( Back side) RSDS Blue Data(-)( Back side) Ground RSDS Blue Data(+)( Back side) RSDS Blue Data(-)( Back side) Ground RSDS Blue Data(+)( Back side) RSDS Blue Data(-)( Back side) Ground RSDS Green Data (+)( Back side) RSDS Green Data (-)( Back side) Ground RSDS Green Data (+)( Back side) RSDS Green Data (-)( Back side) Ground RSDS Green Data (+)( Back side) RSDS Green Data (-)( Back side) Ground Source Driver IC RSDS CLK (+)( Back side) Source Driver IC RSDS CLK (-)( Back side) Ground RSDS Red Data (+)( Back side) RSDS Red Data (-)( Back side) Ground RSDS Red Data (+)( Back side) RSDS Red Data (-)( Back side) Ground RSDS Red Data (+)( Back side) RSDS Red Data (-)( Back side) (b)CN2 Used connector: IL-FHR-B50S-HF(JAE) Pin NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 symbol GND B2P_F B2N_F GND B1P_F B1N_F GND B0P_F B0N_F GND G2P_F G2N_F GND G1P_F G1N_F GND G0P_F G0N_F GND CLKP_F Function Ground RSDS Blue Data(+)( Front side) RSDS Blue Data(-)( Front side) Ground RSDS Blue Data(+)( Front side) RSDS Blue Data(-)( Front side) Ground RSDS Blue Data(+)( Front side) RSDS Blue Data(-)( Front side) Ground RSDS Green Data (+)( Front side) RSDS Green Data (-)( Front side) Ground RSDS Green Data (+)( Front side) RSDS Green Data (-)( Front side) Ground RSDS Green Data (+)( Front side) RSDS Green Data (-)( Front side) Ground Source Driver IC RSDS CLK (+)( Front side) CPT 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CLKN_F GND R2P_F R2N_F GND R1P_F R1N_F GND R0P_F R0N_F GND STH_F LP POL STH_B GND CLKV STV OE VCOM(test) GND 3.3V 3.3V 12V GND 12V 12V 12V NC NC Disallow Disclosure, Reproduction or Distribution Source Driver IC RSDS CLK (-)( Front side) Ground RSDS Red Data (+)( Front side) RSDS Red Data (-)( Front side) Ground RSDS Red Data (+)( Front side) RSDS Red Data (-)( Front side) Ground RSDS Red Data (+)( Front side) RSDS Red Data (-)( Front side) Ground Source Driver IC Start pulse( Front side) Source Driver IC Latch Pulse Source Driver M signal Source Driver IC Start pulse( Back side) Ground Gate Driver IC Start pulse Gate Driver IC Output Enable N.C. Ground Power Supply Voltage for Logic Power Supply Voltage for Logic LCD Power Supply Ground LCD Power Supply LCD Power Supply LCD Power Supply NC NC (C)CN3,4(BACKLIGHT) Backlight-side connector: BHR-04VS-1(JST) Inverter-side connector: SM04(4.0)B-BHS-1-TB(JST) Pin No. 1 2 3 4 Symbol CTH1 CTH2 CTL1 Function VBLH1(HIGH VOLTAGE) VBLH2(HIGH VOLTAGE) VBLL(LOW VOLTAGE) [Note] VBLH-VBLL = VL CPT Disallow Disclosure, Reproduction or Distribution 5. INTERFACE TIMING (a) Timing Specifications Item LCD Timing Frequenc DCLK Symbol fCLK tCLK Min 41.6 14.8 Typ 54 18.5 Max 67.5 24 Unit MHz ns period Horizontal signal: Item CLK pulse width CLK pulse width CLK pulse width DATA set-up time DATA hold time STH set-up time STH hold time STH pulse width LP pulse width (H) LP to STH setup time Symbol Tw Twh Twl Tst1 Thd1 Tst2 Thd2 Twsth Twlp Tlp-sth Last data time CLK-LP time LP-POL time POL-LP time Tldt Tclk-lp Tlp-pol Tpol-lp Min 14 6 6 4 0.2 4 4 1 (48) 5 1 4 (640) (7) Typ 18.5 1 - Max 24 2 (53) - - (784) (30) Unit ns ns ns ns ns ns ns CLKP period CLKP period CLKP period CLKP period ns CLKP period CLKP period Vertical sigal: Item STV set-up time STV hold time CLKV period CLKV High width CLKV Low width OE pulse width OE-CLKV time LP rise-CLKV rise time Symbol tst(STV) thd(STV) tw(CLKV) twH(CLKV) twL(CLKV) Tw(OE) tOE-CLKV tLP-CLKV MIN TYP MAX Unit s s s s s s s ns 1 1 8 3.5 3.5 2.4 1.5 0 2.9 2 0 3.4 3 0 CPT (b) Timing Chart a. Horizontal Timing Chart Timing Diagram 1 CLKP_F-CLKN_F (RSDS) Disallow Disclosure, Reproduction or Distribution CLKP_B-CLKN_B (RSDS) STH_F 50% 50% 10% TWSTH_F TLDT 50% 10% STH_B 50% TLP-STH_F DxxP_F-DxxN_F (RSDS) Invalid EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD Invalid 1st Data 2nd Data Last Data DxxP_B-DxxN_B (RSDS) Invalid EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD Invalid TLP-CLKP 1st Data 2nd Data Last Data 90% 10% TWLP 90% 10% LP TPOL-LP TLP-POL 90% 10% POL Invalid 90% 10% Invalid } dd _F CLKP_CLKN_B (RSDS) _F STH_B _F DxxP-DxxN_B (RSDS) CPT b. Vertical Timing Chart Disallow Disclosure, Reproduction or Distribution Vertical Signal 1 tw(CLKV) CLKV twL(CLKV) twH(CLKV) STV tst(S TV) thd(STV) tw(OE ) OE LP tOE-CLKV tLP-CLKV [Note]GSTVBCLKV output signal speci i ons evel is VOL(MAX)=80%BVOH(MIN)=20%. ficat l c. Color Data Assignment COLOR INPUT DATA R5 R4 MSB 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 R DATA R3 R2 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 R1 0 1 0 0 0 1 1 1 0 0 1 BASIC COLOR BLACK RED(63) GREEN(63) BLUE(63) CYAN MAGENTA YELLOW WHITE RED(0) RED(1) RED(2) G DATA R0 G5 G4 G3 G2 G1 G0 LSB MSB LSB 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 1 1 1 0 1 0 0 0 B DATA B3 B2 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1 1 1 0 1 0 0 0 B1 0 0 0 1 1 1 0 1 0 0 0 B0 LSB 0 0 0 1 1 1 0 1 0 0 0 RED RED(62) RED(63) GREEN(0) GREEN(1) GREEN(2) GREEN GREEN(62) GREEN(63) BLUE(0) BLUE(1) BLUE(2) BLUE BLUE(62) BLUE(63) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [Note] (1)Definition of gray scale: Color(n) : n indicates gray scale level. Higher n means brighter level. (2) Data:1-High,0-Low. (d)Color Data Assignment D(1,1) D(1,2) .. D(1,Y) .. D(1,1023) D(1,1024) D(2,1) D(2,2) .. D(2,Y) .. D(2,1023) D(2,1024) .. .. + .. + .. .. D(X,1) D(X,2) .. D(X,Y) .. D(X,1023) D(X,1024) .. .. + .. + .. .. D(1280,1) D(1280,2) .. D(1280,Y) .. D(1279,Y) D(1279,1023) D(1279,1024) CPT Disallow Disclosure, Reproduction or Distribution 6. BLOCK DIAGRAM TFT-LCD Module CN1 Backlight Back RSDS Signals Voltag e Suppl for y Gray Level And Vcom CN3 Source Board FrontRSDS Si s gnal Gate Board SXGA 1280*1024 TFT Panel Cont ol Signal r s +12V DC Input DC-DC Convert er Backlight CN4 BACK LIGHT CCFL CN3,4 1 2 4 INVERTER CIRCUIT (OUT SIDE) CN3,4 1 2 4 DC-AC Inverter LIGHT CONTROL CPT Disallow Disclosure, Reproduction or Distribution 7. MECHANICAL SPECIFICATION (a) Front side Unit: mm Tolerance is O 0.5mm unless noted CPT (b) Rear side Disallow Disclosure, Reproduction or Distribution Unit: mm Tolerance is O 0.5mm unless noted CPT Disallow Disclosure, Reproduction or Distribution 8.OPTICAL CHARACTERISTICS Ta = 25C , Vcc=12.0V ITEM Contrast Ratio Normal Uniformit Normal Uniformit SYMBO L CR L L Tf Ti s r r Wx Wy Rx Ry Gx Gy Bx By CONDITION 2hour -- 75~75 - 60~60 0.283 0.299 0.607 0.314 0.280 0.552 -- 85~85 - 70~70 0.313 0.329 0.637 0.344 0.310 0.582 2 --0.343 0.359 0.667 0.374 0.340 0.612 MIN. TYP. MAX. UNIT Luminance 9 point % % Response Time Image Sticking Horizontal Vertical Viewing Angle Horizontal Vertical White Red Color Coordinates Green Blue s ec [Note] These items are measured using CS-1000 (MINOLUTA) OR BM-5A(TOPCON)under the dark room condition( no ambient light) after more than 30 minutes from turning on the lamp unless noted. Condition: IL=7.0*4(lamp)mA, Inverter Frequency=50kHz. Definition of these measurement items are as follows: (1)Definition of Contrast RatioG CR=ON(White)Luminance/OFF(Black)Luminance (2) Definition of Luminance and Luminance uniformity Measure White Luminance on the below center(5)A 5 point(5,10,11,12,13) and 9 point(1~9). UniformityG 5 point G W 1/10 W (1,1) 256 512 768 7 320 4 12 8 1 10 2 11 3 1/10 H 5 13 6 H 9 (1280,1024) 640 960 CPT Disallow Disclosure, Reproduction or Distribution (3) Definition of Viewing Angle(c ,r ) Upper(+) c r Left(-) Right(+) LCD Panel (4)Definition of Response Time (5) Image sticking: Continuously display the test pattern shown in the figure below for two-hours. Then display a completely white screen. The previous image shall not persist more than two seconds at 25J . CPT Disallow Disclosure, Reproduction or Distribution TEST PATTERN FOR IM AGE STICKING TEST Cols 638-642 W hite Area Rows 510-514 Black Lines 9.RELIABILITY TEST CONDITIONS (1) Temperature and Humidity TEST ITEMS HIGH TEMPERATURE HIGH HUMIDITY OPERATION HIGH TEMPERATURE HIGH HUMIDITY STORAGE HIGH TEMPERATURE OPERATION LOW TEMPERATURE STORAGE THERMAL SHOCK HIGH TEMPERATURE STORAGE LOW TEMPERATURE OPERATION CONDITIONS 40J ; 95%RH; 240h (No condensation) 60J ; 90%RH;48h (No condensation) 50J ; 240h -20J ; 240h BETWEEN -20J (1hr)AND 60J (1hr); 100 CYCLES 60J ; 240h 0J ; 240h (2)Shock & Vibration ITEMS CONDITIONS SHOCK Shock level:1470m/s^2(150G) (NON-OPERATION) Waveform: half sinusoidal wave, 2ms Number of shocks: one shock input in each direction of three mutually perpendicular axes for a total of six shock inputs VIBRATION Vibration level: 9.8m/s^2(1.0G) zero to peak (NON-OPERATION) Waveform: sinusoidal Frequency range: 5 to 500 Hz Frequency sweep rate: 0.5 octave/min Duration: one sweep from 5 to 500Hz in each of three mutually perpendicular axis(each x,y,z axis: 1 hour, total 3 hours) (3)Judgment standard The judgment of the above test should be made as follow: Pass: Normal display image with no obvious non-uniformity and no line defect. Partial transformation of the module parts should be ignored. Fail: No display image, obvious non-uniformity, or line defects. CPT Disallow Disclosure, Reproduction or Distribution 10. HANDLING PRECAUTIONS FOR TFT-LCD MODULE Please pay attention to the followings in handling- TFT-LCD products; 1 ASSEMBLY PRECAUTION (1) Please use the mounting hole on the module side in installing and do not beading or wrenching LCD in assembling. And please do not drop, bend or twist LCD module in handling. (2) Please design display housing in accordance with the following guide lines. (2.1) Housing case must be destined carefully so as not to put stresses on LCD all sides and not to wrench module. The stresses may cause non-uniformity even if there is no non-uniformity statically. (2.2) Keep sufficient clearance between LCD module back surface and housing when the LCD module is mounted. Approximately 1.0 mm of the clearance in the design is recommended taking into account the tolerance of LCD module thickness and mounting structure height on the housing. (2.3) When some parts, such as, FPC cable and ferrite plate, are installed underneath the LCD module, still sufficient clearance is required, such as 0.5mm. This clearance is, especially, to be reconsidered when the additional parts are implemented for EMI countermeasure. (2.4) Design the inverter location and connector position carefully so as not to give stress to lamp cable, or not to interface the LCD module by the lamp cable. (2.5) Keep sufficient clearance between LCD module and the others parts, such as inverter and speaker so as not to interface the LCD module. Approximately 1.0mm of the clearance in the design is recommended. (3) Please do not push or scratch LCD panel surface with any-thing hard. And do not soil LCD panel surface by touching with bare hands. ( Polarizer film, surface of LCD panel is easy to be flawed.) (4) Please do not press any parts on the rear side such as source TCP, gate TCP, control circuit board and FPCs during handling LCD module. If pressing rear part is unavoidable, handle the LCD module with care not to damage them. (5) Please wipe out LCD panel surface with absorbent cotton or soft cloth in case of it being soiled. (6) Please wipe out drops of adhesives like saliva and water on LCD panel surface immediately. They might damage to cause panel surface variation and color change. (7) Please do not take a LCD module to pieces and reconstruct it. Resolving and reconstructing modules may cause them not to work well. (8) Please do not touch metal frames with bare hands and soiled gloves. A color change of the metal frames can happen during a long preservation of soiled LCD modules. (9) Please pay attention to handling lead wire of backlight so that it is not tugged in connecting with inverter. 2 OPERATING PRECAUTIONS (1) Please be sure to turn off the power supply before connecting and disconnecting signal input cable. (2) Please do not change variable resistance settings in LCD module. They are adjusted to the most suitable value. If they are changed, it might happen LCD does not satisfy the characteristics specification. (3) Please consider that LCD backlight takes longer time to become stable of radiation characteristics in low temperature than in room temperature. (4) A condensation might happen on the surface and inside of LCD module in case of sudden change of ambient temperature. (5) Please pay attention to displaying the same pattern for very long time. Image might CPT Disallow Disclosure, Reproduction or Distribution stick on LCD. If then, time going on can make LCD work well. (6) Please obey the same caution descriptions as ones that need to pay attention to ordinary electronic parts. 3 PRECAUTIONS WITH ELECTROSTATICS (1) This LCD module use CMOS-IC on circuit board and TFT-LCD panel, and so it is easy to be affected by electrostatics. Please be careful with electrostatics by the way of your body connecting to the ground and so on. (2) Please remove protection film very slowly on the surface of LCD module to prevent from electrostatics occurrence. 4 STORAGE PRECAUTIONS (1) When you store LCDs for a long time, it is recommended to keep the temperature between 0J ~40J without the exposure of sunlight and to keep the humidity less than 90%RH. (2) Please do not leave the LCDs in the environment of high humidity and high temperature such as 60J 90%RH. (3) Please do not leave the LCDs in the environment of low temperature; below -20J . 5 SAFETY PRECAUTIONS (1) When you waste LCDs, it is recommended to crush damaged or unnecessary LCDs into pieces and wash them off with solvents such as acetone and ethanol, which should later be burned. (2) If any liquid leaks out of a damaged-glass cell and comes in contact with the hands, wash off throughly with soap and water. 6 OTHERS (1) A strong incident light into LCD panel might cause display characteristics' changing inferior because of polarizer film, color filter, and other materials becoming inferior. Please do not expose LCD module direct sunlight Land strong UV rays. (2) Please pay attention to a panel side of LCD module not to contact with other materials in preserving it alone. (3) For the packaging box, please pay attention to the followings: (3.1) Packaging box and inner case for LCD are designed to protect the LCDs from the damage or scratching during transportation. Please do not open except picking LCDs up from the box. (3.2) Please do not pile them up more than 3 boxes. (They are not designed so.) And please do not turn over. (3.3) Please handle packaging box with care not to give them sudden shock and vibrations. And also please do not throw them up. (3.4) Packing box and inner case for LCDs are made of cardboard. So please pay attention not to get them wet. (Such like keeping them in high humidity or wet place can occur getting them wet.) |
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