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NCP5306 Three-Phase VRM 9.0 Buck Controller
Multiphase controllers provide fast, accurate regulation with the control features required to power the next generation of processors in desktop, workstation and server applications. Combined with external gate drivers and power components, the NCP5306 implements a compact, highly integrated buck converter. Enhanced V2TM control inherently compensates for variations in both line and load. Current sharing between phases is achieved by Peak Current Sharing. The NCP5306 includes Power Good with a programmable lower threshold. Applications include Embedded Processor Power and low voltage/high current power supplies. Features
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24 1 SO-24L DW SUFFIX CASE 751E
* Switching Regulator Controller - Lossless Current Sensing - Enhanced V2 Control Method Provides Excellent Regulation
and Fast Transient Response - Programmable Up to 800 kHz Switching Frequency (Per Phase) - Duty Cycle - 0% to 100% - Programmable Adaptive Voltage Positioning Reduces Output Capacitor Requirements - Programmable Soft Start Accurate Current Sharing Protection Features - Pulse-by-Pulse Current Limit for Each Phase - Programmable Hiccup Overcurrent Protection - All "1" DAC Code Fault - Processor Overvoltage Protection through Bottom MOSFETs - Undervoltage Lockout System Power Management - 5-Bit DAC With 1.0% Tolerance Compatible with VRM 9.0 - Power Good Output - Programmable Power Good Lower Threshold Guaranteed Startup at -20C
MARKING DIAGRAM
24 NCP5306 AWLYYWW 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
* *
PIN CONNECTIONS
GND OCSET ROSC CS3 CS2 CS1 NC CSREF VDRP VFB COMP SS 1 24 VCC GATE3 GATE2 GATE1 NC VID0 VID1 VID2 VID3 VID4 PWRGDS PWRGD
*
*
ORDERING INFORMATION
Device NCP5306DW NCP5306DWR2 Package SO-24L SO-24L Shipping 30 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. 3
1
Publication Order Number: NCP5306/D
NCP5306
+12 V
BST TG
DRN
CO
6.2 V
5.5 V
VOUT
NCP5351
ENABLE PGND PGND DRN PGND DRN VS BG VS BG BST TG VS BG BST TG
GND
GND OCSET ROSC CS3
VCC GATE3 GATE2 GATE1
CO
NCP5306
CS1 NC CSREF VDRP VFB COMP SS
VID1 VID2 VID3 VID4
PWRGDS PWRGD
PWRGD VID4 VID3 VID2 VID1 VID0
Figure 1. Application Diagram, 12 V to 1.5 V/60 A Three-Phase Converter
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2
ENABLE
CO
ENABLE
CS2
NC VID0
NCP5351
NCP5351
NCP5306
MAXIMUM RATINGS*
Rating Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) Package Thermal Resistance Junction-to-Case, RJC Junction-to-Ambient, RJA Lead Temperature Soldering: Reflow (Note 1.) MSL 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Value 150 -65 to 150 2.0 16 80 230 peak Level 1 Unit C C kV C/W C/W C -
MAXIMUM RATINGS
Pin Number 1 2 3 4-6 7, 20 8 9 10 11 12 13 14 15-19 21-23 24 Pin Symbol GND OCSET ROSC CS3-CS1 NC CSREF VDRP VFB COMP SS PWRGD PWRGDS VID4-VID0 GATE1-GATE3 VCC VMAX N/A 7.0 V 7.0 V 7.0 V - 7.0 V 7.0 V 7.0 V 7.0 V 7.0 V 18 V 7.0 V 18 V 7.0 V 18 V VMIN N/A -0.3 V -0.3 V -0.3 V N/A -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE 0.4 A, 1.0 s, 100 mA DC 1.0 mA 1.0 mA 1.0 mA - 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 0.1 A, 1.0 s, 25 mA DC 100 mA ISINK N/A 1.0 mA 1.0 mA 1.0 mA - 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 10 mA 1.0 mA 1.0 mA 0.1 A, 1.0 s, 25 mA DC 1.0 mA
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NCP5306
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEx = 100 pF, CCOMP = 0.01F, CSS = 0.1F, CVCC = 0.1F, RROSC = 32.4 k, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Test Conditions Min Typ Max Unit Voltage Identification DAC (0 = Connected to GND, 1 = Open or Pull-Up to Internal 3.3 V or External Voltage 12 V) Accuracy (all codes) VID code VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VID4, VID3, VID2, VID1, VID0 0 V < VID4, VID3, VID2,VID1, VID0 < 3.3 V 1.089 1.114 1.139 1.163 1.188 1.213 1.238 1.263 1.287 1.312 1.337 1.361 1.386 1.411 1.436 1.460 1.485 1.510 1.535 1.560 1.584 1.609 1.634 1.658 1.683 1.708 1.733 1.757 1.782 1.807 1.832 1.00 25 Output Off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850 1.25 50 1.111 1.136 1.162 1.187 1.212 1.237 1.263 1.288 1.313 1.338 1.364 1.389 1.414 1.439 1.465 1.490 1.515 1.540 1.566 1.591 1.616 1.641 1.667 1.692 1.717 1.742 1.768 1.793 1.818 1.843 1.869 1.5 100 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V k Connect VFB to COMP, Measure COMP -1.0 - +1.0 %
Input Threshold Input Pull-Up Resistance
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NCP5306
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEx = 100 pF, CCOMP = 0.01F, CSS = 0.1F, CVCC = 0.1F, RROSC = 32.4 k, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Test Conditions Min Typ Max Unit Voltage Identification DAC (0 = Connected to GND, 1 = Open or Pull-Up to Internal 3.3 V or External Voltage 12 V) (continued) Pull-Up Voltage Power Good Output Upper Threshold Lower Threshold Switch Leakage Current Delay Output Low Voltage Voltage Feedback Error Amplifier VFB Bias Current Comp Source Current Comp Sink Current Transconductance Output Impedance Open Loop DC Gain Unity Gain Bandwidth PSRR @ 1.0 kHz COMP Max Voltage COMP Min Voltage PWM Comparators Minimum Pulse Width Transient Response Time - Measured from CSREF to GATEx, COMP = 2.1 V, CSx = CSREF = 0.5 V, CSREF stepped from 1.2 V-2.0 V CSx = CSREF = VFB = 0 V, measure VCOMP when GATEx switch high 50% Duty Cycle, Note 3 - - 40 40 70 60 ns ns VFB = 0 V VFB = 1.6 V Note 3 - - Note 2 COMP = 0.5 V to 2.0 V, VFB = 1.8 V, DAC = 00000 COMP = 0.5 V to 2.0 V, VFB = 1.15 V, DAC = 11110 -10 A < ICOMP < +10 A, Note 3 - 9.9 15 15 200 - 45 - - 2.4 - 10.25 30 30 500 2.5 95 50 60 2.7 50 10.6 60 60 750 - - - - - 150 A A A mho M dB kHZ dB V mV Force PWRGDS Force PWRGDS VCC = 14 V, PWRGDS = 1.4 V PWRGDS low to PWRGD low PWRGDS = 1.0 V, IPWRGD = 4.0 mA 1.876 (-5%) -5% - 100 - 1.975 VID/2 0.1 800 0.15 2.074 (+5%) +5% 1.0 2000 0.4 V V A s V 1.0 M to GND 2.5 2.7 3.0 V
Channel Start-Up Offset
350
600
750
mV
Artificial Ramp Amplitude Gates High Voltage Low Voltage
-
115
-
mV
Measure GATEx IGATEx = 1.0 mA Measure GATEx, IGATEx = 1.0 mA
2.0 -
2.6 0.5
3.0 0.7
V V
2. The VFB Bias Current changes with the value of ROSC per Figure 4. 3. Guaranteed by design. Not tested in production.
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NCP5306
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEx = 100 pF, CCOMP = 0.01F, CSS = 0.1F, CVCC = 0.1F, RROSC = 32.4 k, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Gates Rise Time Fall Time Oscillator Switching Frequency Switching Frequency Switching Frequency ROSC Voltage Phase Delay Adaptive Voltage Positioning VDRP Output Voltage to DACOUT Offset Maximum VDRP Voltage CSx = CSREF, VFB = COMP, Measure VDRP - COMP CSx - CSREF = 50 mV, VFB = COMP, TA = 25C, Measure VDRP - COMP CSx - CSREF = 50 mV, VFB = COMP, TA = 25C, Measure VDRP - COMP (V@temp * V@room) @ 106 DT @ V@room CSx - CSREF = 50 mV, VFB = COMP, Measure VDRP - COMP VDRP = 1.5 V -5.0 500 0 560 5.0 625 mV mV - ROSC = 32.4 k ROSC = 66.5 k, Note 4 ROSC = 15.4 k, Note 4 300 150 600 0.90 105 400 200 800 1.00 120 500 250 1000 1.10 140 kHz kHz kHz V deg 0.8 V < GATEx < 2.0 V, VCC = 10 V 2.0 V > GATEx > 0.8 V, VCC = 10 V - - 5.0 5.0 20 20 ns ns Test Conditions Min Typ Max Unit
Current Sense Input to VDRP Gain Temperature Coefficient of VDRP Gain VDRP Source Current Limit
3.33
3.75
4.17
V/V
- 1.0
-850 7.0
- 14
ppm/C mA
Soft Start SS Source Current SS Sink Current SS Min Threshold SS Max Threshold SS Source/Sink Ratio SS COMP Pull Down Current Current Sense Amplifiers CSREF Input Bias Current CSx Input Bias Current Sense Amp Gain CSREF = CSx = 0 V CSREF = CSx = 0 V CSREF = 0 V, CSx = 0.05 V, Measure V(COMP) when GATEx switches high Note 4 - VFB = CSREF = 1.5 V, COMP = 2.0 V, Measure CSx - CSREF when GATEx goes low - - - 2.6 0.1 2.60 3.0 1.0 - A A V/V VCC = 10 V VCC = 10 V VCC = 7.0 V VCC = 10 V VCC = 10 V - 130 4.0 0.25 2.4 20 200 160 5.0 0.3 2.7 32 900 200 6.25 0.35 - 48 3000 A A V V - A
Common Mode Input Range Bandwidth Single Phase Pulse by Pulse Current Limit
0 - 75
- 7.0 85
2.0 - 100
V MHz mV
4. Guaranteed by design. Not tested in production.
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NCP5306
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEx = 100 pF, CCOMP = 0.01F, CSS = 0.1F, CVCC = 0.1F, RROSC = 32.4 k, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Current Sense Amplifiers OCSET Input Bias Current Current Sense Input to OCSET Gain Current Limit Filter Slew Rate General Electrical Specification VCC Operating Current UVLO Start Threshold UVLO Stop Threshold UVLO Hysteresis COMP = 0.3 V (no switching) SS Charging Gates Switching Gates not switching, SS & COMP discharging Start-Stop - 8.5 7.5 0.8 20 9.0 8.0 1.0 30 9.5 8.5 1.2 mA V V V OCSET = 0 V OCSET/(CSx-CSREF), 0.25 V < OCSET < 0.6 V, GATEx not switching CSREF = 1.1 V, CSx = 1.0 V, pulse CSx to 1.16 V, Note 5. - 3.2 0.1 3.7 1.0 4.3 A V/V Test Conditions Min Typ Max Unit
2.0
5.0
13
mV/s
5. Guaranteed by design. Not tested in production.
PACKAGE PIN DESCRIPTION
Pin Number 1 2 3 4-6 7, 20 8 9 Pin Symbol GND OCSET ROSC CS3-CS1 NC CSREF VDRP Pin Name Ground Overcurrent Set Oscillator Frequency Adjust Current Sense Inputs No Connect Current Sense Reference Current Sense Amp Output Voltage Feedback Error Amp Output and PWM Comparator Input Soft Start Power Good Output Power Good Sense DAC VID Inputs Function IC power supply return. Connected to IC substrate. Resistor divider from ROSC to GND. Programs the threshold of the hiccup overcurrent protection. ROSC is a regulated 1.0 V output and programs the oscillator frequency with a resistor to GND. Non-inverting inputs to the current sense amplifiers. Pins not connected to IC. Inverting input to the current sense amplifiers and reference for Power Good. Programs the voltage drop due to loading. A resistor from VDRP to FB programs the amount of Adaptive Voltage Positioning. Omitting this resistor defeats the AVP function. Error Amplifier inverting input. Input bias current is used to program AVP light load offset via a resistor connected to the converter output voltage. Provides loop compensation and is clamped by SS. Controls fault timing and startup. Open collector output, which is "low" when the converter output is out of regulation. A resistor divider from VOUT to GND programs the Power Good lower threshold. TTL-compatible logic input used to program the converter output voltage. Internal 50 k pull-ups to 3.3 V via a blocking diode are provided. All high generates fault. PWM outputs to drive FET driver IC. IC bias input.
10 11 12 13 14 15-19
VFB COMP SS PWRGD PWRGDS VID4-VID0
21-23 24
GATE3-1 VCC
Channel Outputs Supply Input
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VCC + Soft Start Latch OC Comparator ILIM1 Comparator - + 0.3 V R Discharge Comparator PWM2 Comparator - + + - - + CO2F 5.0 A - + Internal Ramp 3 1.975 V - + - - + + - + - CO3F CO3 CO2 0.31 V VCC CO1F CO1 - + + - Reset Dominant - + + - S Set Dominant S Internal Ramp 1 PWM1 Comparator - + PWM1 Latch R VCC
Start Stop
- FAULT
UVLO Comparator
OCSET
50 k VID = 11111 (Output Off) DAC OUTPUT 160 A 3.3 V Internal Ramp 2
*0.5 V/V
ILIM2 Comparator 0.31 V
S
Delay
PWRGD - +
Reset Dominant
x2.6 - CO3F + SS VFB COMP
- +
Figure 2. Block Diagram
PWRGDS
CSREF 0.6 V Start-Up Offset
CS1
- +
x 3.75
x2.6 - CO1F +
CS2 *+1.0 V/V
- +
x 3.75
x2.6 - CO2F +
x 3.75
CS3
- +
- +
VDRP
AVP Amp
Reset Dominant
VID0 VID1 VID2 VID3 VID4 DAC
- +
- + 3.3 V
9.0 V 8.0 V
GATE1
OC Filter
PWM2 Latch R
GATE2
PWM3 Comparator - + + - ILIM3 Comparator 0.31 V
PWM3 Latch R
VCC GATE3
NCP5306
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IBIAS 3.3 V + - 1.0 V + -
8
S
CO1
CO2 Oscillator Current Source IOSC Generator Pulseout1 Ramp1 Pulseout2 Ramp2 Pulseout3 Ramp3 GND ROSC
CO3
NCP5306
TYPICAL PERFORMANCE CHARACTERISTICS
900 800 VFB Bias Current (A) 20 30 40 50 ROSC Value (k) 60 70 700 Frequency (kHz) 600 500 400 300 200 100 10 0 10 20 30 40 50 ROSC Value (k) 60 70 80 20 15 10 5 25
Figure 3. Oscillator Frequency
20.0 19.5 19.0 18.5 ICC (mA) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 -15 5 25 45 65 TA (C) 85 105 FOSC (kHz) 410 409 408 407 406 405 404 403 402 401
Figure 4. VFB Bias Current vs. ROSC Value
0
20
40
60 TA (C)
80
100
120
Figure 5. ICC vs. Temperature
Figure 6. Oscillator Frequency vs. Temperature (ROSC = 32.4 kW)
700
0.20 VID = 1.1 V 0.15 VID = 1.5 V Error (%) 0.10 0.05 0.00 -0.05 Offset Voltage (mV) 80 100 120 VID = 1.3 V
650 600 550 500 450 400 350
0
20
40
60 TA (C)
300
0
20
40
60 TA (C)
80
100
120
Figure 7. DAC Output Error vs. Temperature
Figure 8. Current Sense Amplifier Channel Startup Offset Voltage vs. Temperature
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NCP5306
TYPICAL PERFORMANCE CHARACTERISTICS
4.0 3.8 Power Good Delay (ms) 3.6 3.4 Gain (V/V) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 -15 5 25 45 65 TA (C) 85 105 Current Sense Amp to PWM Comparator Current Sense Amp to VDRP Gain Current Sense Amp to OC Comparator 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0 20 40 60 TA (C) 80 100 120
Figure 9. Sense Amp Gains vs. Temperature
0.3 0.2 Offset Voltage (mV) 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0 20 40 60 TA (C) 80 100 120 VDRP Source Current (mA) 0.1
Figure 10. Power Good Delay vs. Temperature
-3.55 -3.60 -3.65 -3.70 -3.75 -3.80
0
20
40
60 TA (C)
80
100
120
Figure 11. VDRP to DAC Output Offset Voltage vs. Temperature
Figure 12. VDRP Source Current vs. Temperature
10.30 10.28 VFB Bias Current (A) VFB = 1.0 V 10.26 10.24 VFB = 1.9 V 10.22 10.20 10.18
0
20
40
60 TA (C)
80
100
120
Figure 13. VFB Bias Currents vs. Temperature (ROSC = 32.4 kW)
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NCP5306
APPLICATIONS INFORMATION
Overview
The NCP5306 DC/DC controller from ON Semiconductor was developed using the Enhanced V2 topology. Enhanced V2 combines the original V2 topology with peak current-mode control for fast transient response and current sensing capability. The addition of an internal PWM ramp and implementation of fast-feedback directly from Vcore has improved transient response and simplified design. The NCP5306 includes Power Good (PWRGD), providing a highly integrated solution to simplify design, minimize circuit board area, and reduce overall system cost. Two advantages of a multi-phase converter over a single-phase converter are current sharing and increased apparent output frequency. Current sharing allows the designer to use less inductance in each phase than would be required in a single-phase converter. The smaller inductor will produce larger ripple currents but the total per-phase power dissipation is reduced because the RMS current is lower. Transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. Increased apparent output frequency is desirable because the off- time and the ripple voltage of the multi-phase converter will be less than that of a single-phase converter.
Fixed Frequency Multi-Phase Control
In a multi-phase converter, multiple converters are connected in parallel and are switched on at different times. This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. The NCP5306 controller uses three-phase, fixed-frequency, Enhanced V2 architecture to measure and control currents in individual phases. Each phase is delayed 120 from the
x = 1, 2 or 3 SWNODE Lx RLx RSx CSREF VOUT (VCORE)
+
previous phase. Normally, GATEx transitions to a high voltage at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the PWM comparator and bring GATEx low. Once GATEx goes low, it will remain low until the beginning of the next oscillator cycle. While GATEx is high, the Enhanced V2 loop will respond to line and load variations. On the other hand, once GATEx is low, the loop cannot respond until the beginning of the next PWM cycle. Therefore, constant frequency Enhanced V2 will typically respond to disturbances within the off-time of the converter. The Enhanced V2 architecture measures and adjusts the output current in each phase. An additional input (CSx) for inductor current information has been added to the V2 loop for each phase as shown in Figure 14. The triangular inductor current is measured differentially across RS, amplified by CSA and summed with the channel startup offset, the internal ramp and the output voltage at the non-inverting input of the PWM comparator. The purpose of the internal ramp is to compensate for propagation delays in the NCP5306. This provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation and PWM duty cycles above 50% without external slope compensation. As the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the PWM comparator rises and terminates the PWM cycle. If the inductor starts a cycle with higher current, the PWM cycle will terminate earlier providing negative feedback. The NCP5306 provides a CSx input for each phase, but the CSREF and COMP inputs are common to all phases. Current sharing is accomplished by referencing all phases to the same CSREF and COMP pins, so that a phase with a larger current signal will turn off earlier than a phase with a smaller current signal.
CSx
+ CSA -
COx
Internal Ramp + - "Fast-Feedback" Connection + - PWM COMP To F/F Reset
VFB DAC Out COMP
+
- E.A. +
Channel Start-Up Offset
CAMP
Figure 14. Enhanced V2 Control Employing Resistive Current Sensing and Internal Ramp
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NCP5306
Enhanced V2 responds to disturbances in VCORE by employing both "slow" and "fast" voltage regulation. The internal error amplifier performs the slow regulation. Depending on the gain and frequency compensation set by the amplifier's external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in one or two PWM cycles. Fast voltage feedback is implemented by a direct connection from Vcore to the non-inverting pin of the PWM comparator via the summation with the inductor current, internal ramp and offset. A rapid increase in output current will produce a negative offset at Vcore and at the output of the summer. This will cause the PWM duty cycle to increase almost instantly. Fast feedback will typically adjust the PWM duty cycle in one PWM cycle. As shown in Figure 14, an internal ramp (nominally 115 mV at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the PWM comparator. This additional ramp compensates for propagation time delays from the current sense amplifier (CSA), the PWM comparator and the MOSFET gate drivers. As a result, the minimum ON time of the controller is reduced and lower duty-cycles may be achieved at higher frequencies. Also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the RCSxCCSx time constant of the feedback components from VCORE to the CSx pin. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. When the average output current is zero, the COMP pin will be:
VCOMP + VOUT @ 0 A ) Channel_Startup_Offset ) Int_Ramp ) GCSA @ Ext_Ramp 2
Or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as:
DV + RS @ GCSA @ DIOUT
The single-phase power stage output impedance is:
Single Stage Impedance + DVOUT DIOUT + RS @ GCSA
The total output impedance will be the single stage impedance divided by 3. The output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the COMP pin. The peak output current can be calculated from:
IOUT,PEAK + (VCOMP * VOUT * Offset) (RS @ GCSA)
Int_Ramp is the "partial" internal ramp value at the corresponding duty cycle, Ext_Ramp is the peak-to-peak external steady-state ramp at 0 A, GCSA is the current sense amplifier gain (nominally 2.6 V/V) and the channel startup offset is typically 0.60 V. The magnitude of the Ext_Ramp can be calculated from:
Ext_Ramp + D @ (VIN * VOUT) (RCSx @ CCSx @ fSW)
Figure 15 shows the step response of the COMP pin at a fixed level. Before T1, the converter is in normal steady-state operation. The inductor current provides a portion of the PWM ramp through the current sense amplifier. The PWM cycle ends when the sum of the current ramp, the "partial" internal ramp voltage signal and offset exceed the level of the COMP pin. At T1, the output current increases and the output voltage sags. The next PWM cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the VFB pin and the cycle ends at T2. After T2, the output voltage remains lower than at light load and the average current signal level (CSx output) is raised so that the sum of the current and voltage signal is the same as with the original load. In a closed loop system, the COMP pin would move higher to restore the output voltage to the original level.
SWNODE
VFB (VOUT)
For example, if VOUT at 0 A is set to 1.700 V with AVP and the input voltage is 12.0 V, the duty cycle (D) will be 1.700/12.0 or 14.2%. Int_Ramp will be 115 mV/50% 14.2% = 33 mV. Realistic values for RCSx, CCSx and fSW are 10 k, 0.015 F and 650 kHz. Using these and the previously mentioned formula, Ext_Ramp will be 15.0 mV.
VCOMP + 1.700 V ) 0.60 V ) 33 mV ) 2.6 V V @ 15.0 mV 2 + 2.3 Vdc.
Internal Ramp CSA Out w/ Exaggerated Delays COMP-Offset CSA Out + Ramp + CSREF
If the COMP pin is held steady and the inductor current changes, there must also be a change in the output voltage.
T1
T2
Figure 15. Open Loop Operation
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NCP5306
SWNODE Lx CCSx RLx VOUT (VCORE) CSREF RCSx x = 1, 2 or 3 CSx + CSA - COx
Internal Ramp + - "Fast-Feedback" Connection + - PWM COMP To F/F Reset
+
VFB DAC Out COMP
+
- E.A. +
Channel Start-Up Offset
CAMP
Figure 16. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp Inductive Current Sensing
For lossless sensing, current can be sensed across the inductor as shown in Figure 16. In the diagram, L is the output inductance and RL is the inherent inductor resistance. To compensate the current sense signal, the values of RCSx and CCSx are chosen so that L/RL = RCSx CCSx. If this criteria is met, the current sense signal will be the same shape as the inductor current and the voltage signal at CSx will represent the instantaneous value of inductor current. Also, the circuit can be analyzed as if a sense resistor of value RL was used. When choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0.39% per C. The increase in winding resistance at higher temperatures should be considered when setting the OCSET threshold. If a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in Figure 14.
Current Sharing Accuracy
accuracy of the current sharing between phases. The worst case CSA input mismatch is 10 mV and will typically be within 4.0 mV. The difference in peak currents between phases will be the CSA input mismatch divided by the current sense resistance. If all current sense components are of equal resistance, a 3.0 mV mismatch with a 2.0 m sense resistance will produce a 1.5 A difference in current between phases.
External Ramp Size and Current Sensing
Printed circuit board (PCB) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. For accurate current sharing, the current sense inputs should sense the current at relatively the same point for each phase and the connection to the CSREF pin should be made so that no phase is favored. In some cases, especially with inductive sensing, resistance of the PCB can be useful for increasing the current sense resistance. The total current sense resistance used for calculations must include any PCB trace resistance between the CSx input and the CSREF input that carries inductor current. Current Sense Amplifier (CSA) input mismatch and the value of the current sense component will determine the
The internal ramp allows flexibility in setting the current sense time constant. Typically, the current sense RCSx CCSx time constant should be equal to or slightly slower than the inductor's time constant. If RC is chosen to be smaller (faster) than L/RL, the AC or transient portion of the current sensing signal will be scaled larger than the DC portion. This will provide a larger steady-state ramp, but circuit performance will be affected and must be evaluated carefully. The current signal will overshoot during transients and settle at the rate determined by RCSx CCSx. It will eventually settle to the correct DC level, but the error will decay with the time constant of RCSx CCSx. If this error is excessive, it will affect transient response, adaptive positioning and current limit. During a positive current transient, the COMP pin will be required to undershoot in response to the current signal in order to maintain the output voltage. Similarly, the VDRP signal will overshoot which will produce too much transient droop in the output voltage. The single-phase pulse-by-pulse overcurrent protection will trip earlier than it would if compensated correctly and hiccup-mode current limit will have a lower threshold for fast rising step loads than for slowly rising output currents. The waveforms in Figure 17 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of L = 500 nH, RL = 1.6 m, RCSx = 20 k and CCSx = .01 F. In this case, ideal current signal compensation would require RCSx to be 31 k.
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Due to the faster than ideal RC time constant, there is an overshoot of 50% and the overshoot decays with a 200 s time constant. With this compensation, the OCSET pin threshold must be set more than 50% above the full load current to avoid triggering current limit during a large output load step.
Transient Response and Adaptive Voltage Positioning
For applications with fast transient currents, the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. Adaptive voltage positioning can reduce peak-peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. Similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. For low current applications, a droop resistor can provide fast, accurate adaptive positioning. However, at high currents, the loss in a droop resistor becomes excessive. For example, a 50 A converter with a 1 m resistor would provide a 50 mV change in output voltage between no load and full load and would dissipate 2.5 W. Lossless adaptive voltage positioning (AVP) is an alternative to using a droop resistor, but it must respond to changes in load current. Figure 18 shows how AVP works. The waveform labeled "normal" shows a converter without AVP. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) AVP, the peak-to-peak excursions are cut in half. In the slow AVP waveform, the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. The controller can be configured to adjust the output voltage based on the output current of the converter. (Refer to the application diagram in Figure 1). To set the no-load positioning, a resistor is placed between the output voltage and VFB pin. The VFB bias current will develop a voltage across the resistor to adjust the no-load output voltage. The VFB bias current is dependent on the value of ROSC as shown in the datasheets. During no-load conditions, the VDRP pin is at the same voltage as the VFB pin, so none of the VFB bias current flows through the VDRP resistor. When output current increases, the VDRP pin voltage increases proportionally. Current set by the VDRP resistor offsets the VFB bias current, causing the output voltage to decrease. The response during the first few microseconds of a load transient is controlled primarily by power stage output impedance, and by the ESR and ESL of the output filter. The transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. If the ramp size is too large or the error amp too slow, there will be a long transition to the final voltage after a transient. This will be most apparent with low capacitance output filters.
Figure 17. Inductive Sensing Waveform During a Load Step with Fast RC Time Constant (50 s/div)
Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits
Figure 18. Adaptive Voltage Positioning Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of the normal operation of the Enhanced V2 control topology with synchronous rectifiers. The control loop responds to an overvoltage condition within 40 ns, causing the GATEx output to shut off. The (external) MOSFET driver should react normally to turn off the top MOSFET and turn on the bottom MOSFET. This results in a "crowbar" action to clamp the output voltage and prevent damage to the load. The regulator will remain in this state until the overvoltage condition ends or the input voltage is pulled low.
Power Good
According to the latest specifications, the Power Good (PWRGD) signal must be asserted when the output voltage is within a window defined by the VID code, as shown in Figure 19. The PWRGDS pin is provided to allow the PWRGD comparators to accurately sense the output voltage. The effect of the PWRGD lower threshold can be modified using a resistor divider from the output to PWRGDS to ground, as shown in Figure 20.
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PWRGD
HIGH
LOW
-5%
+5%
VLOWER
Figure 19. PWRGD Assertion Window
Since the internally-set thresholds for PWRGDS are VID/2 for the lower threshold and a fixed 1.975V for the upper threshold, a simple equation can be provided to assist the designer in selecting a resistor divider to provide the desired PWRGD performance.
V R ) R2 VLOWER + VID @ 1 2 R1 VUPPER + 1.975 V
The logic circuitry inside the chip sets PWRGD low only after a delay period has been passed. A "power bad" event does not cause PWRGD to go low unless it is sustained through the delay time of 500 s. If the anomaly disappears before the end of the delay, the PWRGD output will never be set low. In order to use the PWRGD pin as specified, the user is advised to connect external resistors as necessary to limit the current into this pin to 4 mA or less.
Undervoltage Lockout
The NCP5306 includes an undervoltage lockout circuit. This circuit keeps the IC's output drivers low until VCC applied to the IC reaches 9 V. The GATE outputs are disabled when VCC drops below 8 V.
Soft Start and Hiccup Mode
At initial power-up, both SS and COMP voltages are zero. The total SS capacitance will begin to charge with a current of 160 A. The error amplifier directly charges the COMP capacitance. An internal clamp ensures that the COMP pin voltage will always be less than the voltage at the SS pin, ensuring proper start-up behavior. All GATE outputs are held low until the COMP voltage reaches 0.6 V. Once this threshold is reached, the GATE outputs are released to operate normally. In current limit, the internal fault latch will initiate a 5 A discharge current on the SS pin, and the internal clamp will discharge the capacitor connected to the COMP pin at a similar rate. This performance will result in GATE pulses being generated until the overcurrent condition reoccurs and the discharge/soft start cycle begins anew.
EEE EEE CCC CCC CCC CCC
-5% +5%
EEE EEE CCC CCC CCC CCC
PWRGD low
PWRGD high
PWRGD low
VOUT R1 PWRGDS
VOUT
R2
1.975 V
Figure 20. Adjusting the PWRGD Threshold Current Limit
Two levels of over-current protection are provided. First, if the voltage on the Current Sense pins (CSx) exceeds CSREF by more than a fixed threshold (Single Pulse Current Limit), the PWM comparator is turned off. This provides fast peak current protection for individual phases. Second, the individual phase currents are summed and low-pass filtered to compare an averaged current signal to a user adjustable voltage on the OCSET pin. If the OCSET voltage is exceeded, the fault latch trips and the Soft Start capacitor discharges until the Soft Start pin reaches 0.3 V. Then Soft Start begins. The converter will continue to operate in a low average current hiccup-mode until the fault condition is corrected.
Fault Protection Logic
The NCP5306 includes fault protection circuitry to prevent harmful modes of operation from occurring. The fault logic is described in Table 1.
Gate Outputs
The NCP5306 is designed to operate with external gate drivers. Accordingly, the gate outputs are capable of driving a 100 pF load with typical rise and fall times of 5 ns.
Digital to Analog Converter (DAC)
The output voltage of the NCP5306 is set by means of a 5-bit, 1% DAC. The DAC pins are internally pulled up to a 3.3 V rail through a blocking diode and a set of 50 k resistors. The blocking diode allows external pull up to a bias voltage greater than 3.3 V and less than 13 V. The output of the DAC is described in the Electrical Characteristics section of the data sheet. These outputs are consistent with the latest VRM and processor specifications. The DAC output is equal to the VID code specification. In order to produce a workable power supply using the NCP5306, the designer is expected to use AVP as described earlier to position the output voltage below the DAC output, resulting in an output voltage somewhere in the middle of the acceptable range.
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Table 1. Fault Protection Logic
Fault Modes Undervoltage Lockout VID-11111 Phase Over Current (0.31 V Limit) Stop Switching Yes Yes No SS Pin Characteristics -5.0 A -5.0 A Not Affected Reset Method SS < 0.3 V Change VID Code Automatic
The latest VRM and processor specifications require a power supply to turn its output off in the event of a 11111 VID code. When the DAC sees such a code, the GATE pins stop switching and go low. This condition is described in Table 1. Design Procedure
1. Output Capacitor Selection
The output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. Typically, microprocessor applications require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. The bulk capacitors provide "hold up" during transient loading. The low impedance capacitors reduce steady-state ripple and bypass the bulk capacitance when the output current changes very quickly. The microprocessor manufacturers usually specify a minimum number of ceramic capacitors. The designer must determine the number of bulk capacitors. Choose the number of bulk output capacitors to meet the peak transient requirements. The formula below can be used to provide a starting point for the minimum number of bulk capacitors (NOUT,MIN):
DI NOUT,MIN + ESR per capacitor @ O,MAX DVO,MAX
(1)
magnetic saturation, temperature, physical size and cost (usually the primary concern). In general, the output inductance value should be electrically and physically as small as possible to provide the best transient response at minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, too low an inductance value will result in very large ripple currents in the power components (MOSFETs, capacitors, etc.) resulting in increased dissipation and lower converter efficiency. Increased ripple currents force the designer to use higher rated MOSFETs, oversize the thermal solution, and use more, higher rated input and output capacitors, adversely affecting converter cost. One method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. Lower ripple currents will result in less core and MOSFET losses and higher converter efficiency. Equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current () per phase. The inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. Conversely, higher inductor values will result in less than the selected maximum ripple current.
(VIN * VOUT) @ D LoMIN + (a @ IO,MAX @ fSW)
(3)
In reality, both the ESR and ESL of the bulk capacitors determine the voltage change during a load transient according to:
DVO,MAX + (DIO,MAX Dt) @ ESL ) DIO,MAX @ ESR (2)
Unfortunately, capacitor manufacturers do not specify the ESL of their components and the inductance added by the PCB traces is highly dependent on the layout and routing. Therefore, it is necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors.
2. Output Inductor Selection
The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady-state and transient performance of the converter. When selecting an inductor, the designer must consider factors such as DC current, peak current, output voltage ripple, core material,
is the ripple current as a percentage of the maximum output current per phase ( = 0.15 for 15%, = 0.25 for 25%, etc.). If the minimum inductor value is used, the inductor current will swing % about its value at the center. Therefore, for a three-phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + ) IO,MAX/3. The maximum inductor value is limited by the transient response of the converter. If the converter is to have a fast transient response, the inductor should be made as small as possible. If the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required and the converter cost will be increased. For a given inductor value, it is useful to determine the times required to increase or decrease the current. For increasing current:
DtINC + Lo @ DIO (VIN * VOUT)
(3.1)
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For decreasing current:
DtDEC + Lo @ DIO (VOUT)
(3.2)
ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX 3 * DILo 2
(9)
For typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. Thus, it may be more difficult for the converter to stay within the regulation limits when the load is removed than when it is applied and excessive overshoot may result. The output voltage ripple can be calculated using the output inductor value derived in this Section (LoMIN), the number of output capacitors (NOUT,MIN) and the per capacitor ESR determined in the previous Section:
VOUT,P-P + (ESR per cap NOUT,MIN) @ (VIN * #Phases @ VOUT) @ D (LoMIN @ fSW)
(4)
ILo is the peak-to-peak ripple current in the output inductor of value Lo:
DILo + (VIN * VOUT) @ D (Lo @ fSW)
(10)
For the three-phase converter, the input capacitor(s) RMS current is then:
ICIN,RMS + [3D @ (IC,MIN2 ) IC,MIN @ DILO ) DILO2 3) ) IIN,AVG2 @ (1 * 3D)]1 2
(11)
Select the number of input capacitors (NIN) to provide the RMS input current (ICIN,RMS) based on the RMS ripple current rating per capacitor (IRMS,RATED):
NIN + ICIN,RMS IRMS,RATED
(12)
This formula assumes steady-state conditions with no more than one phase on at any time. The second term in Equation 4 is the total ripple current seen by the output capacitors. The total output ripple current is the "time summation" of the three individual phase currents that are 120 degrees out-of-phase. As the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. Therefore, the total output ripple current and voltage are reduced in a multi-phase converter.
3. Input Capacitor Selection
The choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. The designer must choose capacitors that will support the worst case input voltage with adequate margin. To calculate the number of input capacitors, one must first determine the total RMS input ripple current. To this end, begin by calculating the average input current to the converter:
IIN,AVG + IO,MAX @ D h
(5)
For a three-phase converter with perfect efficiency ( = 1), the worst case input ripple-current will occur when the converter is operating at a 16.7% duty cycle. At this operating point, the parallel combination of input capacitors must support an RMS ripple current equal to 16.7% of the converter's DC output current. At other duty cycles, the ripple-current will be less. For example, at a duty cycle of either 3% or 30%, the three-phase input ripple-current will be approximately 10% of the converter's DC output current. In general, capacitor manufacturers require derating to the specified ripple-current based on the ambient temperature. More capacitors will be required because of the current derating. The designer should know the ESR of the input capacitors. The input capacitor power loss can be calculated from:
PCIN + ICIN,RMS2 @ ESR_per_capacitor NIN (13)
where: D is the duty cycle of the converter, D = VOUT/VIN; is the specified minimum efficiency; IO,MAX is the maximum converter output current. The input capacitors will discharge when the control FET is ON and charge when the control FET is OFF as shown in Figure 21. The following equations will determine the maximum and minimum currents delivered by the input capacitors:
IC,MAX + ILo,MAX h * IIN,AVG IC,MIN + ILo,MIN h * IIN,AVG
(6) (7)
Low ESR capacitors are recommended to minimize losses and reduce capacitor heating. The life of an electrolytic capacitor is reduced 50% for every 10C rise in the capacitor's temperature.
IC,MAX IC,MIN 0A IC,IN = IC,MAX - IC,MIN = ILO
tON FET Off, Caps Charging
T/3
-IIN,AVG
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAX 3 ) DILo 2
(8)
FET On, Caps Discharging
Figure 21. Input Capacitor Current for a Four-Phase Converter
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MAX dI/dt occurs in first few PWM cycles. ILi Li TBD NCi x Ci + Vi - 12 V ESRCi/NCi Vi(t = 0) = 12 V Q1 SWNODE ILo Lo
+ VCi +
VOUT
Vo(t = 0) = 1.745 V
NCo x Co 14 u(t)
Q2
ESRCo/NCo
Figure 22. Calculating the Input Inductance 4. Input Inductor Selection
The use of an inductor between the input capacitors and the power source will accomplish two objectives. First, it will isolate the voltage source and the system from the noise generated in the switching supply. Second, it will limit the inrush current into the input capacitors at power up. Large inrush currents reduce the expected life of the input capacitors. The inductor's limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case input current slew rate will occur during the first few PWM cycles immediately after a step-load change is applied as shown in Figure 22. When the load is applied, the output voltage is pulled down very quickly. Current through the output inductors will not change instantaneously, so the initial transient load current must be conducted by the output capacitors. The output voltage will step downward depending on the magnitude of the output current (IO,MAX), the per capacitor ESR of the output capacitors (ESROUT) and the number of the output capacitors (NOUT) as shown in Figure 22. Assuming the load current is shared equally between the three phases, the output voltage at full transient load will be:
VOUT,FULL-LOAD +
(14)
The differential voltage across the output inductor will cause its current to increase linearly with time. The slew rate of this current can be calculated from:
dILo dt + DVLo Lo
(16)
Current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. The amount of voltage drop across the input capacitors (VCi) is determined by the number of input capacitors (NIN), their per capacitor ESR (ESRIN) and the current in the output inductor according to:
DVCi + ESRIN NIN @ dILo dt @ tON + ESRIN NIN @ dILo dt @ D fSW
(17)
Before the load is applied, the voltage across the input inductor (VLi) is very small and the input capacitors charge to the input voltage VIN. After the load is applied, the voltage drop across the input capacitors, VCi, appears across the input inductor as well. Knowing this, the minimum value of the input inductor can be calculated from:
LiMIN + VLi + DVCi dIIN dtMAX dIIN dtMAX
(18)
VOUT,NO-LOAD * (IO,MAX 3) @ ESROUT NOUT
When the control MOSFET (Q1 in Figure 22) turns ON, the input voltage will be applied to the opposite terminal of the output inductor (the SWNODE). At that instant, the voltage across the output inductor can be calculated as:
DVLo + VIN * VOUT,FULL-LOAD + VIN * VOUT,NO-LOAD ) (IO,MAX 3) @ ESROUT NOUT
(15)
dIIN/dtMAX is the maximum allowable input current slew rate. The input inductance value calculated from Equation 18 is relatively conservative. It assumes the supply voltage is very "stiff" and does not account for any parasitic elements that will limit dI/dt such as stray inductance. Also, the ESR values of the capacitors specified by the manufacturer's data sheets are worst case high limits. In reality, input voltage "sag," lower capacitor ESRs and stray inductance will help reduce the slew rate of the input current.
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As with the output inductor, the input inductor must support the maximum current without saturating the inductor. Also, for an inexpensive iron powder core, such as the -26 or -52 from Micrometals, the inductance "swing" with DC bias must be taken into account and inductance will decrease as the DC input current increases. At the maximum input current, the inductance must not decrease below the minimum value or the dI/dt will be higher than expected.
5. MOSFET & Heatsink Selection
VGS_TH
ID
VGATE
Power dissipation, package size and thermal requirements drive MOSFET selection. To adequately size the heat sink, the design must first predict the MOSFET power dissipation. Once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or upper MOSFET will display both switching and conduction losses. The synchronous or lower MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non-overlap time of the gate drivers. For the upper or control MOSFET, the power dissipation can be approximated from:
PD,CONTROL + (IRMS,CNTL2 @ RDS(on)) ) (ILo,MAX @ Qswitch Ig @ VIN @ fSW) ) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
(19)
QGS1
QGS2
QGD
VDRAIN
Figure 23. MOSFET Switching Characteristics
D is the duty cycle of the converter:
D + VOUT VIN
(23)
ILo is the peak-to-peak ripple current in the output inductor of value Lo:
DILo + (VIN * VOUT) @ D (Lo @ fSW)
(24)
RDS(on) is the ON resistance of the MOSFET at the applied gate drive voltage. Qswitch is the post gate threshold portion of the gate-to-source charge plus the gate-to-drain charge. This may be specified in the data sheet or approximated from the gate-charge curve as shown in the Figure 23.
Qswitch + Qgs2 ) Qgd
(25)
The first term represents the conduction or IR losses when the MOSFET is ON while the second term represents the switching losses. The third term is the loss associated with the control and synchronous MOSFET output charge when the control MOSFET turns ON. The output losses are caused by both the control and synchronous MOSFET but are dissipated only in the control FET. The fourth term is the loss due to the reverse recovery time of the body diode in the synchronous MOSFET. The first two terms are usually adequate to predict the majority of the losses. IRMS,CNTL is the RMS value of the trapezoidal current in the control MOSFET:
IRMS,CNTL + D
(20)
Ig is the output current from the gate driver IC. VIN is the input voltage to the converter. fsw is the switching frequency of the converter. QRR is the reverse recovery charge of the lower MOSFET. Qoss is the sum of all the MOSFET output charge specified in the data sheet. For the lower or synchronous MOSFET, the power dissipation can be approximated from:
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on)) ) (Vfdiode @ IO,MAX 3 @ t_nonoverlap @ fSW)
(26)
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAX 3 ) DILo 2
(21)
The first term represents the conduction or IR losses when the MOSFET is ON and the second term represents the diode losses that occur during the gate non-overlap time. All terms were defined in the previous discussion for the control MOSFET with the exception of:
IRMS,SYNCH + 1 * D
(27)
ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX 3 * DILo 2
(22)
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
IO,MAX is the maximum converter output current.
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where: Vfdiode is the forward voltage of the MOSFET's intrinsic diode at the converter output current. t_nonoverlap is the non-overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the data sheet for the control IC. When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature.
qT t (TJ * TA) PD
(28)
As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading and component variations (i.e., worst case MOSFET RDS(on)). Also, the inductors and capacitors share the MOSFET's heatsinks and will add heat and raise the temperature of the circuit board and MOSFET. For any new design, it is advisable to have as much heatsink area as possible. All too often, new designs are found to be too hot and require re-design to add heatsinking.
6. Adaptive Voltage Positioning
where: T is the total thermal impedance (JC + SA); JC is the junction-to-case thermal impedance of the MOSFET; SA is the sink-to-ambient thermal impedance of the heatsink assuming direct mounting of the MOSFET (no thermal "pad" is used); TJ is the specified maximum allowed junction temperature; TA is the worst case ambient operating temperature. For TO-220 and TO-263 packages, standard FR-4 copper clad circuit boards will have approximate thermal resistances (SA) as shown below:
Pad Size (in2/mm2) 0.50/323 0.75/484 1.00/645 1.50/968 Single-Sided 1 oz. Copper 60-65C/W 55-60C/W 50-55C/W 45-50C/W
There are two resistors that determine the Adaptive Voltage Positioning: RFB and RDRP. RFB establishes the no-load "high" voltage position and RDRP determines the full-load "droop" voltage. Resistor RFB is connected between VCORE and the VFB pin of the controller. At no load, this resistor will conduct the internal bias current of the VFB pin and develop a voltage drop from VFB to the VCORE pin. Because the error amplifier regulates VFB to the DAC setting, the output voltage, VCORE, will be lower by the amount IBIASVFB RFB. This condition is shown in Figure 24. To calculate RFB, the designer must specify the no-load voltage decrease below the VID setting (VNO-LOAD) and determine the VFB bias current. Usually, the no-load voltage decrease is specified in the design guide for the processor that is available from the manufacturer. The VFB bias current is determined by the value of the resistor from ROSC to ground (see Figure 4 in the data sheet for a graph of IBIASVFB versus ROSC). The value of RFB can then be calculated:
RFB + DVNO-LOAD IBIASVFB
(29)
RCS1 L1 0A
CS1
+- - + + - GVDRP COMP VID Setting IBIAS VFB RFB VFB = VID VCORE
CCS1
Error Amp RDRP
RCSx Lx 0A
CSx
CCSx CSREF
+ - GVDRP
VDRP = VID
IDRP = 0
IFB = IBIASVFB
VCORE = VID + IBIASVFB w RFB
Figure 24. AVP Circuitry at No-Load
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RCS1 L1 IMAX/3 CS1 +- - + + - GVDRP COMP VID Setting IBIAS VFB RFB VCORE
CCS1
Error Amp RDRP
RCSx Lx IMAX/3
CSx
+ - GVDRP
VDRP = VID + VFB = VID IMAX * RL * GVDRP IDRP IFB
CCSx CSREF
IDRP = IMAX * RL * GVDRP/RDRP IFBK = IDRP - IBIASVFB
VCORE = VID - (IDRP - IBIASVFB) w RFB = VID - IMAX w RL w GVDRP w RFB/RDRP + IBIASVFB w RFB
Figure 25. AVP Circuitry at Full-Load
Figure 26. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Long (Slow): VDRP and VOUT Respond Too Slowly.
Resistor RDRP is connected between the VDRP and the VFB pins. At no-load, the VDRP and the VFB pins will both be at the DAC voltage. This resistor will conduct zero current. However, at full-load, the voltage at the VDRP pin will increase proportional to the output inductor's current while VFB will still be regulated to the DAC voltage. Current will be conducted from VDRP to VFB by RDRP. This current will be large enough to supply the VFB bias current and cause a voltage drop from VFB to VCORE across RFB. The converter's output voltage will be reduced. This condition is shown in Figure 25. To determine the value of RDRP, the designer must specify the full-load voltage reduction from the VID (DAC) setting (VOUT,FULL-LOAD) and predict the voltage increase at the VDRP pin at full-load. Usually, the full-load voltage reduction is specified in the design guide for the processor that is available from the manufacturer. To predict the voltage increase at the VDRP pin at full-load (VDRP), the designer must consider the output inductor's resistance (RL), the PCB trace resistance between the current sense points (RPCB) and the controller IC's gain from the current sense to the VDRP pin (GVDRP):
DVDRP + IO,MAX @ (RL ) RPCB) @ GVDRP
(30)
The value of RDRP can then be calculated:
DVDRP RDRP + (IBIASVFB ) DVOUT,FULL-LOAD RFB)
(31)
VOUT,FULL-LOAD is the full-load voltage reduction from the VID (DAC) setting. VOUT,FULL-LOAD is not the voltage change from the no-load AVP setting.
Figure 27. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Short (Fast): VDRP and VOUT Both Overshoot. 7. Current Sensing
For inductive current sensing, choose the current sense network (RCSx, CCSx, x = 1, 2 or 3) to satisfy
RCSx @ CCSx + Lo (RL ) RPCB)
(32)
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Figure 28. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Optimal: VDRP and VOUT Respond to the Load Current Quickly Without Overshooting.
Figure 29. The Value of CAMP Is Too High and the Loop Gain/Bandwidth Too Low. COMP Slews Too Slowly Which Results in Overshoot in VOUT.
For resistive current sensing, choose the current sense network (RCSx, CCSx, x = 1, 2 or 3) to satisfy
RCSx @ CCSx + Lo (Rsense)
(33)
operating at full steady-state load, the peak-to-peak voltage ripple (VPP) on the COMP pin should be less than 20 mVPP as shown in Figure 31. Less than 10 mVPP is ideal. Excessive ripple on the COMP pin will contribute to jitter.
9. Current Limit Setting
This will provide an adequate starting point for RCSx and CCSx. After the converter is constructed, the value of RCSx (and/or CCSx) should be fine-tuned in the lab by observing the VDRP signal during a step change in load current (Figures 27 and 28). Tune the RCSx CCSx network to provide a "square-wave" at the VDRP output pin with maximum rise time and minimal overshoot as shown in Figure 28.
8. Error Amplifier Tuning
After the steady-state (static) AVP has been set and the current sense network has been optimized, the Error Amplifier must be tuned. The gain of the Error Amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the Error Amplifier's feedback capacitor (CAMP in Figures 14 and 16). The bandwidth of the control loop will vary directly with the gain of the error amplifier. If CAMP is too large, the loop gain/bandwidth will be low, the COMP pin will slew too slowly and the output voltage will overshoot as shown in Figure 29. On the other hand, if CAMP is too small, the loop gain/bandwidth will be high, the COMP pin will slew very quickly and overshoot will occur. Integrator "wind up" is the cause of the overshoot. In this case, the output voltage will transition more slowly because COMP spikes upward as shown in Figure 30. Too much loop gain/bandwidth increases the risk of instability. In general, one should use the lowest loop gain/bandwidth possible to achieve acceptable transient response. This will insure good stability. If CAMP is optimal, the COMP pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in Figure 32. After the control loop is tuned to provide an acceptable transient response, the steady-state voltage ripple on the COMP pin should be examined. When the converter is
When the output of the current sense amplifier (COx in the block diagram) exceeds the voltage on the OCSET pin, the part will enter hiccup mode. For inductive sensing, the OCSET pin voltage should be set based on the inductor's maximum resistance (RLMAX). The design must consider the inductor's resistance increase due to current heating and ambient temperature rise. Also, depending on the current sense points, the circuit board may add additional resistance. In general, the temperature coefficient of copper is +0.39% per _C. If using a current sense resistor (RSENSE), the ILIM pin voltage should be set based on the maximum value of the sense resistor. To set the level of the OCSET pin:
Figure 30. The Value of CAMP Is Too Low and the Loop Gain/Bandwidth Too High. COMP Moves Too Quickly, Which Is Evident from the Small Spike in Its Voltage When the Load Is Applied or Removed. The Output Voltage Transitions More Slowly Because of the COMP Spike.
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NCP5306
Figure 31. At Full-Load the Peak-to-Peak Voltage Ripple on the COMP Pin Should Be Less than 20 mV for a Well-Tuned/Stable Controller. Higher COMP Voltage Ripple Will Contribute to Output Voltage Jitter. OCSET + (IOUT,LIM ) DILo 2) @ R @ GILIM
(34)
Figure 32. The Value of CAMP Is Optimal. COMP Slews Quickly Without Spiking or Ringing. VOUT Does Not Overshoot and Monotonically Settles to Its Final Value.
where: IOUT,LIM is the current limit threshold of the converter; ILo/2 is half the inductor ripple current; R is either (RLMAX + RPCB) or RSENSE; GILIM (nominally 3.75 V/V) is the current sense to ILIM gain. For the overcurrent protection to work properly, the current sense time constant (RC) should be slightly larger than the RL time constant. If the RC time constant is too fast, a step load change will cause the sensed current waveform to appear larger than the actual inductor current and will trip the current limit at a lower level than expected.
10. PWM Comparator Input Voltage
VCOx,MAX + [VCSx * VCSREF] @ GCSA,MAX + (IO,MAX 3 ) DILo 2) @ RMAX @ GCSA,MAX RMAX + RSENSE or (RL,MAX ) RPCB,MAX) 11. Soft Start Time
The Soft Start time (TSS) can be calculated from:
TSS + CSS @ DV ISS + CSS @ VCOMP * Channel_Startup_Offset 160 mA
(36)
where:
VCOMP + VOUT @ 0 A ) Channel_Startup_Offset ) Int_Ramp ) GCSA @ Ext_Ramp 2 + 2.3 Vdc (from page 12)
The voltage at the positive input terminal of the PWM comparator (see Figure 14 or 16) is limited by the internal voltage supply of the controller, the size of the internal and external ramps and the magnitude of the channel startup offset voltage. To prevent the PWM comparator from saturating, the differential input voltage from CSREF to CSn (n = 1, 2 or 3) must satisfy the following equation:
VCSREF,MAX ) VCOx,MAX ) 600 mV ) 230 mV v 2.90 V
(35)
If CSS = 0.1 F, then the Soft Start time will be:
TSS + 0.1 mF @ 1.7 Vdc + 1.06 ms 160 mA
(37)
where:
VCSREF,MAX + Max VID Setting w AVP @ Full Load
The Channel_Startup_Offset is subtracted from VCOMP as the output does not begin to rise until VCOMP exceeds this voltage. As the internal and external ramp values are small, the Soft Start time may be approximated by:
TSS + CSS @ VOUT @ 0 A ISS
(38)
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NCP5306
PACKAGE DIMENSIONS
SO-24L DW SUFFIX CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE 22X X 45 _
G
K
M
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5306/D

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