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ALC655
SIX CHANNEL AC'97 2.3 AUDIO CODEC ALC655
0. Revision History ..............................................................2 1. Features............................................................................3 2. General Description ........................................................3 3. Block Diagram.................................................................4 4. Pin Assignments ..............................................................5 5. Pin Description ................................................................6 5.1 Digital I/O Pins ..........................................................6 5.2 Analog I/O Pins..........................................................6 5.3 Filter/Reference..........................................................7 5.4 Power/Ground ............................................................7 6. Registers...........................................................................8 6.1 Mixer Registers ..........................................................8 6.1.1 MX00 Reset........................................................9 6.1.2 MX02 (Front) Master Volume............................9 6.1.3 MX06 MONO_OUT Volume.............................9 6.1.4 MX0A PC BEEP Volume ..................................9 6.1.5 MX0C PHONE Volume ...................................10 6.1.6 MX0E MIC Volume .........................................10 6.1.7 MX10 LINE_IN Volume..................................10 6.1.8 MX12 CD Volume ...........................................11 6.1.9 MX16 AUX Volume ........................................11 6.1.10 MX18 PCM_OUT Volume ............................11 6.1.11 MX1A Record Select......................................12 6.1.12 MX1C Record Gain........................................12 6.1.13 MX20 General Purpose Register ....................12 6.1.14 MX24 Audio interrupt and Paging .................13 6.1.15 MX26 Powerdown Control/Status..................14 6.1.16 MX28 Extended Audio ID..............................15 6.1.17 MX2A Extended Audio Status and Control Register........15 6.1.18 MX2C PCM Front/Center Output Sample Rate....16 6.1.19 MX2E PCM Surround Output Sample Rate......16 6.1.20 MX30 PCM LFE Output Sample Rate ...........16 6.1.21 MX32 PCM Input Sample Rate......................16 6.1.22 MX36 LFE/Center Master Volume ................16 6.1.23 MX38 Surround Master Volume ....................17 6.1.24 MX3A S/PDIF Output Channel Status and Control....17 6.2 Vendor Defined Registers (Page ID-00h) ................18 6.2.1 MX60 S/PDIF Input Channel Status [15:0]......18 6.2.2 MX62 S/PDIF Input Channel Status [29:15]....18 6.2.3 MX64 Surround DAC Volume.........................19 6.2.4 MX66 Center/LFE DAC Volume.....................19 6.2.5 MX6A Data Flow Control ............................... 19 6.3 Discovery Descriptor (Page ID-01h) ....................... 20 6.3.1 MX62 PCI Sub System ID............................... 20 6.3.2 MX64 PCI Sub Vendor ID............................... 20 6.3.3 MX66 Sense Function Select ........................... 20 6.3.4 MX68 Sense Function Information.................. 21 6.3.5 MX6A Sense Detail ......................................... 21 6.4 Extension Registers ................................................. 21 6.4.1 MX78 GPIO(JD) Interrupt Control & Status ... 21 6.4.2 MX7A Miscellaneous Control ................................ 22 6.4.4 MX7C VENDOR ID1..................................... 23 6.4.5 MX7E VENDOR ID2 ..................................... 23 7. Electrical Characteristics............................................. 24 7.1.1 Absolute Maximum Ratings ............................ 24 7.1.2 Threshold Hold Voltage................................... 24 7.1.3 Digital Filter Characteristics ............................ 24 7.1.4 S/PDIF output Characteristics.......................... 25 7.2 AC Timing Characteristics ...................................... 25 7.2.1 Cold Reset ........................................................ 25 7.2.2 Warm Reset...................................................... 25 7.2.3 AC-Link Clocks ............................................... 26 7.2.4 Data Output and Input Timing ......................... 26 7.2.5 Signal Rise and Fall Timing............................. 27 7.2.6 AC-Link Low Power Mode Timing................. 27 7.2.7 ATE Test Mode................................................ 28 7.2.8 AC-Link IO Pin Capacitance and Loading ...... 28 7.2.9 SPDIF Output................................................... 28 8. Analog Performance Characteristics .......................... 29 9. Design Suggestions........................................................ 31 9.1 Clocking .................................................................. 31 9.2 AC-Link................................................................... 32 9.3 Reset ........................................................................ 33 9.4 CD Input .................................................................. 33 9.5 Odd Addressed Register Access .............................. 33 9.6 Power-down Mode .................................................. 33 9.7 Test Mode ................................................................ 33 9.7.1 ATE In Circuit Test Mode ............................... 33 9.7.2 Vendor Specific Test Mode ............................. 33 9.8 POWER OFF CD Function ..................................... 34 10. Application Circuits ................................................... 35 11. Mechanical Dimensions.............................................. 39
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0. Revision History
Version 0.30: Preliminary version Version 0.40: 1.Update application circuit for automatic jack sensing function. 2.Add a FRONT-MIC2 for stereo microphone input for front panel application. (Ver.D or later) Version 1. 0: Just change Version from 0.4 to 1.0
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1. Features
Meets performance requirements for audio on PC99/2001 systems Meets Microsoft WHQL/WLP 2.0 audio requirements 16-bit Stereo full-duplex CODEC with 48KHz sampling rate Compliant with AC'97 2.3 specifications -Front-Out, Surround-Out, MIC-In and LINEIn Jack Sensing -14.318MHz- 24.576MHz PLL to save crystal -12.288MHz BITCLK input can be consumed -Integrated PCBEEP generator to save buzzer -Interrupt capability Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX High quality differential CD input Two analog line-level mono input: PCBEEP, PHONE-IN Two software selectable MIC inputs A dedicated Front-MIC input for front panel applications (software selectable) Boost preamplifier for MIC input LINE Input shared with surround output; MIC input shared with Center and LFE output Both Front-out and Surround-Out built-in 50mW/20 amplifier External Amplifier Power Down (EAPD) capability Power management and enhanced power saving features Stereo MIC record for AEC/BF application Supports Power Off CD function Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback Support 48KHz of S/PDIF output is compliant with AC'97 rev2.3 specification Support 32K/44.1K/48KHz of S/PDIF input Power support: Digital: 3.3V; Analog: 3.3V/5V Standard 48-Pin LQFP Package EAXTM 1.0&2.0 compatible Direct Sound 3DTM compatible A3DTM compatible I3DL2 compatible HRTF 3D Positional Audio SensauraTM 3D Enhancement (optional) 10 Bands of Software EQualizer Voice Cancellation and Key Shifting in Kara OK mode AVRack(R) Media Player Configuration Panel to improve Experience of User
2. General Description
The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meet performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bit volume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655 also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/ Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation, 10-band equalizer), HRTF 3D positional audio and SensauraTM 3D (optional) provide an excellent entertainment package and game experience for PC users. Besides, ALC655 includes Realtek's impedance sensing techniques that makes device load on outputs and inputs can be detected.
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MX36 MX66 MX6A.5 MX64 MX18 MX6A.4 Surround Volume Amp MX6A.0 MX0A MX0C +20dB PCBEEP Amp RESET# MONO-OUT FRONT-OUT MX0E MX38 SURR-OUT
Center/LFE Volume
CEN / LFE PCM out CEN/LFE-OUT (43,44)
DAC
Rear PCM out
DAC
Front PCM out
DAC
3. Block Diagram
PC-BEEP
PHONE MIC1 MX6A.10 CEN-OUT MIC2 LFE-OUT
MX20.8
Front-MIC Master Volume MX02
+20dB
MX74.0
4
MX10 MX12 MX16 MX20.9 stereo mix mono mix phone mic-L mic-R line CD aux MX1A M U X Record Gain MX1C
LINE-IN
SURR-OUT
MX6A.9
CD-IN
AUX-IN
Mono Volume MX06
mono analog stereo analog stereo digital
* : default setting
ADC
PCM in
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4. Pin Assignments
FRONT-OUT-R FRONT-OUT-L FRONT-MIC1 NC FRONT-MIC2 VRDA AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48
MONO-OUT AVDD2 SURR-OUT-L NC SURR-OUT-R AVSS2 CEN-OUT LFE-OUT JD0/GPIO0 XTLSEL SPDIFI/EAPD SPDIFO
24
23 22 21 20 19 18 17 16 15 14 13
ALC655
1 2 3 4 5 6 7 8 9 10 11 12
LINE-IN-R LINE-IN-L MIC2 MIC1 CD-R CD-GND CD-L JD1/GPIO1 JD2 AUX-R AUX-L PHONE
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DVDD1 XTL-IN XTL-OUT DVSS1 SDATA-OUT BIT-CLK DVSS2 SDATA-IN DVDD2 SYNC RESET# PC-BEEP
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5. Pin Description
5.1 Digital I/O Pins
Name XTL-IN XTL-OUT SDATAOUT BIT-CLK SDATA-IN SYNC RESET# JD1/GPIO1 JD2 JD0/GPIO0 XTLSEL SPDIFI / EAPD SPDIFO Type I O I IO O I I I/O I I/O I I/O O Pin No 2 3 5 6 8 10 11 17 16 45 46 47 48 Description Crystal input pad (24.576Mhz) Crystal output pad Serial TDM AC'97 output Bit clock output (12.288Mhz) Serial TDM AC'97 input Sample Sync (48Khz) AC'97 master H/W reset Jack Detect 1 / General Purpose I/O 1 Jack Detect 2 Jack Detect 0 / General Purpose I/O 0 Crystal Selection S/PDIF input / External Amplifier power down control S/PDIF output Characteristic Definition Crystal input pad Crystal output pad CMOS input CMOS input/output, Vt=0.35Vdd, internal pulled low by a 100K resistor. CMOS output, internal pulled low by a 100K resistor. CMOS input CMOS input Internally pulled high to AVDD by a 100K resistor Internally pulled high to AVDD by a 100K resistor Internally pulled high to AVDD by a 100K resistor Internally pulled high Digital input / output Digital output
TOTAL: 13 Pins XTLSEL=floating, bypass 14.318MHz 24.576MHz digital PLL. The clock source is 24.576MHz crystal or external clock. XTLSEL=pull low, select 14.318MHz 24.576MHz digital PLL
5.2 Analog I/O Pins
Name PC-BEEP PHONE AUX-L AUX-R CD-L CD-GND CD-R MIC1 MIC2 LINE-L LINE-R Front-MIC1 Front-MIC2 LINE-OUT-L LINE-OUT-R MONO-OUT S-OUT-L S-OUT-R CEN-OUT LFE-OUT Type I I I I I I I I/O I/O I/O I/O I I O O O O O O O Pin No 12 13 14 15 18 19 20 21 22 23 24 34 32 35 36 37 39 41 43 44 Description PC speaker input Speaker phone input AUX Left channel AUX Right channel CD audio Left channel CD audio analog GND CD audio Right channel First Mic in / CEN-OUT Secondary Mic in / CEN-OUT Line-In Left channel / S-OUT-L Line-In Right channel/ S-OUT-R Dedicated MIC Input 1 Dedicated MIC Input 1 (Supported by D version or later) Line-Out Left channel Line-Out Right channel Speaker Phone output Surround Out Left channel Surround Out Right channel Center Out channel Low Frequency Effect Out channel Characteristic Definition Analog input (1Vrms) Analog input (1Vrms) Analog input (1Vrms) Analog input (1Vrms) Analog input (1Vrms) Analog input (1Vrms) Analog input (1Vrms) Analog input (1Vrms) / Analog output (1Vrms) Analog input (1Vrms) / Analog output (1Vrms) Analog input (1Vrms) / Analog output (1Vrms) Analog input (1Vrms) / Analog output (1Vrms) Analog input (1Vrms) for front panel MIC input Analog input (1Vrms) for front panel MIC input Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) TOTAL: 20 Pins
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5.3 Filter/Reference
Name VREF VREFOUT AFILT1 AFILT2 VRDA NC Type O O O O O Pin No 27 28 29 30 31 33,40 Description Reference voltage Ref. voltage out with 5mA drive ADC anti-aliasing filter capacitor ADC anti-aliasing filter capacitor Vref for DAC Not connected Characteristic Definition Analog output. +4.7uf and 0.1uf cap to AVSS Analog output (2.5V/4.0V) 1nf cap to AVSS 1nf cap to AVSS 1uf cap to AVSS TOTAL: 7 Pins
5.4 Power/Ground
Name AVDD1 AVDD2 AVSS1 AVSS2 DVDD1 DVDD2 DVSS1 DVSS2 Type I I I I I I I I Pin No 25 38 26 42 1 9 4 7 Description Analog VDD (5.0V) Analog VDD (5.0V) Analog GND Analog GND Digital VDD (3.3V) Digital VDD (3.3V) Digital GND Digital GND TOTAL: 8 Pins Characteristic Definition The minimum value is 3.0V The maximum value is 5.5V The minimum value is 3.0V The maximum value is 5.5V
The minimum value is 3.0V (DVdd-0.3) The maximum value is 3.6V (DVdd+0.3) The minimum value is 3.0V (DVdd-0.3) The maximum value is 3.6V (DVdd+0.3)
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6. Registers
6.1 Mixer Registers
Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0. REG. NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT (HEX)
00h 02h 06h 0Ah 0Ch 0Eh 10h 12h 16h 18h 1Ah 1Ch 20h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 36h 38h 3Ah 64h 66h 6Ah 7Ah 7Ch 7Eh Reset Master Volume Mono-Out Volume PC_BEEP Volume PHONE Volume MIC Volume Line-In Volume CD Volume Aux Volume PCM Out Volume Record Select Record Gain General Purpose Audio Int. & Paging Power Down Ctrl/Status Extended Audio ID Extended Audio Status PCM front Sample Rate PCM Surr. Sample Rate PCM LFE. Sample Rate PCM Input Sample Rate Center/LFE Volume Surround Volume S/PDIF Ctl 0 Mute Mute Mute Mute Mute Mute Mute Mute Mute X Mute X I4 EAPD 0 X 1 1 1 1 Mute Mute V 0 X X X X X X X X X X X X I3 X 0 X 0 0 0 0 X X 0 X X 0 0 1 1 0 X X X X X X X X X X X X I2 PR5 X PRK 1 1 1 1 X X 0 0 0 0 0 0 ML4 ML3 ML2 ML1 ML0 Mute* * X X X X X X F7 X X NL4 CL4 AL4 PL4 X X X I1 PR4 X PRJ 1 1 1 1 F6 X X NL3 CL3 AL3 PL3 F5 X X NL2 CL2 AL2 PL2 F4 X X NL1 CL1 AL1 PL1 F3 X X NL0 CL0 AL0 PL0 F2 X X X X X X 0 X X F1 X 20dB X X X X X X X X X 0 X X F0 X X X X X X X X X X X X 0 0 0 0 0 MR4 MR3 MR2 MR1 MR0 MM4 MM3 MM2 MM1 MM0 PB3 PH4 MI4 NR4 CR4 AR4 PR4 X X X X X X PB2 PH3 MI3 NR3 CR3 AR3 PR3 PB1 PH2 MI2 NR2 CR2 AR2 PR2 PB0 PH1 MI1 NR1 CR1 AR1 PR1 X PH0 MI0 NR0 CR0 AR0 PR0 0000h 8000h 8000h 8000h 8008h 8008h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Fh 09C4h 0040h BB80h BB80h BB80h BB80h 8080h 8080h 2000h 0808h 0808h 0000h 60A2h 414Ch 4760h
X LRS2 LRS1 LRS0 X LRG3 LRG2 LRG1 LRG0 X X X MIX MS LBK I0 PR3 X PR2 X PR1 0 X 1 1 1 1 X PR0 X X
X RRS2 RRS1 RRS0 RRG3 RRG2 RRG1 RRG0 X X X X PG3 PG2 PG1 PG0
REF ANL DAC ADC X X 0 0 0 0 SPDIF SPDIF 0 0 0 0 X X 0 0 0 0 VRA VRA 0 0 0 0
REV1 REV0 PRI SPCV 1 1 1 1 0 0 0 0
LDAC SDAC CDAC
LDAC SDAC CDAC SPSA SPSA 1 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 X X CC2 X X 0 0 1 1 0 0 0 X X CC1 X X 0 0 0 1 0 0 0
LFE4 LFE3 LFE2 LFE1 LFE0 Mute LSR4 LSR3 LSR2 LSR1 LSR0 Mute L CC6 CC5 CC4 CC3 X X 0 0 0 0
CNT4 CNT3 CNT2 CNT1 CNT0 RSR4 RSR3 RSR2 RSR1 RSR0 PRE COPY /AUDI PRO O RSD4 RSD3 RSD2 RSD1 RSD0 CD4 0 0 0 0 CD3 0 0 1 0 CD2 0 0 1 0 CD1 0 0 0 0 CD0 0 0 0 0 CC0
SPSR1 SPSR0 X X 0 0 0 0
Surr. DAC Mute Volume CEN/LFE Mute DAC Volume Multi-channel 0 Ctl Extension 0 Control Vendor ID1 0 Vendor ID2 0
LSD4 LSD3 LSD2 LSD1 LSD0 LD4 0 0 0 0 LD3 0 0 0 0 LD2 0 0 0 1 LD1 0 0 0 1 LD0 0 0 1 1
X: reserved bit *: MX36 is the master volume control of CENTER/LFE output. MX38 is the master volume control of surround output.
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6.1.1 MX00 Reset Default: 0000H
Writing any value to this register will start a register reset, and causes all of the registers to revert to their default values. Reading this register returns the ID code of the specific part. Bit Type Function 15:10 Reserved 9 R Read as 0 (Does not support 20-bit ADC) 8 R Read as 0 (Does not support 18-bit ADC) 7 R Read as 0 (Does not support 20-bit DAC) 6 R Read as 0 (Does not support 18-bit DAC) 5 R Read as 0 (No Loudness support) 4 R Read as 0 (No True Line Level output support) 3 R Read as 0 (No simulated stereo for analog 3D block use) 2 R Read as 0 (No Bass & Treble Control) 1 R Read as 0 (No Modem Line support) 0 R Read as 0 (No Dedicated Mic PCM input channel) Writing any data into this register will reset all mixer registers to their default value. The written data is ignored.
6.1.2 MX02 (Front) Master Volume Default: 8000H
These registers control the volume level of Front-Out. Each step on the left and right channels correspond to 1.5dB in increase/decrease in volume. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:13 Reserved 12:8 R/W Master Left Volume (ML[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W Master Right Volume (MR[4:0]) in 1.5 dB steps For MR/ML, 00h 0 dB 1Fh 46.5 dB attenuation
6.1.3 MX06 MONO_OUT Volume Default: 8000H
Register 06H controls the mono volume output. Mono output is the same data sent on all output channels. Each step in bits 0:4 correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:5 Reserved 4:0 R/W Mono Master Volume (MM[4:0]) in 1.5 dB steps For MM, 00h 0 dB attenuation 1Fh 46.5 dB attenuation
6.1.4 MX0A PC BEEP Volume Default: 0000H
This register controls the input volume for the PC beep signal. Each step in bits 4:1 correspond to a 3dB increase/decrease in volume. 16 levels of volume are available, from 0000 to 1111.
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The purpose of this register is to allow the PC Beep signals to pass through the ALC655, eliminating the need for an external system speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the Front-Out. If the PC speaker/buzzer is eliminated, it is recommended to connect the external speakers at all times so the POST codes can be heard during reset. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:13 Reserved 12:5 R/W Internal PCBEEP Frequency, F[7:0] The internal PCBEEP frequency is the result of dividing the 48KHz clock by 4 times the number specified in F[7:0]. The lowest tone is 48KHz/(255*4)=47Hz. The highest tone is 48KHz/(1*4)=12KHz. A value of 00h in F[7:0] disables internal PCBEEP generator and allows external PCBEEP input. 4:1 R/W PC Beep Volume (PBV[3:0]) in 3 dB steps 0 Reserved For PB, 00h 0 dB attenuation 0Fh 45 dB attenuation
6.1.5 MX0C PHONE Volume Default: 8008H
Register 0CH controls the telephone input volume for software modem applications. Because software modem applications may not have a speaker, the CODEC can offer a speaker-out service. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:5 Reserved 4:0 R/W Phone Volume (PV[4:0]) in 1.5 dB steps For PV, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain
6.1.6 MX0E MIC Volume Default: 8008H
Register 0EH controls the microphone input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume, from 00000 to 11111. Each step in bit 6 corresponds to a magnification of 20dB increase in volume. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:7 Reserved 6 R/W 20 dB Boost Control 0: Normal 1: 20 dB boost 5 Reserved 4:0 R/W Mic Volume (MV[4:0]) in 1.5 dB steps For MV, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain
6.1.7 MX10 LINE_IN Volume Default: 8808H
Register 10H controls the LINE_IN input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 2003/07/31 10 Rev1.01
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15 14:13 12:8 7:5 4:0 R/W Mute Control 0: Normal 1: Mute (- dB) Reserved R/W Line-In Left Volume (NL[4:0]) in 1.5 dB steps Reserved R/W Line-In Right Volume (NR[4:0]) in 1.5 dB steps For NL/NR, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain
6.1.8 MX12 CD Volume Default: 8808H
Register 12H controls the CD input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. it Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:13 Reserved 12:8 R/W CD Left Volume (CL[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W CD Right Volume (CR[4:0]) in 1.5 dB steps For CL/CR, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain
6.1.9 MX16 AUX Volume Default: 8808H
Register 16H controls the auxiliary input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:13 Reserved 12:8 R/W AUX Left Volume (AL[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W AUX Right Volume (AR[4:0]) in 1.5 dB steps For AL/AR, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain
6.1.10 MX18 PCM_OUT Volume Default: 8808H
Register 18H controls the PCM_OUT output volume of front DAC. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:13 Reserved 12:8 R/W PCM Left Volume (PL[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W PCM Right Volume (PR[4:0]) in 1.5 dB steps 2003/07/31 11 Rev1.01
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For PL/PR, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain
6.1.11 MX1A Record Select Default: 0000H
Register 1AH controls the record input volume. Each step in bits 2:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 7 levels of volume, from 000 to 111. Each step in bits 10:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 7 levels of volume, from 000 to 111. Bit Type Function 15:11 Reserved 10:8 R/W Left Record Source Select (LRS[2:0]) 7:3 Reserved 2:0 R/W Right Record Source Select (RRS[2:0]) For LRS 0 MIC 1 CD LEFT 2 Muted 3 AUX LEFT 4 LINE LEFT 5 STEREO MIXER OUTPUT LEFT 6 MONO MIXER OUTPUT 7 PHONE For RRS 0 MIC 1 CD RIGHT 2 Muted 3 AUX RIGHT 4 LINE RIGHT 5 STEREO MIXER OUTPUT RIGHT 6 MONO MIXER OUTPUT 7 PHONE
6.1.12 MX1C Record Gain Default: 8000H
Register 1CH controls the record gain. Each step in bits 3:0 correspond to 1.5dB in increase/decrease in gain for the right channel, allowing 16 levels of gain, from 0000 to 1111. Each step in bits 11:8 correspond to 1.5dB in increase/decrease in gain for the left channel, allowing 16 levels of gain, from 0000 to 1111. Bit Type Function 15 R/W Mute Control 0: Normal 1: Mute (- dB) 14:12 Reserved 11:8 R/W Left Record Gain Select (LRG[3:0]) in 1.5 dB steps 7:4 Reserved 3:0 R/W Right Record Gain Select (RRG[3:0]) in 1.5 dB steps For LRG/RRG, 0Fh +22.5dB 00h 0 dB (No Gain)
6.1.13 MX20 General Purpose Register Default: 0000H
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This register is used to control several functions. Bit 13 enables or disables 3D control. Bit 9 allows selection of mono output. Bit 8 controls the mic selector. Bit 7 enables loopback of the AD output to the DA input without involving the AC-Link, allowing for full system performance measurements. Bit 15:12 11:10 9 8 7 6:0 Type R Function Reserved, Read as 0 DRSS[1:0], Double Rate Slot Select 01: PCM(n+1) data is on Slots 7/8 (Default) 00,10,11: Reserved R/W Mono Output Select 0: MIX 1: MIC R/W Mic Select MIC select 0: MIC 1+(Front-MIC) 1: MIC2+ (Front-MIC) R/W AD to DA Loop-Back Control 0: Disable 1: Enable Reserved Bit 7 enables ADC to front DAC loop-back.
6.1.14 MX24 Audio interrupt and Paging Default: 0000h
Bit 15 Type Function Interrupt Status, I4 0: Interrupt is clear. 1: Interrupt was generated Interrupt event and status are clear by writing a 1 to this bit. The status will change regardless of interrupt enable (I0). Interrupt Cause, I3 Reserved, read as 0 Interrupt Cause, I2 I2=0: Sense value in page ID-01h MX6A.[12:8] has not changed. 1: Sense cycle completed or new sense value in page ID-01h MX6A.[12:8] is available. This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt status (I4) has been confirmed as interrupting. I2 will be zero when I4 is cleared. Sense Cycle, I1 0: Sense cycle not in progress 1: Sense cycle start Writing a `1' to this bit causes a sense cycle start. If a sense cycle is in progress, writing a `0' to this bit will abort the sense cycle. Whether the data in the sense result register (page ID-01h MX6A) is valid or not is determined by the IV bit in MX6A, Page ID-1h. Interrupt Enable, I0 0: Interrupt is masked, interrupt status (I4) will not be shown in bit 0 in Slot 12 in SDATA-IN. 1: Interrupt is un-masked, interrupt status (I4) will be shown in bit 0 in Slot 12 in SDATA-IN. In ALC655, this bit controls the interrupt of sense cycle. Reserved, read as 0 Page Selector, PG[3:0] 0000b: Vendor Specific 0001b: Page ID 01 (AC'97 2.3 Discovery Descriptor Definition) Others: Reserved. This register is used to select a descriptor of 16 word pages between registers MX60 to MX6F. Value of 0 is used to select vendor specific space to maintain compatibility with AC'97 2.2 vendor specific register. Once PG[3:0] is not 0000b and 0001b, ALC655 will return zero data for ACLINK mixer read command.
14 13
R R
12
R/W
11
R/W
10:4 3:0
NA R/W
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6.1.15 MX26 Powerdown Control/Status Default: 0000H
This read/write register is used to program powerdown states and monitor subsystem readiness. The lower half of this register is read only status; a "1" indicating that the subsection is "ready." Ready is defined as the subsection's ability to perform in its nominal state. When the AC-Link "CODEC Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this powerdown control /status register to determine exactly which subsections, if any are ready. Bit 15 14 13 12 11 10 9 8 7:4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R R R R Function PR7 External Amplifier Power Down (EAPD) 0: EAPD output low (enable external amplifier) 1: EAPD output high (shut down external amplifier) Reserved PR5 0: Normal 1: Disable internal clock usage (BCLK still be output for modem CODEC) PR4 0: Normal 1: Power down AC-Link PR3 0: Normal 1: Power down Mixer (Vref off) PR2 0: Normal 1: Power down Mixer (Vref still on) PR1 0: Normal 1: Power down PCM DAC (front DAC) PR0 0: Normal 1: Power down PCM ADC and input MUX Reserved, Read as 0 Vref Status 1: Vref is up to normal level 0: Not yet Analog Mixer Status 1: Ready 0: Not yet DAC Status 1: Ready 0: Not yet ADC Status 1: Ready 0: Not yet
True table for power down mode: CDAC SDAC LDAC ADC DAC Mixer Vref ACLINK Int CLK EAPD * PR0=1 PD PR1=1 PD PR2=1 PD PR3=1 PD PD PD PD PD PD PD PR4=1 PD PD PD PD PD PD PR5=1 PD PD PD PD PD PD PR7=1 High PRI=1 PD PRJ=1 PD PRK=1 PD PD: Power down Blank: Don't care High: output high * SDAC= Surround DAC, LDAC= LFE DAC, CDAC= Center DAC. PRI: Center DAC power down control bit defined in MX2A.11 PRJ: Surround DAC power down control bit defined in MX2A.12 PRK: LFE DAC power down control bit defined in MX2A.13
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6.1.16 MX28 Extended Audio ID Default: 09C6H
The Extended Audio ID register is a read only register used to communicate information to the digital controller. Bit Type Function 15:14 R ID[1:0]. Always read as 0 13:12 Reserved, Read as 0 11:10 R REV [1:0]=10 to indicate that the ALC655 is AC'97 rev2.3 compliant 9 R AMAP, Read as 0. 8 R LDAC, Read as 1 (LFE DAC is supported, according to AC'97 rev2.3) 7 R SDAC, Read as 1 (Surround DAC is supported, according to AC'97 rev2.3) 6 R CDAC, Read as 1 (Center DAC is supported, according to AC'97 rev2.3) 5:3 Reserved, Read as 0 2 R SPDIF, Read as 1 (S/PDIF output is supported) 1 R DRA, Read as 1 (Double Rate Audio is supported) 0 R VRA, Read as 0 (Variable Rate Audio is not supported)
6.1.17 MX2A Extended Audio Status and Control Register Default: 05F0H
This register contains two active bits for powerdown and status of the surrounding DACs. Bits 1 & 2 are read/write bits which are used to enable or disable DRA and SPDIF respectively. Bits 4 & 5 are read/write bits used to determine the AC-LINK slot assignment of the S/PDIF. Bits 6, 7 & 8 are read only bits which tell the controller when the Center, Surround and LFE DACs are ready to receive data. Bit 10 is a read only bit which tells the controller if the S/PDIF configuration is valid. Bits 11, 12 & 13 are read/write bits which are used to powerdown the Center, Surround and LFE DACs respectively. Bit Type Function 15 R/W VCFG, Validity Configuration of S/PDIF Output Combined with MX3A.15 to decide validity control in S/PDIF output signal. 14 Reserved. 13 R/W Power Down LFE DAC. (PRK) 0: Normal 1: Power down LFE DAC 12 R/W Power Down Surround DAC. (PRJ) 0: Normal 1: Power down Surround DAC 11 R/W Power Down Center DAC. (PRI) 0: Normal 1: Power down Center DAC 10 R SPCV (S/PDIF Configuration Valid) 0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid 1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid 9 Reserved 8 R LFE DAC Status (LDAC). 0: Not yet 1: Ready 7 R Surround DAC Status (SDAC). 0: Not yet 1: Ready 6 R Center DAC Status (CDAC). 0: Not yet 1: Ready 5:4 R/W SPSA[1:0] (S/PDIF Slot Assignment) 00: S/PDIF source data assigned to AC-LINK slot3/4 01: S/PDIF source data assigned to AC-LINK slot7/8 10: S/PDIF source data assigned to AC-LINK slot6/9 11: S/PDIF source data assigned to AC-LINK slot10/11 (default) 3 Reserved 2 R/W SPDIF Enable. 1: Enable 0: Disable (Hi-Z) 1 R/W DRA Enable. 1: Enable 0: Disable 0 Reserved. 2003/07/31 15 Rev1.01
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SPCV is a read only bit that indicates whether the current S/PDIF-Out configuration is supported or not. If the configuration is supported, SPCV is set as 1 by H/W. So driver can check this bit to determine the status of the S/PDIF transmitter system. SPCV is always operating, independent of the SPDIF enable bit (MX2A.2). The S/PDIF output is active if MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid (SPCV=0), channel status is still output, but the output data bits will be all zero. The condition to allow S/PDIF output is SPDIF(MX2A.2)=1 & SPACV=1, otherwise the S/PDIF output will be all zero when MX2A.2=1 and SPACV=0 (invalid). Only front DACs supports 96KHz sample rate when DRA=1. MX2A.1 just selects clock source for front DACs. Software must mute surround DACs and CEN/LFE DACs.
6.1.18 MX2C PCM Front/Center Output Sample Rate Default: BB80H
Bit 15:0 Type R Function Read as BB80h. (ALC655 supports 48KHz sample rate.)
6.1.19 MX2E PCM Surround Output Sample Rate Default: BB80H
Bit 15:0 Type R Function Read as BB80h. (ALC655 supports 48KHz sample rate.)
6.1.20 MX30 PCM LFE Output Sample Rate Default: BB80H
Bit 15:0 Type R Function Read as BB80h. (ALC655 supports 48KHz sample rate.)
6.1.21 MX32 PCM Input Sample Rate Default: BB80H
Bit 15:0 Type R Function Read as BB80h. (ALC655 supports 48KHz sample rate.)
6.1.22 MX36 LFE/Center Master Volume Default: 8080H
Bit 15 14:13 12:8 7 6:5 4:0 Type Function R/W LFE Mute Control 0: Normal 1: Mute (- dB) Reserved R/W LFE Master Volume (LFE[4:0]) in 1.5 dB steps R/W Center Mute Control 0: Normal 1: Mute (- dB) Reserved R/W Center Master Volume (CNT[4:0]) in 1.5 dB steps For LFE/CEN, 00h 0dB 1Fh 46.5dB attenuation
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6.1.23 MX38 Surround Master Volume Default: 8080H
Bit 15 14:13 12:8 7 6:5 4:0 Type Function R/W Left Mute Control 0: Normal 1: Mute (- dB) Reserved R/W Surround Master Left Volume (LSR[4:0]) in 1.5 dB steps R/W Right Mute Control 0: Normal 1: Mute (- dB) Reserved R/W Surround Master Right Volume (RSR[4:0]) in 1.5 dB steps For LSR/RSR, 00h 0dB 1Fh -46.5dB attenuation
6.1.24 MX3A S/PDIF Output Channel Status and Control Default: 2000H
Bit 15 14 13:12 11 10:4 3 2 1 0 Type R/W Function Validity Control (control V bit in Sub-Frame) 0: The V bit (valid flag) in sub-frame depends on whether or not the S/PDIF data is under-run 1: The V bit in sub-frame is always send as 1 to indicate the invalid data is not suitable for receiver R DRS (Double Rate S/PDIF) The ALC655 does not support double rate S/PDIF, this bit is always 0. R/W SPSR [1:0] (S/PDIF Sample Rate) 10: Sample rate set to 48KHz. Fs[0:3]=0100 (default) 00,01,11: Reserved R/W LEVEL (Generation Level) R/W CC [6:0] (Category Code) R/W PRE (Preemphasis) 0: None 1: Filter preemphasis is 50/15 sec R/W COPY (Copyright) 0: Asserted 1: Not asserted R/W /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data R PRO (Professional or Consumer format) 0: Consumer format 1: Professional format ALC655 supports consumer channel status format, this bit is always 0 To ensure the control and status information started up correctly at the beginning of S/PDIF transmission, MX3A.[14:0] should only be written to when S/PDIF transmitter is disabled (MX2A.2=0). If validity control is set (MX3A.15=1), those data bits (bit 8 ~ bit 27) should be forced to 0 to get better compatibility with mini disc.
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6.2 Vendor Defined Registers (Page ID-00h)
These registers are available to Realtek and Realtek customers for specialized functions.
6.2.1 MX60 S/PDIF Input Channel Status [15:0] Default: 0000h
The data in MX60 are captured from channel status [15:0] of S/PDIF-IN signal. Bit Type Function 15 R LEVEL (Generation Level) 14:8 R CC[6:0] (Category Code) 7:6 R Mode[1:0] 5:3 R PRE[2:0] (Pre-Emphasis) 2 R COPY (Copyright) 0: asserted 1: Not asserted 1 R /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 0 R PRO (Professional or Consumer format) 0: consumer format 1: professional format
6.2.2 MX62 S/PDIF Input Channel Status [29:15] Default: 0000h
The data in MX62 are captured from channel status [29:16] of S/PDIF-IN signal. Bit Type Function 15 R "V" bit in sub-frame of SPDIFI 0: Data X and Y are valid 1: At least one of data X and Y is invalid This bit is real-time updated, and it is meaning when S/PDIF-IN is locked 14 R S/PDIF-IN Input Signal Locked by hardware 0: Unlocked 1: Locked 13:12 R Ca[1:0] ( Clock Accuracy) 11:8 R Fs[3:0]. (Sample Frequency in channel status) 0000: 44.1KHz 0010: 48 KHz 0011: 32 KHz Others: Reserved 7:4 R Cn[3:0] (Channel Number) 3:0 R Sn[3:0] (Source Number) The bits [13:0] are captured from channel status [29:16] of SPDIFI. The consumer channel status of SPDIFI (bit0~bit31): 0 1 2 3 4 5 6 7 PRO /AUDIO COPY PRE0 PRE1 PRE2 Mode0 Mode1 8 9 10 11 12 13 14 15 CC0 CC1 CC2 CC3 CC4 CC5 CC6 LEVEL 16 17 18 19 20 21 22 23 Sn0 Sn1 Sn2 Sn3 Cn0 Cn1 Cn2 Cn3 24 25 26 27 28 29 30 31 Fs0 Fs1 Fs2 Fs3 Ca0 Ca1 0 0 The data from SPDIF input is forced to 0 once the SPDIF input signal is unlocked. Software must check this `LOCK' bit before dealing with SPDIF input operations.
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6.2.3 MX64 Surround DAC Volume Default: 0808H
Bit 15 14:13 12:8 7:5 4:0 Type Function R/W Mute Control 0: Normal 1: Mute (- dB) Reserved R/W Surround DAC Left Volume (SDL[4:0]) in 1.5 dB steps Reserved R/W Surround DAC Right Volume (SDR[4:0]) in 1.5 dB steps For SDL/SDR, 00h +12 dB gain 08h 0dB 1Fh -34.5dB attenuation The default value is 0808H (unmuted).
6.2.4 MX66 Center/LFE DAC Volume Default: 0808H
Bit 15 14:13 12:8 7:5 4:0 Type Function R/W Mute Control 0: Normal 1: Mute (- dB) Reserved R/W LFE DAC Volume (LD[4:0]) in 1.5 dB steps Reserved R/W Center DAC Volume (CD[4:0]) in 1.5 dB steps For LD/CD, 00h +12 dB gain 08h 0dB 1Fh -34.5dB attenuation The default value is 0808H (unmuted).
6.2.5 MX6A Data Flow Control Default: 0000h
This register is used to control various parts of the ALC655 multi-channel functions. Bit Type Function 15 RW SPDIF Input Enable 0: Disable (Default) 1: Enable 14 R/W SPDIF-In Monitoring Control 0: Disable, SPDIFI data is not added into PCM data to DAC. (Default) 1: Enable, MSB 16-bit of SPDIFI data will be added into PCM data to DAC if SPDIFI is locked. 13:12 R/W S/PDIF Output Source 00: S/PDIF output data is from ACLINK (default) 01: S/PDIF output data is from ADC 10: Directly bypass S/PDIF-In signal to S/PDIF-Out 11: Reserved. 11 R/W PCM Data to AC-LINK 0: PCM Data are from ADC (default) 1: PCM Data are from SPDIF input. 10 R/W MIC1 & MIC2 / CENTER & LFE Output Control 0: pin-21 is MIC1, pin-22 is MIC2 (default) 1: pin-21 is CENTER-Out, pin-22 is LFE-Out. 9 R/W Line-In / Surround Output Control 0: pin-23 and pin-24 are analog input (Line-In). (default) 1: pin-23 and pin-24 are duplicated output of surround channel (Surround-Out) 8:6 Reserved 2003/07/31 19 Rev1.01
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5 4 3:1 0 R/W R/W R/W Analog Input Pass to Center/LFE Control 0: off 1: on Analog Input Pass to Surround Control 0: off 1: on Reserved Surround Output Source. 0: S-OUT is the real surround output. (default) 1: S-OUT is the duplicated output of LINE-OUT
6.3 Discovery Descriptor (Page ID-01h)
These registers are defined in AC'97 2.3 for sensing and analog plug&play functions.
6.3.1 MX62 PCI Sub System ID Default: FFFFh
Bit 15:0 Type R/W Function PCI Sub System Vendor ID This register can be written once only after power on, and is not affected by AC97 cold reset. System manufacture's BIOS can set its own sub-system ID. The default value FFFFh means this register is implemented and data is not set by BIOS.
6.3.2 MX64 PCI Sub Vendor ID Default: FFFFh
Bit 15:0 Type R/W Function PCI Vendor ID This register can be written once only after power on, and is not affected by AC97 cold reset. System manufacture's BIOS can set its own sub-vendor ID. The default value FFFFh means this register is implemented and data is not set by BIOS.
6.3.3 MX66 Sense Function Select Default: 0000h
Bit 15:5 4:1 Type R/W Function Reserved Function Code bits, FC[3:0] These bits specify the type of audio function described in page ID-01h MX66, MX68 and MX6A. 0h: FRONT OUT 1h: SURROUND OUT 5h: MIC1 In 6h: MIC2 In 7h: LINE In Others: Not supported Tip or Ring Selection, T/R This bit sets which jack conductor the sense value is measured from. It is combined with FC[3:0]. 0: Tip (Left channel) 1: Ring (Right channel)
0
R/W
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6.3.4 MX68 Sense Function Information Default: 02F1h
Bit 15:5 4 Type R/W Function Reserved Information Valid bit, IV 0: After a sense cycle is completed indicates that no information is provided on the sensing method 1: After a sense cycle is completed indicates that information is provided on the sensing method Clearing this bit by writing "1", writing "0" to this bit has no effect. Reserved Function Information Present, FIP This bit is set to a `0' indicates that the G[4:0], INV, DL[4:0] and ST[2:0] bits are not supported.
3:1 0
NA R
6.3.5 MX6A Sense Detail Default: 0000h
Bit 15:13 12:8 Type R Function Reserved Sense bits, S[4:0] (Default value depends on sensed result after Cold Reset) For output devices: 02h: Not specificed or unknown 05h: Powered speaker 06h: Earphone or passive speaker Other: Not supported For input deices: 12h: Not specified or unknown 13h: Mono Microphone 15h: Stereo Line-In Other: Not supported This field reports the type of output/input peripheral plugged in the jack after sensing. Always read as 0.
7:0
R
6.4 Extension Registers
6.4.1 MX78 GPIO(JD) Interrupt Control & Status Default: 0000h
Bit 15 14 13 12 11:10 9 8 2003/07/31 Type R/W R/W R/W R/W NA R/W R/W Function GPIO Statue Indication in SDATA_IN 0:The status of GPIO0(JD0)/GPIO1(JD1)/JD2 and its valid tag are not indicated in SDATA_IN. 1: The status of GPIO0(JD0)/GPIO1(JD1)/JD2 and its valid tag are indicated in SDATA_IN JD2 interrupt Enable 0: Disable 1: Enable. A low to high transaction will trigger the interrupt in bit0 in SDATA_IN's slot-12. GPIO1(JD1) interrupt Enable (when GPIO1/JD1 is used as input) 0: Disable 1: Enable. A low to high transaction will trigger the interrupt in bit0 in SDATA_IN's slot-12. GPIO0(JD0) interrupt Enable (when GPIO0/JD0 is used as input) 0: Disable 1: Enable. A low to high transaction will trigger the interrupt in bit0 in SDATA_IN's slot-12. Reserved GPIO1Primitiveness Control 0: Set GPIO1(JD1) as input pin. 1: Set GPIO1(JD1) as output pin. GPIO0 Primitiveness Control 0: Set GPIO0(JD0) as input pin. 21 Rev1.01
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7 6 1: Set GPIO0(JD0) as output pin. Reserved JD2 Interrupt Status (JD2_IS) 0: No JD2 interrupt. 1: JD2 interrupt. JD2_IS= (MX78.14==1) & (JD2 transition). Write 1 to clear this status bit. R/W GPIO1/JD1 Interrupt Status (JD1_IS). (When GPIO1 is used as input) 0: No JD1 interrupt. 1: JD1 interrupt. JD1_IS= (MX78.13==1)&(MX78.9==0) & (JD1 transition). Write 1 to clear this status bit. R/W GPIO0/JD0 Interrupt Status (JD0_IS). (When GPIO0 is used as input) 0: No JD0 interrupt. 1: JD0 interrupt. JD0_IS= (MX78.12==1)&(MX78.8==0) & (JD0 transition) Write 1 to clear this status bit. NA Reserved R JD2 Input Status 0: JD2 is driven low by external device (input). 1: JD2 is driven high by external device (input). R/W GPIO1(JD1) Input/Output Status 0: GPIO1 is driven low by/to external device. 1: GPIO1 is driven high by/to external device. R/W GPIO0(JD0) Input/Output Status 0: GPIO0 is driven low by/to external device. 1: GPIO0 is driven high by/to external device. GPINT in bit0 of SDATA_IN's slot-12 = (MX78.4 | MX78.5 | MX78.6 ) | (MX24.15&MX24.11) When GPIO1/0 is used as input pin, its status will be also reflected in bit2/1 of SDIN's slot-12. Once GPIO1/0 is used as output pin, the bit2/1 of SDATA_IN's slot-12 is always 0. The GPIOx is internally pulled high by a weak resistor. (Weak resistor is about 50K ~ 100K ohm) NA R/W
5
4
3 2 1 0
6.4.2 MX7A Miscellaneous Control Default: 60A2H
This register is used for three types of information. Bit 0 is a read/write bit which enables/disables the S/PDIF input receiver. Bit 1 is used to switch pin 47, which is duplexed due for pin-count reduction, between EAPD and S/PDIF modes. Bit 2 is used to select the clock source for the ALC655. Bit Type Function 15 R Clock Source Selection (XTLSEL) 0: Disable 14.318M 24.576M digital PLL. (Default if XTSEL is floating) 1: Enable 14.318M 24.576M digital PLL. (Default if XTLSEL is pull low) 14:13 Reserved 12 R/W Vrefout Disable 0: Vrefout is driven by the internal reference (Default) 1: Vrefout is in high-Z mode. Software must set this bit to disable Vrefout output before MX6A.10 is set (MIC1 and MIC2 are shared as Center and LFE output). 11 R/W Independent Left/Right Mute Control for MX02 0: Disable, only bit15 is a mute bit for left and right channel (Default) 1: Enable, bit15 mute left channel, bit7 mute right channel. 10:4 Reserved 3 R/W JD2 Control Surround-Out, Center-Out and LFE-Out 0: Disable. (Default) 1: Enable, when (MX7A.3=1 & MX78.2=1), Surr-Out and CEN/LFE-Out are muted. 2 R/W JD1 Control Surround-Out, Center-Out and LFE-Out 2003/07/31 22 Rev1.01
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1 0 R/W R/W 0: Disable. (Default) 1: Enable, when (MX7A.2=1 & MX78.1=1 & MX78.9=0), Surr-Out and CEN/LFE-Out are muted. Pin-47 Function Selection 0: EAPD 1: SPDIF Input (Default) JD0 Control Surround-Out, Center-Out and LFE-Out 0: Disable. (Default) 1: Enable, when (MX7A.0=1 & MX78.0=1 & MX78.8=0), Surr-Out and CEN/LFE-Out are muted. (Internal MX36.15, MX36.7, MX38.15 and MX38.7 are all set to 1.) This function should be implement by digital designer.
6.4.4 MX7C VENDOR ID1 Default: 414CH
The two registers (MX7C Vendor ID1 and MX7E Vendor ID2) contain four 8-bit ID codes. The first three codes have been assigned by Microsoft for Plug and Play definitions. The fourth code is a Realtek assigned code identifying the ALC655. The MX7C Vendor ID1 register contains the value 414Ch, which is the first and second characters of the Microsoft ID code. The MX7C Vendor ID2 register contains the value 4760h, which is the third of the Microsoft ID code. Bit 15:0 Type R Function Vendor ID- "AL"
6.4.5 MX7E VENDOR ID2 Default: 4760H
Bit 15:8 7:4 3:0 Type R R R Function Vendor ID- "G" Chip ID- 0110b (ALC655) Version number- 0000b.
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7. Electrical Characteristics
7.1.1 Absolute Maximum Ratings
Parameter Power Supplies Digital Analog Operating Ambient Temperature Storage Temperature ESD (Electrostatic Discharge) Symbol DVDD AVDD Ta Ts Minimum 3.0 3.5 0 Typical 3.3 5.0 Susceptibility Voltage Maximum 3.6 5.5 +70 +125 Units V V o C o C
7.1.2 Threshold Hold Voltage
Dvdd= 3.3V5%, Tambient=250C, with 50pF external load. Parameter Symbol Input voltage range Vin Low level input voltage VIL (SYNC,SDATA_OUT,RESET#) Low level input voltage VIL (XTAL_IN,BIT_CLK) Low level input voltage VIL (Other digital pins) High level input voltage VIH (SYNC,SDATA_OUT,RESET#) High level input voltage VIH (XTAL_IN,BIT_CLK) High level input voltage VIH (Other digital pins) High level output voltage VOH Low level output voltage VOL Input leakage current Output leakage current (Hi-Z) Output buffer drive current Internal pull up resistance Minimum -0.30 0.4DVdd 0.4DVdd 0.4DVdd 0.9DVdd -10 -10 30k Typical 0.7 1.0 1.2 1.7 2.2 1.7 5 50k Maximum Dvdd+0.30 0.35Dvdd 0.35Dvdd 0.35Dvdd 0.1DVdd 10 10 100k Units V V V V V V V V V A A mA
7.1.3 Digital Filter Characteristics
Filter ADC Lowpass Filter Symbol Passband Stopband Stopband Rejection Passband Frequency Response Passband Stopband Stopband Rejection Passband Frequency Response Minimum 0 28.8 Typical -76.0 +- 0.20 0 28.8 -78.5 +- 0.20 19.2 Maximum 19.2 Units KHz KHz dB dB KHz KHz dB dB
DAC Lowpass Filter
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7.1.4 S/PDIF output Characteristics
Dvdd= 3.3V, Tambient=250C, with 75 external load. Parameter Symbol High level output voltage VOH Low level output voltage VOL Minimum 3.0 Typical 3.3 0 Maximum 0.5 Units V V
7.2 AC Timing Characteristics
7.2.1 Cold Reset
Parameter RESET# active low pulse width RESET# inactive to BIT_CLK Startup delay Symbol Trst_low Trst2clk Minimum 1.0 162.8 Typical Maximum Units s ns
Cold reset timing diagram
7.2.2 Warm Reset
Parameter SYNC active high pulse width SYNC inactive to BIT_CLK Startup delay Symbol Tsync_high Tsync2clk Minimum 1.0 162.8 Typical Maximum Units s ns
Warm reset timing diagram
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7.2.3 AC-Link Clocks
Parameter Symbol BIT_CLK frequency BIT_CLK period Tclk_period BIT_CLK output jitter BIT_CLK high pulse width (note Tclk_high 2) BIT_CLK low pulse width (note 2) Tclk_low SYNC frequency SYNC period Tsync_period SYNC high pulse width Tsync_high SYNC low pulse width Tsync_low Note 1: Worse case duty cycle restricted to 45/55. Minimum 36 36 Typical 12.288 81.4 40.7 40.7 48.0 20.8 1.3 19.5 Maximum 750 45 45 Units MHz ns ps ns ns KHz s s s
BIT_CLK and SYNC timing diagram
7.2.4 Data Output and Input Timing
Parameter Symbol Minimum Typical Maximum Output Valid Delay from rising tco 15 edge of BIT_CLK Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Note 2: 50pF external load Parameter Symbol Minimum Typical Maximum Input Setup to falling edge of tsetup 10 BIT_CLK Input Hold from falling edge of thold 10 BIT_CLK Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Parameter Symbol Minimum Typical Maximum BIT_CLK combined rise or fall 7 plus flight time SDATA combined rise or fall 7 plus flight time Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes. Units ns
Units ns ns
Units ns ns
Data Output and Input timing diagram
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7.2.5 Signal Rise and Fall Timing
Parameter Symbol BIT_CLK rise time Triseclk BIT_CLK fall time Tfallclk SYNC rise time Trisesync SYNC fall time Tfallsync SDATA_IN rise time Trisedin SDATA_IN fall time Tfalldin SDATA_OUT rise time Trisedout SDATA_OUT fall time Tfalldout Note 1: 75pF external load (50 pF in AC'97 rev2.1) Note 2: rise is from 10% to 90% of Vdd (Vol to Voh) Note 3: fall is from 90% to 10% of Vdd (Voh to Vol) Minimum Typical Maximum 6 6 6 6 6 6 6 6 Units ns ns ns ns ns ns ns ns
Signal Rise and Fall timing diagram
7.2.6 AC-Link Low Power Mode Timing
Parameter End of slot 2 to BIT_CLK, SDATA_IN low Symbol Ts2_pdown Minimum Typical Maximum 1.0 Units s
AC-Link low power mode timing diagram
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7.2.7 ATE Test Mode
To meet AC'97 rev2.3 specifications, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in test mode. Parameter Symbol Minimum Typical Maximum Units Setup to trailing edge of RESET# Tsetup2rst 15.0 ns (also applies to SYNC) Rising edge of RESET# to Hi-Z Toff 25.0 ns delay
ATE test mode timing diagram
7.2.8 AC-Link IO Pin Capacitance and Loading
Output Pin BIT_CLK (must support 2 CODECs) SDATA_IN 1 CODEC 55pF 47.5pF 2 CODEC 62.5pF 55pF 3 CODEC 75pF 60pF 4 CODEC 85pF 62.5pF
7.2.9 SPDIF Output
SPDIF_OUT Rise time/fall time Duty cycle Minimum 0 45
T(h)
Typical
Maximum 10 55
Units % %
T(l)
90%
50% 10%
T(r)
T(f)
Notes:
Rise time = 100 * T(r)/ (T(l)+ T(h))% Fall time = 100 * T(f)/ (T(l)+ T(h))% Duty cycle = 100 * T(h)/ (T(l)+ T(h))%
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8. Analog Performance Characteristics
Standard test conditions: Tambient=250C, Dvdd=3.3V 5%,Avdd=5.0V5% 1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms 10K/50pF load; Test bench Characterization BW: 10Hz~22KHz 0dB attenuation; tone and 3D disabled Parameter Minimum Typical Maximum Full scale input voltage: Line inputs (Mixers) 1.6 Line inputs (A/D) 1.0 Mic input (0 dB) 1.6 Mic input (20 dB boost) 0.16 Full scale output voltage FRONT-OUT / SURROUND-OUT 1.25 CEN/LFE-OUT 1.25 Analog to Analog S/N: CD to LINE-OUT 90 Other to LINE-OUT 90 Analog frequency response 10 22,000 S/N (A-weighted): D/A 86 A/D 86 Total Harmonic Distortion: D/A -70 A/D -75 D/A & A/D frequency response 20 19,200 Transition Band 19,200 28,800 Stop Band 28,800 Stop Band Rejection -75 Out-of-Band Rejection -65 Group delay 1 Power Supply Rejection -40 MIC Boost Gain 6 30 Master Volume (FRONT/SURR/CEN/LFE): 32 step Step Size 1.5 Attenuation Control Range 0 -46.5 Master Volume (MONO-OUT): 32 step Step Size 1.5 Attenuation Control Range 0 -46.5 PC Beep Volume 16 steps: Step Size 3.0 Attenuation Control Range 0 -45 Analog Mixer Volume 32 steps: Step Size 1.5 Gain Control Range -34.5 +12 Record Gain 16 steps: Step Size 1.5 Gain Control Range 0 +22.5 Input impedance (gain = 0dB, mixer = off) LINE-IN, CD-IN, AUX-IN, MIC1 / MIC2 64 PCBEEP, PHONE 16 cont...
Units Vrms
Vrms Vrms dB Hz dB dB Hz Hz Hz dB dB ms dB dB dB dB dB dB dB dB dB dB dB dB K K
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Output Impedance FRONT-OUT / SURROUND-OUT CEN/LFE-OUT MONO-OUT Amplifier Maximum Output Power @20 load Power Supply Current VA=5.0V VD=3.3V Power Down Current VA=5.0V VD=3.3V Vrefout/Vrefout2/Vrefout3 Vrefout Drive Current 5 200 500 50 15 2.50 5 50 1000 700 4.0 mW mA mA uA uA V mA
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9. Design Suggestions
9.1 Clocking
The clock source is decided by XTLSEL latched from pin-46 after power-on reset. The clock source of different configuration is listed below: Configuration Operation & ID0 Pin-46(XTLSEL) ID0 BIT-CLK Clock source NC 0 (Primary) Output Crystal or ext. 24.576MHz is attached 12.288MHz at XTL-IN Low 0 (Primary) Output Crystal or ext. 14.318MHz is attached 12.288MHz at XTL-IN NC 0 (Primary) Input 12.288M input at BIT-CLK *Low: Pulled low by a 0 ohm resistor. NC: Not connect or pulled high. *Pin-46is internally pulled high by a weak resistor. According to AC'97 ver 2.3, the primary mode while RESET# is asserted, if a clock is present at BIT-CLK pin for at least 5 cycles before RESET# is de-asserted, ALC655 is a consumer of BITCLK. ALC655 should use external 12.288MHz BITCLK as its clock source.
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9.2 AC-Link
When the ALC655 receives serial data from the AC97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK. When the ALC655 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK. The ALC655 will return any uninstalled bits or registers with 0 for read operations. The ALC655 also stuffs the unimplemented slot or bit with 0 in SDATA_IN. Note that AC-LINK is MSB-justified. Refer to "Audio CODEC '97 Component Specification Revision 2.3." for details.
Slot# SYNC SDATA-OUT
0
1
2
3
4
PCM R PCM R
5
6
7
8
9
10
11
12
TAG CMD DATA PCM L TAG ADD DATA PCM L
CEN SURR SURR LFE SPDIF SPDIF L R L R
SDATA-IN
Default ALC655 Slot Arrangement - CODEC ID = 00 (ALC655 supports only primary mode)
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9.3 Reset
There are 3 types of reset operations: Cold, Warm and Register. Reset Type Cold Register Warm CODEC response Reset all hardware logic and all registers to its default value. Write register indexed 00h Reset all registers to its default value. Driven SYNC high for specified period without Reactivates AC-LINK, no change to register values. BIT_CLK Trigger condition Assert RESET# for a specified period
The AC97 controller should drive SYNC and SDATA_OUT low during the period of RESET# assertion to guarantee that the ALC655 has reset successfully.
9.4 CD Input
It is important to pay attention to differential CD input. Below is an example of differential CD input.
Example of differential CD input
9.5 Odd Addressed Register Access
The ALC655 will return "0000h" when odd-addressed and unimplemented registers are read.
9.6 Power-down Mode
It is important to pay special attention to the power down control register (index 26h), especially PR4 (powerdown AC-link).
9.7 Test Mode
To provide compatibility with AC'97 rev2.2, the ALC655 will float its digital output pins in both ATE and Vendor-Specific test modes. Please refer to AC'97 rev2.2 section 9.2 for a detailed description of the test modes.
9.7.1 ATE In Circuit Test Mode
SDATA_OUT is sampled high at the trailing edge of RESET#. In this mode, the ALC655 will drive BIT_CLK, SDATA_IN, EAPD and SPDIFO to high impedance.
9.7.2 Vendor Specific Test Mode
The Vendor Specific Test mode is no longer supported.
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9.8 POWER OFF CD Function
The `POWER OFF CD' function describes a state after the system has been shut down (digital power is off) and a +5V analog power is supplied, the ALC655 will turn on the CD-IN op and output amplifier. It is possible to design a system which will save op-amp circuitry and bypass CD output directly to the speaker. The figure below indicates the system application circuitry to support the `POWER OFF CD' function. The operation mode is defined by +3.3VCC and +5VA analog power without VAUX is required for ALC20x series codec. +3.3VCC No (0) No (0) No (0) Yes (1) Yes (1) +5VA No (0) Yes (1) No (0) Yes (1) +5Vstandby No (0) Yes (1) No (0) Operation Mode Shut Down Power Off CD Power Off CD Digital on, Analog is off Normal
+5VA
+5Vstandby
+3.3VCC
D1 1N5817M/CYL D2
0.1u
+
10u
+
10u
0.1u
1N5817M/CYL
2 3
XTL-IN XTL-OUT
AVDD AVDD
VDD VDD
25 38
1 9
FRONT-OUT-L FRONT-OUT-R MONO-OUT VREF VREFOUT AFILT1 AFILT2
35 36 37 27 28 29 30 31 32 33 34 43 44 45 46 47 48 39 40 41
11 6 10 5 8 12 13 14 15 16 17 18 20 21 22 23 24
RESET# BITCLK SYNC SDOUT SDIN PC-BEEP PHONE AUX-L AUX-R JD2 JD1/GPIO1 CD-L CD-R MIC1 MIC2 LINE-L LINE-R GND GND
ALC655
0 1 2 3 4 0
1u 1u
19
2003/07/31
26 42
4 7
AGND AGND
1u
CD-GND
CD-IN
0
VRDA VRAD NC FRONT-MIC CEN-OUT LFE-OUT JD0/GPIO0 XTLSEL SPDIFI/EAPD SPDIFO SURR-OUT-L NC SURR-OUT-R
34
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ALC655
10. Application Circuits
The application circuit is for design reference only. System designers are suggested to visit Realtek's web site to download the latest application circuits. To get the best compatibility in hardware design and software driver, any modifications of application circuits have to be confirmed by Realtek.
FRONT-MIC2 R38 0@658 JD4 JD4 C75 1u@655
VREFOUT2 for UAJ2
R43
0@658
+5VAUX D1 1N4148@655/658
R43 is only for ALC658(UAJ2 bias voltage)
C9 FRONT-MIC1 C4 1u C13 1u@650 1u@650 + C1 10u
Reserved for ALC655/658 (Power Off CD)
Reserve for fine tune accuracy of Jack Sensing
R55 5.6K@ALC655/658 VREFOUT +5VA C6 10u + C15 10u +5VA
+12V U1 3 VREFOUT + C7 C11 0.1u LM7805CT/200mA IN GND 1 L3 FERB
OUT
FRONT-OUT-L FRONT-OUT-R
C5 C12
100u 100u C10 1000P
VREFOUT3 for UAJ1
R46
0@658
C14 1000P 36 35 34 33 32 31 30 29 28 27
C16 1u 25 U8
+
R46 is for ALC658(UAJ1 bias voltage)
+5VA C19 10u + C20 1u 37 38 SURR-OUT-L JD3 JD3 SURR-OUT-R C26 1u C23 1u 39 40 41 42 CENTER-OUT LFE-OUT JD0 JD0 R4 SPDIFI C29 C31 1u 1u 43 44 45 0@EXT-14.318M 46 47 48
AFILT2
AFILT1
AVSS1
26
VREFOUT
FRONT-OUT-L
FRONT-OUT-R
FRONT-MIC1
VREFOUT2
FRONT-MIC2/VRDA
VRDA/VRAD
AVDD1
VREF
C21 24 23 22 21 20 19 18 17 16 15 14 13 C37 C22 C24 C25 C27 C28 C30
1u 1u 1u 1u 1u 1u 1u R1 R2 R3
LINE-IN-R LINE-IN-L MIC2-IN MIC1-IN 0 0 0 C67 1u@650 C68 J5 4 3 2 1
LINE-IN-R LINE-IN-L MIC2-IN MIC1-IN J4 CD-IN Header 4 3 2 1 J16 1 2 3 4 VIDEO-IN Header
MONO-O AVDD2
LINE-IN-R LINE-IN-L MIC2 MIC1 CD-R CD-GND CD-L JD1/VIDEO-R JD2/VIDEO-L AUX-R AUX-L
SURR-OUT-L/HP-OUT-L NC SURR-OUT-R/HP-OUT-R AVSS2 CEN-OUT LFE-OUT JD0/GPIO0 XTLSEL/ID1# SPDIFI/EAPD
ALC650/655/658
1u@650 R34 0@655/658 JD1 R44 0@655/658 JD2
JD1 JD2
SDATA-OUT
SDATA-IN
RESET#
BIT-CLK
DVDD1
DVDD2
DVSS1
DVSS2
XTL-IN
SYNC
Spilt by DGND
SPDIFO
PC-BEEP
SPDIFO XTL-OUT
PHONE
1u@655/650 C39 1u@655/650
AUX-IN Header
C69 C70
220u@658 220u@658
UAJ2-R UAJ2-L
10
11
+3.3VDD C43 10u C42 + C44 0.1u 0.1u C12A1 1u
12
1
2
3
4
5
6
7
8
9
ALC-AC97
C41 1u R7 0
Audio-From-Modem
R12B1 10K Signal-From-PCSPK C12B1 R12A1 1K
R8 0@EXT-14.318M EXT 14.318MHz
Y1 24.576MHz R9 22
+3.3VDD AC97-RESET# R10 22 AC97-SYNC
100P
C45 22P
C46 22P
AC97-SDIN AC97-BCLK AC97-SDOUT
DGND
AGND
Crysatl Saving:
R8,R4=0; Y1,C45,C46=X (EXT-14.318MHz clock) R8,R4=X; Y1=24.576M, C45,C46=22p (24.576MHz crystal)
C50 22P
Tied at one point only under the codec or near the codec
ALC655
C67 C68 X X 0 0 1u 1u X X X X 1u X X
ALC658
X X 0 0 X X 100u 100u X X 1u 0 0
+
+
ALC650
1u 1u X X 1u 1u X X 1u 1u X X X
Arrangement of Jack Detection Pin:(ALC655)
JD0 for MIC-IN JD1 for FRONT-OUT JD2 for LINE-IN
R34 R44 C37 C39 C69
Arrangement of Jack Detection Pin:(ALC658)
JD0 for MIC-IN JD1 for UAJ1(Front-Pannel) JD2 for UAJ2 (Front-Pannel) JD3 for FRONT-OUT JD4 for LINE-IN
C70 C13 C9 C75 R46 R43
Compatible Filter Connection with ALC655 2003/07/31 35 Rev1.01
2
+ +
+
C8 +10u
+10u
ALC655
INTEL Front Panel I/O Design Guide V1.0
FRONT-MIC1 R26 0 20 20 20@Reserve 20@Reserve J11 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 +5VA
SURR-OUT-L SPDIF-IN
SURR-OUT-L AGND DGND SPDIF-IN DGND
J8 1 3 5 7 9 2 4 6 8 10
SURR-OUT-R AGND +3.3VDD +5VDD SPDIF-OUT
R27 +5VA JD1 R61 SURR-OUT-L JD0 R51
10K 0@658
FRONT-OUT-R R28 FRONT-OUT-L R29 0@Reserve SURR-OUT-R R39 SURR-OUT-L R40
KEY
AUD-RET-R
AUD-RET-R AUD-RET-L
AUD-RET-L
SPDIF-OUT
Onboard Header for Back Panel Bracket
VREFOUT2 for UAJ2 FRONT-MIC1 R47 JD2 R62 20@655 0@658 UAJ2-L
Onboard Header for Front Panel
VREFOUT3 for UAJ1 UAJ2-R R48 20@655 FRONT-MIC2
REALTEK Front Panel I/O for UAJ
R26 ALC655/658/650(with Intel Front Pannel) ALC658(with Realtek Front Pannel - UAJ function)
0 X
R61
X 0
R62
X 0
R51
X X
R47
X X
R48
X X
Onboard Headers for Back Panel Bracket and Front Panel
For Automatic Jack Sensing Only
For ALC650:
R42 VREFOUT VREFOUT 10K JD0 + C74 3.3u
JD Block=X
For ALC655 and ALC658:
JD Block=0
JD Block
R12 4.7K@655/658(Stereo MIC) MIC2-IN MIC1-IN R15 R17 0 0 R57 22K R58 22K R13 4.7K/2.2K L8 L9 FERB FERB J7 1 2 3 4 5 C52 100P C53 100P
MIC2-IN MIC1-IN
Microphone In / Center-LFE Out
For ALC650:
R12=X R13=2.2K
For Automatic Jack Sensing Only
R45 10K C73 3.3u + R72 0@655 JD2
For ALC650:
JD Block=X
For ALC655 and ALC658 use Mono MIC:
R12=X R13=2.2K
R71
0@658
JD4
For ALC655:
R71=X R72=0
For ALC655 and ALC658 use Stereo MIC:
R12=4.7K R13=4.7K
JD Block
For ALC658:
R71=0 R72=X
LINE-IN-R LINE-IN-L
LINE-IN-R LINE-IN-L
R20 R21
0 0 R22 22K
L10 L11 R23 22K
FERB FERB
J10 1 2 3 4 5 C56 100P
C55 100P
Line In / Surround Out
For Automatic Jack Sensing Only
For ALC650:
R56 10K C72 3.3u + R74 0@655 JD1
JD Block=X
R73 0@658 JD3
For ALC655:
R73=X R74=0
JD Block
L13 L15 FERB FERB J13 1 2 3 4 5 C61 100P
For ALC658:
R73=0 R74=X
AUD-RET-R AUD-RET-L
AUD-RET-R AUD-RET-L R59 22K R60 22K
C60 100P
LINE Out (AMP-Out)
Analog I/O Connection
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SURR-OUT-R SURR-OUT-L
L1 L2
FERB FERB C2 100P C3 100P
J1 1 2 3 4 5
Back Panel Bracket
5
U3
TOTX178
N.C GND VCC N.C
Optical Transmitter
4
Surround Out
J3 1 2 3 4 5 1 2 3 C38 IN
LFE-OUT CENTER-OUT
L4 L5
FERB FERB C17 100P C18 100P
C32 0.1u
+5VDD
R5 100 SPDIF-OUT C40 100P 2 0.01u
Center/Lfe Out
J6
1
Only for ALC650/655/658
J2 1 3 5 7 9 2 4 6 8 10
S/PDIF OUTPUT (Coaxial)
SURR-OUT-R SPDIF-IN SURR-OUT-L AGND DGND SPDIF-IN DGND SURR-OUT-R AGND +3.3VDD +5VDD SPDIF-OUT SURR-OUT-L
R6 220
SPDIF-OUT
Bracket Connector
+3.3VDD +5VDD
TORX176/173 with ATC control is recommended
U4
TORX178/179 can be used without connecting RCA
U5
TORX176/173
5 CASE DGND AGND VCC
Optical Receiver
CASE OUT 6 4
TORX178
CASE DGND VCC CASE OUT
Optical Receiver
5
C33 10u +
C34 0.1u
C35 10u +
C36 0.1u
R11
10 SPDIF-IN
4
3
2
1
3
2
L6
47uH C48 0.1u
R14 2.2K C49 0.01u
+3.3VDD
+5VDD
L7
+5VDD
R16 10K R18 R19 10
47uH
J9
1
C51 C54 100P
0.01u
SPDIF-IN
S/PDIF INPUT
2
10K
Only for ALC650/655/658
Back Panel Bracket for Surround/CEN/LFE outputs and S/PDIF I/O
2003/07/31
1 C47 0.1u
37
Rev1.01
ALC655
FRONT-JACK2-ON +5VA C57 1u@Norm L12 L14 R24 10K
R50 10K@UAJ + C71 3.3u@UAJ
UAJ Block
FERB FERB C58 100P R31 C59 100P J12 1 2 3 4 5
AUD-MIC
R35 R25
0 10K
Front Panel Module
AUD-MIC AUD-MIC-BIAS AUD-OUT-R FRONT-JACK1-ON AUD-OUT-L J14 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 +5VA RET-R
+5VA
Front Panel MIC / UAJ2
UAJ2-IO-R UAJ2-IO-L
R53 R54 R52
0@655/658 22K@655/658 0@655/658 0@658
KEY
RET-L
VREFOUT2-UAJ2
UAJ Block
VREFOUT3-UAJ1 UAJ2-IO-R FRONT-JACK1-ON + R32 C66 3.3u L16 L17 FERB FERB C62 R30 22K@655/658 C65 RET-L C63 10K C64 100u/ 0ohm + J15 1 2 3 4 5
VREFOUT2-UAJ2 UAJ2-IO-L FRONT-JACK2-ON
Front Connector
1~10 pin connector: INTEL Front Panel I/O Design Guide V1.0 11~16 pin: REALTEK Front Panel I/O for UAJ
RET-R
AUD-OUT-R AUD-OUT-L R49 VREFOUT3-UAJ1 0@658
100P 100P
Front Panel Out / UAJ1
UAJ Block
100u/ 0ohm
R64 ALC655/658/650(with Intel Front Pannel)
0 0
R65
0 0
R32
X 10K
R66
X 3.3u
R30
X 22K
R31
X 22K
R24
4.7K X
R57
1u X
R35
0 X
R25
X X
R53
X 0
R54
X 0
UAJ Block
X ON
ALC658(with Realtek Front Pannel - UAJ function)
Front Panel Connection
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ALC655
11. Mechanical Dimensions
L L1
SYMBOL
A A1 A2 C D D1 D2 E E1 E2 b e TH L L1
MILLIMETER MIN. TYPICAL MAX. 1.60 0.05 0.15 1.35 1.40 1.45 0.09 0.20 9.00 BSC 7.00 BSC 5.50 9.00 BSC 7.00BSC 5.50 0.17 0.20 0.27 0.50 BSC 0o 3.5o 7o 0.45 0.60 0.75 1.00
INCH MIN. TYPICAL MAX 0.063 0.002 0.006 0.053 0.055 0.057 0.004 0.008 0.354 BSC 0.276 BSC 0.217 0.354 BSC 0.276 BSC 0.217 0.007 0.008 0.011 0.016 BSC 0o 3.5o 7o 0.018 0.0236 0.030 0.0393
TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm LEADFRAME MATERIAL APPROVE DOC. NO. VERSION 02 CHECK DWG NO. PKGC-065 DATE REALTEK SEMICONDUCTOR CORP.
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Rev1.01
ALC655
Realtek Semiconductor Corp.
Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw
2003/07/31
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Rev1.01

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