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24C01SC/02SC
1K/2K 5.0V I2CTM Serial EEPROMs for Smart Cards
FEATURES
* ISO Standard 7816 pad locations * Low power CMOS technology - 1 mA active current typical - 10 A standby current typical at 5.5V * Organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8) * 2-wire serial interface bus, I2CTM compatible * 100 kHz and 400 kHz compatibility * Self-timed write cycle (including auto-erase) * Page-write buffer for up to 8 bytes * 2 ms typical write cycle time for page-write * ESD protection > 4 kV * 1,000,000 E/W cycles guaranteed * Data retention > 200 years * Available for extended temperature ranges - Commercial (C): 0C to +70C
DIE LAYOUT
VSS VCC
SDA DC SCL
BLOCK DIAGRAM
HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24C01SC and 24C02SC are 1K-bit and 2K-bit Electrically Erasable PROMs with bondpad positions optimized for smart card applications. The devices are organized as a single block of 128 x 8-bit or 256 x 8-bit memory with a two-wire serial interface. The 24C01SC and 24C02SC also have page-write capability for up to 8 bytes of data.
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
SDA SCL
YDEC
VCC VSS
SENSE AMP R/W CONTROL
I2C is a trademark of Philips Corporation.
(c) 1998 Microchip Technology Inc.
DS21170C-page 1
24C01SC/02SC
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name VSS SDA SCL VCC DC
PAD FUNCTION TABLE
Function Ground Serial Address/Data I/O Serial Clock +4.5V to 5.5V Power Supply Don't connect
VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0V Storage temperature ..................................... -65C to +150C Ambient temp. with power applied................. -65C to +125C ESD protection on all pads............................................. 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +4.5V to +5.5V Parameter Symbol Min. Commercial (C): Tamb = Max. Units -- V V V A A pF mA mA A 0C to +70C
Conditions
VIH .7 VCC -- VIL -- .3 VCC .05 VCC -- VHYS VOL -- .40 ILI -10 10 ILO -10 10 CIN, -- 10 COUT Operating current ICC Write -- 3 ICC Read -- 1 Standby current ICCS -- 100 Note: This parameter is periodically sampled and not 100% tested.
SCL and SDA pads: High level input voltage Low level input voltage Hysteresis of Schmidt trigger inputs Low level output voltage Input leakage current (SCL) Output leakage current (SDA) Pin capacitance (all inputs/outputs)
(Note) IOL = 3.0 mA, VCC = 4.5V VIN = .1V to 5.5V VOUT = .1V to 5.5V VCC = 5.0V (Note 1) Tamb = 25C, FCLK = 1 MHz VCC = 5.5V Vcc = 5.5V, SCL = 400 KHz VCC = 5.5V, SDA = SCL = VCC
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL TSU:STA SDA THD:STA TSU:STO
START
STOP
DS21170C-page 2
(c) 1998 Microchip Technology Inc.
24C01SC/02SC
TABLE 1-3: AC CHARACTERISTICS
Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Symbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Min. -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max. 400 -- -- 300 300 -- -- -- -- -- 900 -- Units kHz ns ns ns ns ns ns ns ns ns ns ns Remarks
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance
TOF TSP TWR --
20 +0.1 CB -- -- 1M
250 50 10 --
ns ns ms cycles
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) Byte or Page mode 25C, Vcc = 5V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW TR
SCL TSU:STA SDA IN THD:STA TSP TAA SDA OUT THD:STA THD:DAT TSU:DAT TSU:STO
TAA
TBUF
(c) 1998 Microchip Technology Inc.
DS21170C-page 3
24C01SC/02SC
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24C01SC/02SC supports a bi-directional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C01SC/02SC works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24C01SC/02SC does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
FIGURE 3-1:
(A) SCL (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
DS21170C-page 4
(c) 1998 Microchip Technology Inc.
24C01SC/02SC
3.6 Slave Address
4.0
4.1
WRITE OPERATION
Byte Write
After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01SC/02SC, followed by three don't care bits. The eighth bit of slave address determines if the master device wants to read or write to the 24C01SC/02SC (Figure 3-2). The 24C01SC/02SC monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true, and it is not in a programming mode. Operation Read Write Control Code 1010 1010 Chip Select XXX XXX R/W 1 0
FIGURE 3-2:
START
CONTROL BYTE ALLOCATION
READ/WRITE
Following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit, which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01SC/02SC. After receiving another acknowledge signal from the 24C01SC/02SC, the master device will transmit the data word to be written into the addressed memory location. The 24C01SC/02SC acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C01SC/02SC will not generate acknowledge signals (Figure 4-1).
4.2
Page Write
SLAVE ADDRESS
R/W
A
1
0
1
0
X
X
X
X = Don't care
The write control byte, word address, and the first data byte are transmitted to the 24C01SC/02SC in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to eight data bytes to the 24C01SC/02SC, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2).
FIGURE 4-1:
BUS ACTIVITY MASTER
BYTE WRITE
S T A R T CONTROL BYTE WORD ADDRESS DATA S T O P
SDA LINE
S
A C K A C K A C K
P
BUS ACTIVITY
FIGURE 4-2:
PAGE WRITE
S T A R T CONTROL BYTE WORD ADDRESS (n) DATA n DATAn + 1 DATAn + 7 S T O P
BUS ACTIVITY MASTER
SDA LINE
S
A C K A C K A C K A C K A C K
P
BUS ACTIVITY
(c) 1998 Microchip Technology Inc.
DS21170C-page 5
24C01SC/02SC
5.0 ACKNOWLEDGE POLLING 6.0 READ OPERATION
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then NO ACK will be returned. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.
6.1
Current Address Read
FIGURE 5-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The 24C01SC/02SC contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C01SC/02SC issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01SC/02SC discontinues transmission (Figure 6-1).
6.2
Send Stop Condition to Initiate Write Cycle
Random Read
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C01SC/02SC as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then, the master issues the control byte again but with the R/W bit set to a one. The 24C01SC/02SC will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01SC/02SC discontinues transmission (Figure 6-2).
DS21170C-page 6
(c) 1998 Microchip Technology Inc.
24C01SC/02SC
6.3 Sequential Read 6.4 Noise Protection
Sequential reads are initiated in the same way as a random read except that after the 24C01SC/02SC transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24C01SC/02SC to transmit the next sequentially addressed 8-bit word (Figure 6-3). To provide sequential reads the 24C01SC/02SC contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The 24C01SC/02SC employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
FIGURE 6-1:
CURRENT ADDRESS READ
S T A R T CONTROL BYTE S T O P
BUS ACTIVITY MASTER
DATA n
SDA LINE
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 6-2:
RANDOM READ
S T T CONTROL BYTE WORD ADDRESS (n) S T A R T CONTROL BYTE S T O P
BUS ACTIVITY A MASTER R
SDA LINE
DATA n
S
A C K A C K
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 6-3:
SEQUENTIAL READ
CONTROL BYTE
DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P
BUS ACTIVITY MASTER
SDA LINE
P
A C K A C K A C K A C K N O A C K
BUS ACTIVITY
(c) 1998 Microchip Technology Inc.
DS21170C-page 7
24C01SC/02SC
7.0
7.1
PAD DESCRIPTIONS
SDA Serial Address/Data Input/Output
8.0
DIE CHARACTERISTICS
This is a bi-directional pad used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10K for 100 kHz, 2 K for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
Figure 8-1 shows the die layout of the 24C01SC/02SC, including bondpad positions. Table 8-1 shows the actual coordinates of the bondpad midpoints with respect to the center of the die.
FIGURE 8-1:
DIP
VSS
DIE LAYOUT
VCC
7.2
SCL Serial Clock
SDA DC SCL
This input is used to synchronize the data transfer from and to the device.
7.3
DC Don't Connect
TABLE 8-1:
Pad Name
BONDPAD COORDINATES
Pad Midpoint, X dir. Pad Midpoint, Y dir.
This pad is used for test purposes and should not be bonded out. It is pulled down to VSS through an internal resistor.
-495.000 749.130 VSS SDA -605.875 -271.875 SCL 479.875 -746.625 VCC 605.875 -261.375 Note 1: Dimensions are in microns. 2: Center of die is at the 0,0 point.
DS21170C-page 8
(c) 1998 Microchip Technology Inc.
24C01SC/02SC
NOTES:
(c) 1998 Microchip Technology Inc.
DS21170C-page 9
24C01SC/02SC
NOTES:
DS21170C-page 10
(c) 1998 Microchip Technology Inc.
24C01SC/02SC
24C01SC/02SC Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices.
24C01SC/02SC
--
/S Die Thickness Blank = 11 mils 08 = 8 mils Other die thicknesses available, please consult factory. S = Die in Wafer Pak W = Wafer WF = Sawed Wafer on Frame Blank = 0C to +70C
Package:
Temperature Range: Device:
24C01SC 24C02SC
1K 12C ISO Smart Card die 2K 12C ISO Smart Card die
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com)
(c) 1998 Microchip Technology Inc.
DS21170C-page 11
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
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AMERICAS (continued)
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Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 7/98
Printed on recycled paper.
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DS21170C-page 12
(c) 1998 Microchip Technology Inc.

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