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| (R) ISO2-CMOS ST-BUSTM FAMILY MT9174 Digital Network Interface Circuit with Receive Sync Marker Bit Features * * * * * * * * * * Receive sync output pulse Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate Adaptive echo cancellation Up to 4 km loop reach ISDN compatible (2B+D) data format Transparent modem capability Frame synchronization and clock extraction MITEL ST-BUS compatible Low power (typically 50 mW), single 5V supply ISSUE 1 May 1995 Ordering Information MT9174AE MT9174AN MT9174AP 24 Pin Plastic DIP 24 Pin SSOP 28 Pin PLCC -40C to +85C Description The MT9174 is identical to the MT9172 in all respects except for the addition of one feature. The MT9174 includes a digital output pin indicating the temporal position of the "SYNC" bit of the biphase transmission. This feature is especially useful for systems such as PCS wireless base stations applications requiring close synchronization between microcells. The MT9174 is fabricated in Mitel's ISO2-CMOS process. Applications * * * * * TDD Digital PCS (DECT, CT2, PHS) base stations requiring cell synchronization Digital subscriber lines High speed data transmission over twisted wires Digital PABX line cards and telephone sets 80 or 160 kbit/s single chip modem DSTi/Di CDSTi/ CDi Transmit Interface Prescrambler Scrambler Differentially Encoded Biphase Transmitter Transmit Filter & Line Driver LOUT F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 RegC Control Register Transmit Timing V Bias Address Echo Canceller Error Signal Echo Estimate -- DPLL MUX LOUT DIS Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Detect Status Receive Precan + Receive Filter -1 +2 LIN OSC2 DSTo/Do CDSTo/ CDo RxSB Receive Interface DePrescrambler Descrambler Differentially Encoded Biphase Receiver OSC1 VDD VSS VBias VRef Figure 1 - Functional Block Diagram 9-155 MT9174 Advance Information 24 PIN PDIP/ SSOP Figure 2 - Pin Connections Pin Description Pin # Name 24 1 2 3 4,5, 6 7 8 28 2 3 4 5,7, 8 9 11 LOUT VBias VRef Line Out. Transmit Signal output (Analog). Referenced to VBias. Internal Bias Voltage output. Connect via 0.33 F decoupling capacitor to VDD. Internal Reference Voltage output. Connect via 0.33 F decoupling capacitor to VDD. Description MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various operating modes for a particular application. See Table 1 for the operating modes. RegC RxSB Regulator Control output (Digital). A 512 kHz clock used for switch mode power supplies. Unused in MAS/MOD mode and should be left open circuit. Receive Sync Bit output (Digital). This output is held high until receive synchronization occurs (i.e., until the sync bit in Status Register =1). Once low, indicating synchronized transmission, a high going pulse (6.24 s wide pulse @ 160 kb/s and 12.5 s wide @ 80 kb/s) indicates the temporal position of the receive "SYNC" bit in the biphase line transmission. Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the start of the C-channel. Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. Negative Power Supply (0V). Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 9 10 F0/CLD 10 12 CDSTi/ CDi CDSTo/ CDo VSS DSTo/Do DSTi/Di 11 13 12 13 14 14 15 16 9-156 CDSTi/CDi CDSTo/CDo VSS DSTo/Do DSTi/Di F0o/RCK NC LOUT VBias VRef MS2 MS1 MS0 RegC RxSB F0/CLD CDSTi/CDi CDSTo/CDo VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD LIN TEST LOUT DIS Precan OSC1 NC OSC2 C4/TCK F0o/RCK DSTi/Di DSTo/Do 4 3 2 1 28 27 26 * VRef VBias LOUT NC VDD LIN TEST 12 13 14 15 16 17 18 MS2 NC MS1 MS0 RegC F0/CLD RxSB 5 6 7 8 9 10 11 25 24 23 22 21 20 19 NC LOUT DIS Precan OSC1 OSC2 NC C4/TCK 28 PIN PLCC Advance Information Pin Description (continued) Pin # Name 24 15 28 17 Description MT9174 F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system. C4/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system. Oscillator Output. CMOS Output. Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical Characteristics for OSC1 input requirements. Precanceller Disable. When held to Logic '1', the internal path from LOUT to the precanceller is forced to VBias thus bypassing the precanceller section. When logic '0', the LOUT to the precanceller path is enabled and functions normally. An internal pulldown (50 k) is provided on this pin. No Connection. Leave open circuit 16 19 17 19 20 21 22 23 OSC2 OSC1 Precan 18 1,6, 18, 20, 25 24 26 27 28 NC 21 22 23 24 LOUT DIS TEST LIN VDD LOUT Disable. When held to logic "1", LOUT is disabled (i.e., output = VBias). When logic "0", LOUT functions normally. An internal pulldown (50 k) is provided on this pin. Test Pin. Connect to VSS. Receive Signal input (Analog). Positive Power Supply (+5V) input. 9-157 MT9174 NOTES: Advance Information 9-158 |
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