View HMD4M36M3EG_446796.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HANBit
HMD4M36M3EG
16Mbyte(4Mx36) 72-pin SIMM EDO with Parity MODE, 4K Ref. 5V Part No. HMD4M36M3E, HMD4M36M3EG
GENERAL DESCRIPTION
The HMD4M36M3E is a 4M x 36 bit dynamic RAM high-density memory module. The module consists of two CMOS 4M x 16 bit DRAMs in 50-pin TSOP packages and one CMOS 4M x 4bit Quad CAS DRAM in 28pin SOJ package mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line memory module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply. All inputs and outputs are TTLcompatible.
FEATURES
w Part Identification HMD4M36M3E----4K Cycles/64ms Ref, Solder HMD4M36M3EG- 4K Cycles/64ms Ref, Gold w Access times : 50, 60ns w High-density 16MByte design w Single +5V 0.5V power supply wJEDEC standard pinout w EDO Mode operation w TTL compatible inputs and outputs w FR4-PCB design PIN 1 2 3 4 5 6 7 8 9 10 11 12 -5 -6 M 13 14 15 16 17 60ns Vss NC NC NC 18 19 20 PD2 PD3 PD4 NC Vss Vss 21 22 23 24 tRC 90ns 110ns tHPC 26ns 30ns
PIN ASSIGNMENT
SYMBOL Vss DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 NC NC DQ26 DQ8 DQ17 DQ35 Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 NC NC /WE NC PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
PRESENCE DETECT PINS
Pin PD1 50ns Vss
PERFORMANCE RANGE
Speed 5 6 tRAC 50ns 60ns tCAC 13ns 15ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
1
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
HMD4M36M3EG
U1
/RAS0
/RAS
/CAS0
/LCAS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ0-DQ7
/CAS1
/UCAS
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A11 DQ16
/OE
DQ9-DQ16
/W
/RAS /CAS0 /CAS1 /CAS2 /CAS3 /W
U2
DQ0 DQ1 DQ2 DQ3
DQ8 DQ17 DQ26 DQ35
A0-A11
U3
/RAS
/CAS2
/LCAS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ18-DQ25
/CAS3
/UCAS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 A0-A11 DQ15
/OE
DQ27-DQ34
W
/WE A0-A11
Vcc
0.1uFor0.22uFCapacitor foreachDRAM To all DRAMs
Vss
URL:www.hbe.co.kr REV.1.0 (August.2002)
2
HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD4M36M3EG
RATING -1V to 7.0V -1V to 7.0V 3W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 -6 ICC2 -5 ICC3 -6 -5 ICC4 -6 ICC5 -5 ICC6 -6 Il(L) IO(L) VOH VOL ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min )
URL:www.hbe.co.kr REV.1.0 (August.2002)
SPEED -5
MIN -40 -5 2.4 -
MAX 990 900 18 990 900 990 900 9 990 900 45 5 0.4
UNITS mA mA mA mA mA mA mA mA mA mA A A V V
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)
3
HANBit Electronics Co.,Ltd.
HANBit
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA )
HMD4M36M3EG
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
DESCRIPTION Input Capacitance (A0-A10) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
MIN -
MAX 65 80 50 40 20
UNITS pF pF pF pF pF
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 110 50 13 25 3 3 2 30 50 13 38 8 20 15 5 0 10 10K 37 25 10K 13 50 3 3 2 40 60 15 45 10 20 15 5 0 10 10K 45 30 10K 15 50 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 90
STANDARD OPERATION Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time
URL:www.hbe.co.kr REV.1.0 (August.2002)
SYMBOL tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH
4
HANBit Electronics Co.,Ltd.
HANBit
Column address set-up time Column address hold time Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced to /RAS Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) /CAS precharge(C-B-R counter test) tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tREF tWCS tCSR tCHR tRPC tCPA tPC tCP tRASP tWRP tWRH tCPT 40 8 50 10 10 20 0 5 10 5 0 8 25 0 0 0 10 50 10 13 8 0 8 50
HMD4M36M3EG
0 10 30 0 0 0 10 50 10 15 10 0 10 50 64 0 5 10 5 30 40 10 200K 60 10 10 20 200K 35 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES 1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5.Assumes that tRCD tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbe.co.kr REV.1.0 (August.2002)
5
HANBit Electronics Co.,Ltd.
HANBit
PACKAGING INFORMATION
HMD4M36M3EG
107.95 mm 101.19 mm 3.38 mm R1.57 mm 3.18 0.51
18.52mm 10.16 mm 6.35 mm 2.03mm 6.35mm 6.35 mm 95.25 mm R1.5710 mm
5.08mm MAX
0.25 mm MAX
2.54 mm MIN
Gold : 1.040.10 mm 1.27mm Solder:0.9140.10mm 1.290.08 mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
Vcc
SPEED
HMD4M36M3EG-5 HMD4M36M3EG-6
16MByte 16MByte
4MX 36bit 4MX 36bit
72 Pin-SIMM 72 Pin-SIMM
5.0V 5.0V
50ns 60ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
6
HANBit Electronics Co.,Ltd.

▲Up To Search▲

Price & Availability of HMD4M36M3EG

	To Download HMD4M36M3EG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .