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HI1386
August 1997
8-Bit, 75 MSPS, Flash A/D Converter
Description
The HI1386 is an 8-bit, high-speed flash analog-to-digital converter IC capable of digitizing analog signals at a maximum rate of 75 MSPS. The digital I/O levels of this A/D converter are compatible with ECL 100K/10KH/10K. The HI1386 is available in the commercial and industrial temperature range and is supplied in 28 lead plastic DIP and 44 lead ceramic LCC packages.
Features
* Differential Linearity Error 0.5 LSB or Less * Integral Linearity Error 0.5 LSB or Less * Built-In Integral Linearity Compensation Circuit * High-Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MSPS * Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 17pF * Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 150MHz * Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . -5.2V * Low Power Consumption (Typ) . . . . . . . . . . . . .580mW * Low Error Rate * Operable at 50% Clock Duty Cycle * Capable of Driving 50 Loads * Direct Replacement for CXA1386
Ordering Information
PART NUMBER HI1386JCP HI1386AIL TEMP. RANGE (oC) -20 to 75 -20 to 100 PACKAGE 28 Ld PDIP 44 Ld CLCC PKG. NO. E28.6A-S J44.B
Applications
* Video Digitizing * RGB Graphics Processing * HDTV (High Definition TV) * Radar Systems * Communication Systems * Direct RF Down-Conversion * Digital Oscilloscopes
Pinouts
HI1386 (PDIP) TOP VIEW
DGND2 DGND1
HI1386 (CLCC) TOP VIEW
DVEE AVEE AVEE AVEE 39 NC 38 NC 37 AGND 36 VIN 35 AGND 34 VRM 33 AGND 32 VIN 31 AGND 30 NC 29 NC 18 19 20 21 22 23 24 25 26 27 28 DVEE VRB AVEE DGND1 MINV AVEE CLK NC NC CLK NC LINV VRT NC NC NC
LINV 1 DVEE 2 DGND 3 (LSB) D0 4 D1 5 D2 6 D3 7 D4 8 D5 9 D6 10 (MSB) D7 11 DGND 12 DVEE 13 MINV 14
28 AVEE 27 VRT 26 AVEE 25 AGND 24 VIN 23 AGND 22 VRM 21 AGND 20 VIN 19 AGND 18 AVEE 17 VRB 16 CLK 15 CLK
NC 7 (LSB) D0 8 D1 9 D2 10 D3 11 D4 12 D5 13 D6 14 (MSB) D7 15 DGND2 16 NC 17
6
5
4
3
2
1 44 43 42 41 40
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3583.4
4-1148
HI1386 Functional Block Diagram
MINV R1 VRT R/2 R 1 R D7 (MSB) 2 R D6 COMPARATOR
63 R VIN 64 R 65 OUTPUT D3 R 126 R R2 VRM R 128 R D0 (LSB) 129 127 ENCODE LOGIC D1 D2 D4 D5
R 191 R VIN 192 R 193
R 254 R 255 VRB CLK CLK R3 R/2
CLOCK DRIVER
LINV
4-1149
HI1386 Pin Descriptions
PIN NUMBER DIP 19, 21, 23, 25 LCC 31, 33, 35, 37 SYMBOL AGND I/O STANDARD VOLTAGE LEVEL 0V
EQUIVALENT CIRCUIT
DESCRIPTION Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND, DGND1, and DGND2. Analog VEE -5.2V (Typ). Internally connected to DVEE (Resistance: 4 to 6). Bypass with 0.1F to AGND. CLK Input.
18, 26, 28
27, 28, 40, 41, 44
AVEE
-
-5.2V
16 15
23 22
CLK CLK
I
ECL
DGND, DGND1
R R CLK CLK R
R
Input Complementary to CLK. When open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation.
DVEE
R
R
3, 12
-
DGND
-
0V
Digital GND (used for internal circuits and output transistors). Digital GND (used for internal circuits and output transistors). Digital GND (used for output buffers). Digital VEE . Internally connected to AVEE (resistance: 4 to 6). Bypass with 0.1F to DGND LSB of Data Outputs. External pull-down resistor is required. Data Outputs. External pull-down resistors are required.
D1
-
5, 19
DGND1
-
0V
-
6, 16
DGND2
-
0V
2, 13
4, 20
DVEE
-
-5.2V
4
8
D0
O
ECL
DGND
5 6 7 8 9 10 11
9 10 11 12 13 14 15
D1 D2 D3 D4 D5 D6 D7
DVEE
MSB of Data Outputs. External pull-down resistor is required.
4-1150
HI1386 Pin Descriptions
PIN NUMBER DIP 1 LCC 3 SYMBOL LINV I/O I (Continued) STANDARD VOLTAGE LEVEL ECL
DGND, DGND1
EQUIVALENT CIRCUIT
DESCRIPTION Input Pin for D0 (LSB) to D6 Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open.
14
21
MINV
I
ECL
R R LINV OR MINV R -1.3V
Input Pin for D7 (MSB) Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open.
DVEE
R
20, 24
32, 36
VIN
I
VRT to VRB
AGND
VIN VIN
Analog Input Pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions.
AVEE
17
26
VRB
I
-2V
VRT R1 R/2
Reference Voltage (Bottom). Typically -2V. Bypass with a 0.1F and 10F to AGND.
R COMPARATOR 1 R
22
34
VRM
I
VRB/2
Reference Voltage Mid Point. Can be used as a pin for integral linearity compensation. Reference Voltage (Top) Typically 0V.
27
42
VRT
I
0V
R VRM R2 R
COMPARATOR 2
COMPARATOR 127 COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130
R COMPARATOR 255 VRB R3 R/2
4-1151
HI1386
Absolute Maximum Ratings TA = 25oC
Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA
Thermal Information
Thermal Resistance (Typical, Note 1) JAoC/W JCoC/W PDIP Package . . . . . . . . . . . . . . . . . . . 58 N/A CLCC Package . . . . . . . . . . . . . . . . . . 45 11 Maximum Junction Temperature CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Ranges (Note 4) PDIP Package (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CLCC Package (TC) . . . . . . . . . . . . . . . . . . . . . . . -20oC to100oC Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Pulse Width of Clock tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL DYNAMIC CHARACTERISTICS
TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT
fC = 75MHz fC = 75MHz -
8 0.3 0.3
0.5 0.5
Bits LSB LSB
Signal to Noise and Distortion Ratio, SINAD Input = 1MHz, Full Scale fC = 75MHz RMS Signal = ----------------------------------------------------------------RMS Noise + Distor tion Input = 18.75MHz, Full Scale fC = 75MHz Error Rate Differential Gain Error, DG Differential Phase Error, DP Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS ANALOG INPUT Input Bandwidth Analog Input Capacitance, CIN Analog Input Resistance, RIN Input Bias Current, IIN REFERENCE INPUTS Reference Resistance, RREF VIN = -1V VIN = 2VP-P (-3dB) VIN = 1V + 0.07VRMS Input = 18.749MHz, Full Scale Error > 16 LSB, fC = 75MHz NTSC 40 IRE Mod. Ramp, fC = 75 MSPS Error Rate of 10-9 TPS (Note 2)
75 -
46 40 1.0 0.5 10 3.0
10-9 -
dB dB TPS (Note 2) % Degree MSPS ps ns
150 -
17 390 -
200
MHz pF k A
75
110
155
4-1152
HI1386
Electrical Specifications
PARAMETER Offset Voltage EOT EOB DIGITAL INPUTS Logic H Level, VIH Logic L Level, VIL Logic H Current, IIH Logic L Current, IIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH Logic L Level, VOL TIMING CHARACTERISTICS H Pulse Width of Clock, tPW1 L Pulse Width of Clock, tPW0 Output Rise Time, tr Output Fall Time, tf Output Delay, tOD POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption, PD Note 3 -150 -104 580 mA mW RL = 620 to DVEE , 20% to 80% RL = 620 to DVEE , 20% to 80% 6.6 6.6 4.0 0.9 2.1 6.5 9.0 ns ns ns ns ns RL = 620 to DVEE RL = 620 to DVEE -1.03 -1.62 V V -0.8V is Applied to Input -1.6V is Applied to Input -1.13 0 -50 7 -1.50 50 50 V V A A pF VRT VRB 8 0 18 10 32 24 mV mV TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) TEST CONDITIONS MIN TYP MAX UNIT
NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 2 ( V RT- V RB ) 3. P D = I EE * V EE + -----------------------------------R REF 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed.
Timing Diagram
tDS ANALOG IN N N+1
N+2 tPW1 CLK CLK tPW0
DIGITAL OUT tOD
N-1
20%
80%
N
80%
N+1 20% tf
tr
FIGURE 1.
4-1153
HI1386
A/D OUTPUT CODE TABLE MINV 1 LINV 1 STEP D7 D0 D7 0 1 D0 D7 1 0 D0 D7 0 0 D0
VIN (NOTE 1) 0V
000 * * * * * 00 0 1 000 * * * * * 00 000 * * * * * 01 * * *
100 * * * * * 00 100 * * * * * 00 100 * * * * * 01 * * * 111 * * * * * 11 000 * * * * * 00 * * * 011 * * * * * 10 011 * * * * * 11 011 * * * * * 11
011 * * * * * 11 011 * * * * * 11 011 * * * * * 10 * * * 000 * * * * * 00 111 * * * * * 11 * * * 100 * * * * * 01 100 * * * * * 00 100 * * * * * 00
111 * * * * * 11 111 * * * * * 11 111 * * * * * 10 * * * 100 * * * * * 00 011 * * * * * 11 * * * 000 * * * * * 01 000 * * * * * 00 000 * * * * * 00
-1V
127 128
011 * * * * * 11 100 * * * * * 00 * * *
254 255 -2V NOTE: 5. VRT = 0V, VRB = -2V.
111 * * * * * 10 111 * * * * * 11 111 * * * * * 11
Test Circuits
SIGNAL SOURCE fCLK 4 -1kHz + ECL LATCH VIN 8 HI1386 CLK CLK ECL LATCH A B COMPARATOR A>B PULSE COUNTER
2VP-P SINEWAVE DATA 16 SIGNAL SOURCE fCLK fCLK/A
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
+V
S2 HI20201 VIN AMP NTSC SIGNAL SOURCE DUT HI1386 8 ECL LATCH 8 10-BIT D/A
+ S1
S1 : A < B : ON S2 : A > B : ON
CLK
CLK -V AB 8 DELAY COMPARATOR 8 A8 A1 A0 B8 B1 B0 BUFFER
SG (CW) 50 VBB
VECTOR SCOPE DG/DP
VIN
DUT HI1386
DVM "0" CLK (75MHz)
"1" 8 00000000 TO 11111110
CONTROLLER
FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT
FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT
4-1154
HI1386 Test Circuits
(Continued)
-1V A IIN IEE 1 2 3 4 5 6 7 HI1386JCP 8 9 10 11 12 13 14 21 20 19 18 17 16 15 -2V 28 27 26 25 24 23 22 A -5.2V
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35
-1V IIN A
HI1386AIL, CXA1386K
34 33 32 31 30 29
A IEE -5.2V
-2V
FIGURE 5A.
FIGURE 5B.
FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS
VIN
0V -1V -2V
37.5MHz AMP OSC1 : VARIABLE VIN fR CLK OSC2 37.5MHz ECL BUFFER HI1386 8 LOGIC ANALYZER 1024 SAMPLES CLK CLK
t VIN
t
129 128 127 126 125
(LSB)
APERTURE JITTER
Aperture jitter is defined as follows: 256 t AJ = ------ = --------- x 2f , 2 t Where (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 6A. FIGURE 6B. APERTURE JITTER TEST METHOD
FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT
4-1155
HI1386
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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