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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4017 Johnson decade counter with 10 decoded outputs
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
FEATURES * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4017 are high-speed Si-gate CMOS devices and are pin compatible with the "4017" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4017 are 5-stage Johnson decade counters with 10 decoded active HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0 and
74HC/HCT4017
CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see also function table). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi+ (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP0, CP1 to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 77 3.5 35 HCT 21 67 3.5 36 ns MHz pF pF UNIT
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
PIN DESCRIPTION PIN NO. 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 8 12 13 14 15 16 SYMBOL Q0 to Q9 GND Q5-9 CP1 CP0 MR VCC NAME AND FUNCTION decoded outputs ground (0 V) carry output (active LOW)
74HC/HCT4017
clock input (HIGH-to-LOW, edge-triggered) clock input (LOW-to-HIGH, edge-triggered) master reset input (active HIGH) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Fig.4 Functional diagram.
FUNCTION TABLE MR H L L L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition CP0 X H L X H CP1 X L X H L OPERATION Q0 = Q5-9 = H; Q1 to Q9 = L counter advances counter advances no change no change no change no change
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI
74HC/HCT4017
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay CP0 to Qn propagation delay CP0 to Q5-9 propagation delay CP1 to Qn propagation delay CP1 to Q5-9 propagation delay MR to Q1-9 propagation delay MR to Q5-9, Q0 output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH removal time MR to CP0, CP1 set-up time CP1 to CP0; CP0 to CP1 hold time CP0 to CP1; CP1 to CP0 maximum clock pulse frequency 80 16 14 80 16 14 5 5 5 50 10 9 50 10 9 6.0 30 25 typ. 63 23 18 63 23 18 61 22 18 61 22 18 52 19 15 55 20 16 19 7 6 17 6 5 19 7 6 -17 -6 -5 -8 -3 -2 17 6 5 23 70 83 -40 to+85 max. min. 230 46 39 230 46 39 250 50 43 250 50 43 230 46 39 230 46 39 75 15 13 100 20 17 100 20 17 5 5 5 65 13 11 65 13 11 4.8 24 28 max. 290 58 49 290 58 49 315 63 54 315 63 54 290 58 49 290 58 49 95 19 16 120 24 20 120 24 20 5 5 5 75 15 13 75 15 13 4.0 20 24 -40 to+125 min. max. 345 69 59 345 69 59 375 75 64 375 75 64 345 69 59 345 69 59 110 22 19 ns
74HC/HCT4017
TEST CONDITIONS UNIT VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.9
tPHL/ tPLH
ns
Fig.9
tPHL/ tPLH
ns
Fig.9
tPHL/ tPLH
ns
Fig.9
tPHL
ns
Fig.8
tPLH
ns
Fig.8
tTHL/ tTLH
ns
Fig.9
tW
ns
Fig.8
tW
ns
Fig.8
trem
ns
Fig.8
tsu
ns
Fig.7
th
ns
Fig.7
fmax
MHz
Fig.8
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI
74HC/HCT4017
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT CP1 CP0 MR UNIT LOAD COEFFICIENT 0.40 0.25 0.50
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25
min. typ. max.
74HC/HCT4017
TEST CONDITIONS UNIT VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS
-40 to+85
min. max.
-40 to+125
min. max.
tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL tPLH tTHL/ tTLH tW tW trem tsu
propagation delay CP0 to Qn propagation delay CP0 to Q5-9 propagation delay CP1 to Qn propagation delay CP1 to Q5-9 propagation delay MR to Q1-9 propagation delay MR to Q5-9, Q0 output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH removal time MR to CP0, CP1 set-up time CP1 to CP0; CP0 to CP1 hold time CP0 to CP1; CP1 to CP0 16 16 5 10
25 25 25 25 22 20 7 7 4 -5 -3
46 46 50 50 46 46 15 20 20 5 13
58 58 63 63 58 58 19 24 24 5 15
69 69 75 75 69 69 22
ns ns ns ns ns ns ns ns ns ns ns
Fig.9 Fig.9 Fig.9 Fig.9 Fig.8 Fig.8 Fig.9 Fig.8 Fig.8 Fig.8 Fig.7
th
10
6
13
15
ns
4.5
Fig.7
fmax
maximum clock pulse 30 frequency
61
24
20
ns
4.5
Fig.8
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
AC WAVEFORMS
74HC/HCT4017
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the hold and set-up times for CP0 to CP1 and CP1 to CP0.
Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW transition. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the minimum pulse widths for CP0, CP1 and MR inputs; the recovery time for MR and the propagation delays for MR to Qn and Q5-9 outputs.
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW transition. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition times.
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
APPLICATION INFORMATION Some applications for the "4017" are: * Decade counter with decimal decoding * 1 out of n decoding counter (when cascaded) * Sequential controller * Timer
74HC/HCT4017
Figure 10 shows a technique for extending the number of decoded output states for the "4017". Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, as this would cause an extra count.
Fig.10 Counter expansion
Figure 11 shows an example of a divide-by 2 through divide-by 10 circuit using one "4017". Since "4017" has an asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths can be enlarged by inserting a RC network at the MR input.
Fig.11 Divide-by 2 through divide-by 10.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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