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| Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 History Initial Draft Draft Date Jun. 2004 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / June. 2004 1 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM DESCRIPTION The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32. HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES * * * * * * Voltage : VDD, VDDQ 3.3V All device pins are compatible with LVTTL interface 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 * Internal four banks operation * Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks * * * Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst ORDERING INFORMATION Part No. HY5V52(L)F-H HY5V52(L)F-P HY5V52(L)F-S HY5V52(L)FP-H HY5V52(L)FP-P HY5V52(L)FP-S Clock Frequency 133MHz 100MHz 100MHz 133MHz 100MHz 100MHz CAS Latency 3 2 3 3 2 3 4Banks x 2Mbits x32 LVTTL Lead Free Leaded Organization Interface 90 Ball FBGA Note 1. HY5V52F Series : Normal power 2. HY5V52LF Series : Low Power 3. HY5V52xF Series : Leaded 90Ball FBGA 4. HY5V52xFP Series : Lead Free 90Ball FBGA This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / June. 2004 2 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Ball CONFIGURATION 1 A B C D E F G H J K L M N P R DQ26 2 DQ24 3 VSS 4 5 6 7 VDD 8 DQ23 9 DQ21 DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ VDDQ DQ31 NC NC DQ16 VSSQ VSS DQM3 A3 A2 DQM2 VDD A4 A5 A6 A7 A8 NC TOP View A10 A0 A1 NC BA1 A11 CLK CKE A9 BA0 /CS /RAS DQM1 NC NC /CAS /WE DQM0 VDDQ DQS VSS VDD DQ7 VSSQ VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 DQ13 DQ15 VSS VDD DQ0 DQ2 Rev. 0.1 / June. 2004 3 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Ball FUNCTION DESCRIPTIONS SYMBOL CLK CKE CS BA0, BA1 A0 ~ A11 Ball NAME Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output No Connection TYPE INPUT INPUT INPUT INPUT INPUT DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS, WE INPUT RAS, CAS and WE define the operation Refer function truth table for details DQM0~3 DQ0 ~ DQ31 NC I/O SUPPLY - Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin No Connection Rev. 0.1 / June. 2004 4 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 32 I/O Synchronous DRAM Self refresh logic & timer Internal Row Counter CLK CKE CS RAS CAS WE DQM0 DQM1 DQM2 DQM3 2Mx32 BANK 3 Row Active State Machine Row Pre Decoder 2Mx32 BANK 2 2Mx32 BANK 1 2Mx32 BANK 0 X-Decoder X-Decoder X-Decoder DQ0 Sense AMP & I/O Gate X-Decoder I/O Buffer & Logic Refresh Memory Cell Array Column Active Column Pre Decoder Y-Decoder DQ31 Bank Select Column Add Counter A0 A1 Address Register Burst Counter Pipe Line Control Address Buffers A11 BA1 BA0 Mode Register CAS Latency Data Out Control Rev. 0.1 / June. 2004 5 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0 OP Code A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write Burst Type A3 0 1 Burst Type Sequential Interleave CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved Rev. 0.1 / June. 2004 6 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM ABSOLUTE MAXIMUM RATING Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time Symbol TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER Rating 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 . 10 Unit oC oC V V V mA W oC . Sec DC OPERATING CONDITION (TA= 0 to 70oC ) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.3 Max 3.6 VDDQ+0.3 0.8 Unit V V V Note 1 1, 2 1, 3 - Note : 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=3.30.3V, VSS=0V) Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF Note 1 Rev. 0.1 / June. 2004 7 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM CAPACITANCE Parameter CLK Input capacitance A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 DQ0 ~ DQ31 (TA= 0 to 70 oC, f=1MHz, VDD=3.3V) Pin Symbol CI1 CI2 CI/O Min 2.0 2.0 3.5 Max 4.0 4.0 6.5 Unit pF pF pF Data input / output capacitance Note 1. Vtt=1.4V Vtt=1.4V RT=500 RT=50 Output 30pF Output Z0 = 50 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERRISTICS I (TA= 0 to 70oC) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note : 1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6 Symbol ILI ILO VOH VOL Min -1 -1 2.4 - Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -2mA IOL = +2mA Rev. 0.1 / June. 2004 8 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM DC CHARACTERISTICS II (TA= 0 to 70oC) Parameter Symbol Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRC tRC(min), All banks active Normal Speed H 120 2 1 P 110 S Uni Not t e mA mA mA 1 Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS Precharge Standby Current in Non Power Down Mode IDD2N 15 mA 15 5 5 IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS mA Active Standby Current in Non Power Down Mode IDD3N 30 mA 20 IDD3NS Burst Mode Operating Current Auto Refresh Current CL=3 CL=2 150 160 220 3 130 mA 140 mA 2 1 IDD4 IDD5 Self Refresh Current IDD6 CKE 0.2V Low Power mA 1.5 3 Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY5V52F(P) Series : Normal, HY5V52LF(P) Series : Low Power Rev. 0.1 / June. 2004 9 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Parameter System ClockCycle Time CAS Latency=3 CAS Latency=2 Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency=3 CAS Latency=2 Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High- CAS Latency=3 Z Time CAS Latency=2 Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Symbol tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 H Min 7.5 10 2.5 2.5 2.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 2.0 2.0 Max 1000 5.4 6 5.4 6.0 Min 10 10 3.0 3.0 2.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 2.0 2.0 P Max 1000 6 6 6.0 6.0 Min 10 12 3.0 3.0 2.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 2.0 2.0 S Max 1000 6 6 6.0 6.0 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 2 Rev. 0.1 / June. 2004 10 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter RAS Cycle Time RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z Power Down Exit Time Self Refresh Exit Time Refresh Time Note : 1. A new command can be given tRC after self refresh exit. Symbol tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD H P S Min Max Min Max Min Max 65 65 20 45 20 15 1 0 2 100K 70 70 20 50 20 20 1 0 2 100K 70 70 20 50 20 20 1 0 2 100K - Unit Note ns ns ns ns ns ns CLK CLK CLK Operation Auto Refresh tDPL + tRP 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1 CAS Latency=3 CAS Latency=2 tPROZ3 tPROZ2 tDPE tSRE tREF Rev. 0.1 / June. 2004 11 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM COMMAND TRUTH TABLE Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit CKEn-1 H H H H CKEn X X X X CS L H L L L RAS L X H L H CAS L X H H L WE L X H H H DQM X X X X CA RA L H L H H L X X X A9 ball High (Other balls OP code) MRS Mode ADDR A10/AP OP code X BA Note V V H X L H L L X CA V X V H H H H H H L X X L L L H X H H L L X X V X H X L H L L L H L H L H L H L L L L X H X H X H X V X L L L X H X H X H X V H L H X H X H X H X V X X X X X Entry Precharge power down Exit H L X X X L H Clock Suspend Entry Exit H L L H X X X Rev. 0.1 / June. 2004 12 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM PACKAGE INFORMATION 90 Ball 0.8mm pitch, 11mm x 13mm FBGA Unit [mm] 11.0 2.30 0.10 6.40 BSC 0.80( Typ) A1 INDEX MARK 0.80( Typ) 0.450 0.05 11.20 BSC 13.0 0.10 Bottom View 6.50 0.05 3.20 0.05 5.50 0.05 0.340 0.05 1.20 max Rev. 0.1 / June. 2004 13 |
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