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ACT-F1M32 High Speed 32 Megabit Boot Block FLASH Multichip Module
Features
www.aeroflex.com/act1.htm s s s s s
CIRCUIT TECHNOLOGY
s 4 Low Voltage/Power Intel 1M x 8 FLASH Die in One
MCM Package s Overall Configuration is 1M x 32 s +5V Operation (Standard) or +3.3V (Consult Factory) s Access Times of 80, 100 and 120 nS ( 5V VCC) s +5V or +12V Programing s Erase/Program Cycles q 100,000 Commercial q 10,000 Military and Industrial s Sector Architecture (Each Die) q One 16K Protected Boot Block (Bottom Boot Block Standard, Top Boot Block Special Order) q Two 8K Parameter Blocks q One 96K Main Block q Seven 128K Main Blocks
Single Block Erase (All bits set to 1) Hardware Data Protection Feature Independent Boot Block Locking MIL-PRF-38534 Compliant MCMs Available Packaging - Hermetic Ceramic q 68 Lead, .94" x .94" x .180" Dual-Cavity Small Outline Gull Wing, Aeroflex code# "F14" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) s Internal Decoupling Capacitors for Low Noise Operation s Commercial, Industrial and Military Temperature Ranges
Block Diagram - CQFP(F14)
Standard Configuration CE1 WP WE OE A0 - A19 RP 1Mx8 1Mx8 1Mx8 1Mx8 CE2 CE3
Pin Description I/O0-31 CE4 A0-19 WE CE1-4 OE WP RP VCC Data I/O Address Inputs Write Enables Chip Enables Output Enable Write Protect Reset/Powerdown Power Supply Ground Not Connected
General Description
Utilizing Intel's SmartVoltage Boot Block Flash Memory SmartDieTM, the ACT-F1M32 is a high speed, 32 megabit CMOS flash multichip module (MCM) designed for full temperature range military, space, or high reliability applications. The ACT-F1M32 consists of four high-performance Intel X28F800BV 8 Mbit (8,388,608 bit) memory die. Each die contains separately erasable blocks, including a hardware lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each), and 8 main blocks (one block of 98,304 bytes and seven blocks of 131,072 bytes) This defines the boot block flash family architecture. The command register is written by bringing WE to a logic low level (VIL), while CE is low and OE is high (VIH). Reading is
8 I/O0-7
8 I/O8-15
8 I/O16-23
8 I/O24-31
GND NC
Block Diagram - CQFP(F14)
Optional Configuration WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4 RP OE A0 - A19 Pin Description I/O0-31 A0-19 WE1-4 CE1-4 OE 1Mx8 1Mx8 1Mx8 1Mx8 RP VCC 8 I/O0-7 8 I/O8-15 8 I/O16-23 8 I/O24-31 GND NC Data I/O Address Inputs Write Enable Chip Enables Output Enable Reset/Powerdown Power Supply Ground Not Connected
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General Description, Cont'd,
accomplished by chip Enable (CE) and Output Enable (OE) being logically active. Access time grades of 80nS, 100nS and 120nS maximum are standard. The ACT-F1M32 is packaged in a hermetically sealed co-fired ceramic 68 lead, .94" SQ Ceramic Gull Wing CQFP package. This allows operation in a military environment temperature range of -55C to +125C. The ACT-F1M32 provides program and erase capability at 5V or 12V and allows reads with Vcc at 5V or 3.3V(Not tested). Since many designs read from flash memory a large percentage of the time, read operation using 3.3V can provide great power savings. Consult the factory for 3.3V tested parts. In applications where read performance is critical, faster access times are obtainable with the 5V VCC part detailed herein. For program and erase operations, 5V Vpp operation eliminates the need for in system voltage converters. The 12V Vpp operation provides reduced (approx 60%) program and erase times where 12V is available in the system. For design simplicity, however, connect Vcc and Vpp to the same 5V 10% source. Each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. The boot block is located at either the bottom (Standard) or the top (Special Order) of the address map in order to accommodate different microprocessor protocols for boot code location. Locking and unlocking of the boot block is controlled by WP and/or RP. Intel's boot block architecture provides a flexible solution for the different design needs of various applications. The asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. The boot block provides a secure boot PROM; the parameter blocks can emulate EEPROM functionality for parameter store with proper software techniques; and the main blocks provide code and data storage with access times fast enough to execute code in place, decreasing RAM requirements. For Detail Information regarding the operation of the 28F800BV Memory die, see the Intel datasheet (order number 290539-002).
SmartDieTM is a Trademark of Intel Corporation
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Absolute Maximum Ratings
Parameter Case Operating Temperature Range Storage Temperature Range Voltage on Any Pin with Respect to GND (except VCC, VPP, A9 and RP) (1) Voltage on Pins A9 or RP with Respect to GND (except VCC, VPP, A9 and RP)
(1) (1,2)
Range -55 to +125 -65 to +150 -2.0 to +7.0 -2.0 to +13.5 -2.0 to +14.0 -2.0 to +7.0 100
Units C C V V V V mA
VPP Program Voltage with Respect to GND during Block Erase/ and Word/Byte Write (1,2) Vcc Supply Voltage with Respect to Ground Output Short Circuit Current (3)
Notes: 1. Minimum DC voltage is -0.5V on input/output pins. During Transitions, inputs may undershoot to -2.0V for periods < 20nS. Maximum DC voltage on input/output pins is Vcc + 0.5V, which may overshoot to Vcc + 2.0V for periods < 20nS. 2. Maximum DC voltage on Vpp may overshoot to +14.0V for periods < 20nS. Maximum DC voltage on RP or A9 may overshoot to VCC + 0.5V for periods <20nS 3. Output shorted for no more than 1 second. No more than one output shorted at one time. NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage. These are stress rating only. Operation beyond the "Operation Conditions" is not recommended and extended exposure beyond the "Operation Conditions" may effect device reliability.
Recommended Operating Conditions
Symbol VCC Parameter 5V Power Supply Voltage (10%) 3.3V Power Supply Voltage (0.3V) (Consult Factory) VIH VIL TA Input High Voltage (3.3V & 5V VCC) Input Low Voltage (3.3V & 5V VCC) Operating Temperature (Military) Minimum +4.5 +3.0 +2.0 -0.5 -55 Maximum +5.5 +3.6 Vcc + 0.5 +0.8 +125 Units V V V V C
Capacitance
(f = 1MHz, TA = 25C)
Symbol CAD COE CCE CRP CWE CWP CI/O
Parameter A0 - A19 Capacitance OE Capacitance CE Capacitance RP Capacitance WE Capacitance WP Capacitance I/O0 - I/O31 Capacitance
Maximum 50 50 20 50 60 50 20
Units pF pF pF pF pF pF pF
Capacitance Guaranteed by design, but not tested.
DC Characteristics - CMOS Compatible
(TA = -55C to +125C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified)
+3.3V VCC (1) Parameter Input Load Current Output Leakage Current Vcc Standby Current Vcc Deep Power-Down Current Vcc Read Current Vcc Write Current Sym IIL ILO ICCS ICCD ICCR ICCW1 ICCW2 Vcc Erase Current ICCE1 ICCE2 Vcc Erase Suspend Current VPP Standby Current
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+5.0V VCC Standard Min -1 -10 Max +1 +10 600 32 260 200 180 180 160 48 60 A A A A mA mA mA mA mA mA A Units
Conditions VCC = VCCMax., VIN = VCC or GND VCC = VCCMax., VIN = VCC or GND VCC = VCCMax., CE = RP = WP = VCC 0.2V VCC = VCCMax., VIN = VCC or GND, RP = GND 0.2V VCC = VCCMax., CE = GND, f = 10MHz (5V), 5MHz (3.3V), IOUT = 0 mA, Inputs = GND 0.2V or VCC 0.2V VPP = VPPH1 (at 5V), Word Write in Progress (x32) VPP = VPPH2 (at 12V), Word Write in Progress (x32) VPP = VPPH1 (at 5V),Block Erase in Progress VPP = VPPH2 (at 12V),Block Erase in Progress CE = VIH, Block Erase Suspend VPP < VPPH2 3
Typical Min -1 -10 Max +1 +10 440 32 120 120 100 120 100 32 60
ICCES IPPS
SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700
DC Characteristics - CMOS Compatible
(TA = -55C to +125C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified)
+3.3V VCC (1) Parameter VPP Deep Power Down Current VPP Read Current VPP Write Current Sym IPPD IPPR IPPW1 IPPW2 VPP Erase Current IPPE1 IPPE2 VPP Erase Suspend Current RP Boot Block Unlock Current Output Low Voltage Output High Voltage IPPES IRP VOL VOH1 VOH2 VPP Lock-Out Voltage VPP (Program/Erase Operations) VPP (Program/Erase Operations) VCC Erase/Write Lock Voltage RP Unlock Voltage VPPLK VPPH1 VPPH2 VLKO VHH RP = GND 0.2V VPP > VPPH2 VPP = VPPH1 (at 5V), Word Write in Progress (x32) VPP = VPPH2 (at 12V), Word Write in Progress (x32) VPP = VPPH1 (at 5V), Block Erase in Progress VPP = VPPH2 (at 12V), Block Erase in Progress VPP = VPPH, Block Erase Suspend in Progress RP = VHH, VPP = 12V VCC = VCCMin., IOL = 5.8 mA (5V), 2 mA (3.3V) VCC = VCCMin., IOH = -2.5 mA VCC = VCCMin., IOH = -100 A Complete Write Protection VPP = at 5V VPP = at 12V Locked Condition Boot Block Write/Erase, VPP = 12V 0.85 x VCC VCC 0.4V 0.0 4.5 11.4 0 11.4 1.5 5.5 12.6 2.0 12.6 Conditions Typical Min Max 40 800 120 100 120 100 800 2 0.45
+5.0V VCC Standard Min Max 40 800 120 100 100 80 800 2 0.45 0.85 x VCC VCC 0.4V 0.0 4.5 11.4 0 11.4 1.5 5.5 12.6 2.0 12.6 A A mA mA mA mA A mA V V V V V V V V Units
Notes: 1. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not tested).
AC Characteristics - Write/Erase/Program Operations - WE Controlled
(TA = -55C to +125C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified)
Symbol Parameter JEDEC Standard tAVAV tPHWL tELWL tPHHWH tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL
(1)
+3.3V VCC Typical 120nS Min Max 120 1.5 0 200 200 90 70 90 0 0 0 30 6 0.3 0.3 0.6 0 0
(2)
+4.5V to +5.5V VCC 80nS Min Max 80 .45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0 100nS Min Max 100 .45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0 100 100 120nS Min Max 120 .45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0 100 nS S nS nS nS nS nS nS nS nS nS nS S Sec Sec Sec nS nS nS Units
Write Cycle Time RP High Recovery to WE Going Low CE Setup to WE Going Low Boot Block Unlock Setup to WE Going High(1) VPP Setup to WE Going High
(1)
Address Setup to WE Going High Data Setup to WE Going High WE Pulse Width Data Hold Time from WE High Address Hold Time from WE High CE Hold Time from WE High WE Pulse Width High Duration of Word Write Operation (x32) Duration of Erase Operation (Boot) (1) Duration of Erase Operation (Parameter) (1) Duration of Erase Operation (Main) (1) VPP Hold from Valid SRD
(1) (1)
tWHQV1 tWHQV2 tWHQV3 tWHQV4
RP VHH Hold from Valid SRD (1) Boot Block Lock Delay
tQVVL tQVPH tPHBR
200
Notes: 1. Guaranteed by design, not tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not tested).
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AC Characteristics - Write/Erase/Program Operations, CE Controlled
(TA = -55C to +125C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified)
Symbol Parameter JEDEC Standard tAVAV
+3.3V VCC (2) Typical 120nS Min Max 120 1.5 0 200 200 90 70 90 0 0 0 20 6 0.3 0.3 0.6 0 0 200 80nS
+4.5V to +5.5V VCC Units 100nS Min Max 100 .45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0 100 100 120nS Min Max 120 .45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0 100 nS S nS nS nS nS nS nS nS nS nS nS S Sec Sec Sec nS nS nS Min Max 80 .45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0
Write Cycle Time RP High Recovery to CE Low WE Setup to CE Going Low Boot Block Unlock Setup to CE Going High VPP Setup to CE Going High
(1) (1)
tPHEL
tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL
(1)
Address Setup to CE Going High Data Setup to CE Going High CE Pulse Width Data Hold Time from CE High Address Hold Time from CE High WE Hold Time from CE High CE Pulse Width High Duration of Word Write Operation (x32)
(1) (1)
tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQVVL tQVPH tPHBR
Duration of Erase Operation (Boot)
Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) VPP Hold from Valid SRD
(1) (1) (1)
RP VHH Hold from Valid SRD (1) Boot Block Lock Delay
NOTES: 1. Sampled, but not 100% tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not Tested).
AC Characteristics - Read Only Operations
(TA = -55C to +125C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified)
Symbol Parameter JEDEC Standard tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH
+3.3V VCC (2) Typical 120nS Min Max 120 120 120 1.5 65 0 55 0 45 0 0 0 30 0 30 80nS Min Max 80 80 80
+4.5V to +5.5V VCC Units 100nS Min Max 100 100 100 .45 40 0 30 0 30 0 0 0 30 0 30 120nS Min Max 120 120 120 .45 40 nS nS nS S nS nS nS nS nS nS
Read Cycle Time Address to Output Delay CE to Output Delay RP to Output Delay OE to Output Delay CE to Output in Low Z (1) CE to Output in High Z (1) OE to Output in Low Z (1) OE to Output in High Z (1) Output Hold from Address, CE, or OE Change, Whichever Occurs First (1)
.45 40
Notes: 1. Guaranteed by design, but not tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not Tested).
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SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700
AC Test Circuit
Test Configuration Component Values Test Configuration
VCC
CL (pF) 50 50
R1 () 990 580
R2 () 770 390
3.3V Standard Test 5V Standard Test
R1
Device Under Test CL R2
OUT
NOTES: CL includes jig capacitance.
Parameter Input Pulse Level Input Rise and Fall Input and Output Timing Reference Level
Typical 0 - 3.0 5 1.5
Units V nS V
AC Waveforms for Write and Erase Operations, WE Controlled
VCC Power-up Standby VIH Write Write Program or Valid Address & Data (Program) Erase Setup Command or Erase Confirm Command Automated Program or Erase Delay Read Status Register Data Write Read Array Command
Addresses
VIL
AIN
AIN
tAVAV
VIH
tAVWH
tWHAX
CE
VIL
tELWL
tWHEH
VIH
OE
VIL
tWHWL
VIH
tWHQV1,2,3,4
WE
VIL
tWLWH tWHDX tDVWH
VIH
Data
VIL
High Z
tPHWL
DIN
DIN
Valid SRD
DIN
tPHHWH
VHH
tQVPH
6.5V
VIH
RP
VIL
VIH
WP
VIL
tVPWH
VPPH2 VPPH1 VPPLK VIL
tQVVL
VPP
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SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700
AC Waveforms for Write and Erase Operations, CE Controlled
VCC Power-up Standby VIH Write Write Program or Valid Address & Data (Program) Erase Setup Command or Erase Confirm Command Automated Program or Erase Delay Read Status Register Data Write Read Array Command
Addresses
VIL
AIN
AIN
tAVAV
VIH
tAVEH
tEHAX
WE
VIL
tWLEL
tEHWH
VIH
OE
VIL
tEHEL
VIH
tEHQV1,2,3,4
CE
VIL
tELEH tEHDX tDVEH
VIH
Data
VIL
High Z
tPHEL
DIN
DIN
Valid SRD
DIN
tPHHEH
VHH
tQVPH
6.5V
VIH
RP
VIL
VIH
WP
VIL
tVPEH
VPPH2 VPPH1 VPPLK VIL
tQVVL
VPP
AC Waveform For Read Operations
Standby Device and Address Selection Outputs Enabled Addresses Stable VIL Data Valid Standby
VIH
Addresses
tAVAV
VIH
CE
VIL
tEHQZ
VIH
OE
VIL VIH
tGHQZ tGLQV
WE
VIL
tELQV tGLQX tELQX
VOH
tOH
High Z
Valid Output
Data
VOL
High Z
tAVQV
VIH
RP
VIL
tPHQV
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SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700
Pin Numbers & Functions 68 Pins -- Dual-Cavity CQFP (Standard Configuration)
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function GND CE3 A5 A4 A3 A2 A1 A0 RP I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 VCC A11 A12 A13 A14 A15 A16 CE1 Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function OE CE2 A17 WP NC NC A18 A19 VPP I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 Pin # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function GND I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 VCC A10 A9 A8 A7 A6 WE CE4
Consult Factory for Special order (Optional Configuration): Pin 38 - WE2, Pin 39 - WE3, Pin 40 - WE4 and Pin 67 - WE1
"F14" -- CQFP Dual-Cavity Flat Package
0.990 SQ .010 0.940 SQ .010 0.180 MAX Pin 61 0.01R Pin 60
Pin 9 Pin 10
0.015 .002 0.750 .008 +.002 -.001
.010 .008 .040
Detail "A"
Pin 26 Pin 27 0.800 REF
Pin 44 Pin 43 See Detail "A"
All dimensions in inches
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SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
ACT-F1M32B-080F14C ACT-F1M32B-100F14C ACT-F1M32B-120F14C ACT-F1M32B-080F14I ACT-F1M32B-100F14I ACT-F1M32B-120F14I ACT-F1M32B-080F14M ACT-F1M32B-100F14M ACT-F1M32B-120F14M ACT-F1M32B-080F14Q ACT-F1M32B-100F14Q ACT-F1M32B-120F14Q
Screening
Commercial (0C to +70C) Commercial (0C to +70C) Commercial (0C to +70C) Industrial (-40C to +85C) Industrial (-40C to +85C) Industrial (-40C to +85C) Military (-55C to +125C) Military (-55C to +125C) Military (-55C to +125C) DESC Drawing Pending MIL-PRF-38534 Compliant DESC Drawing Pending MIL-PRF-38534 Compliant DESC Drawing Pending MIL-PRF-38534 Compliant
Speed 80 nS 100 nS 120 nS 80 nS 100 nS 120 nS 80 nS 100 nS 120 nS 80 nS 100 nS 120 nS
Package
CQFP CQFP CQFP CQFP CQFP CQFP CQFP CQFP CQFP CQFP CQFP CQFP
Part Number Breakdown
ACT- F 1M 32 B- 080 F14 M
Aeroflex Circuit Technology Memory Type S = SRAM F = FLASH EEPROM E = EEPROM D = Dynamic RAM Memory Depth, Locations Memory Width, Bits Pinout Options B = Bottom Boot Block (Standard), T= Top Boot Block (Special Order) Memory Speed, ns (+5V VCC) Specifications subject to change without notice Screening C = Commercial Temp, 0C to +70C I = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C, Screened * Q = MIL-PRF-38534 Compliant/SMD if applicable Package Type & Size Surface Mount Packages F14 = .94" SQ 68 Lead\Dual-Cavity CQFP
* Screened to the individual test methods of MIL-STD-883
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