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STQ2NK60ZR-AP STP2NK60Z - STD2NK60Z-1
N-CHANNEL 600V - 7.2 - 1.4A TO-220/TO-92/IPAK Zener-Protected SuperMESHTM MOSFET
Table 1: General Features
TYPE STQ2NK60ZR-AP STP2NK60Z STD2NK60Z-1
s s s s s s
Figure 1: Package
ID 0.4 A 1.4 A 1.4 A Pw 3W 45 W 45 W <8 <8 <8
VDSS 600 V 600 V 600 V
RDS(on)
TYPICAL RDS(on) = 7.2 EXTREMELY HIGH dv/dt CAPABILITY ESD IMPROVED CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED
TO-92 (Ammopack) TO-220
3 1 2
3
DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
2 1
IPAK Figure 2: Internal Schematic Diagram
APPLICATIONS s LOW POWER BATTERY CHARGERS s SWITH MODE LOW POWER SUPPLIES(SMPS) s LOW POWER, BALLAST, CFL (COMPACT FLUORESCENT LAMPS)
Table 2: Order Codes
SALES TYPE STQ2NK60ZR-AP STP2NK60Z STD2NK60Z-1 MARKING Q2NK60ZR P2NK60Z D2NK60Z PACKAGE TO-92 TO-220 IPAK PACKAGING AMMOPAK TUBE TUBE
Rev. 3 July 2004 1/13
STQ2NK60ZR-AP - STP2NK60Z - STD2NK60Z-1
Table 3: Absolute Maximum ratings
Symbol VDS VDGR VGS ID ID IDM ( ) PTOT VESD(G-S) dv/dt (1) Tj Tstg Parameter TO-220 / IPAK Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate source ESD (HBM-C= 100pF, R=1.5k) Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature 1.4 0.77 5.6 45 0.36 1500 4.5 -55 to 150 600 600 30 0.4 0.25 1.6 3 0.025 Value TO-92 V V V A A A W W/C V V/ns C Unit
( ) Pulse width limited by safe operating area (1) ISD 1.4A, di/dt 200A/s, VDD V(BR)DSS, T j T JMAX.
Table 4: Thermal Data
TO-220 / IPAK Rthj-case Rthj-amb Rthj-lead Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Junction-lead Max Maximum Lead Temperature For Soldering Purpose 2.77 100 -300 TO-92 -120 40 260 Unit C/W C/W C/W C
Table 5: Avalanche Characteristics
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 1.4 90 Unit A mJ
Table 6: Gate-Source Zener Diode
Symbol BVGSO Parameter Gate source Breakdown Voltage Test Conditions Igs= 1 mA (Open Drain) Min. 30 Typ. Max. Unit V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions ID = 1mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V VDS = VGS, ID = 50 A VGS = 10V, ID = 0.7 A 3 3.75 7.2 Min. 600 1 50 10 4.5 8 Typ. Max. Unit V A A A V
Table 8: Dynamic
Symbol gfs (1) Ciss Coss Crss Coss eq. (3) td(on) tr td(off) tr Qg Qgs Qgd Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Test Conditions VDS = 15 V, ID= 0.7 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 1 170 27 5 30 8 30 22 55 7.7 1.7 4 10 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
Equivalent Output Capacitance VGS = 0V, VDS = 0V to 480V Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 300 V, ID = 0.65 A, RG= 4.7 , VGS = 10 V (Resistive Load see, Figure 21) VDD = 480V, ID = 1.5 A, VGS = 10V (see, Figure 24)
Table 9: Source Drain Diode
Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 1.5 A, VGS = 0 ISD = 1.3 A, di/dt = 100 A/s VDD = 25V, Tj = 25C (see test circuit, Figure 22) ISD = 1.3 A, di/dt = 100 A/s VDD = 25V, Tj = 150C (see test circuit, Figure 22) 250 550 4.4 300 690 4.6 Test Conditions Min. Typ. Max. 1.5 6 1.6 Unit A A V ns C A ns C A
(1) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. (3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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STQ2NK60ZR-AP - STP2NK60Z - STD2NK60Z-1
Figure 3: .Safe Operating Area For TO-220 Figure 6: Thermal Impedance For TO-220
Figure 4: Safe Operating Area For IPAK
Figure 7: Thermal Impedance For IPAK
Figure 5: Safe Operating Area For TO-92
Figure 8: Thermal Impedance For TO-92
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Figure 9: Output Characteristics Figure 12: Transfer Characteristics
Figure 10: Transconductance
Figure 13: Static Drain-source On Resistance
Figure 11: Gate Charge vs Gate-source Voltage
Figure 14: Capacitance Variations
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Figure 15: Normalized Gate Thereshold Voltage vs Temperature Figure 18: Normalized On Resistance vs Temperature
Figure 16: Source-Drain Forward Characteristics
Figure 19: Normalized BVDSS vs Temperature
Figure 17: Maximum Avalanche Energy vs Temperature
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Figure 20: Unclamped Inductive Load Test Circuit Figure 23: Unclamped Inductive Wafeform
Figure 21: Switching Times Test Circuit For Resistive Load
Figure 24: Gate Charge Test Circuit
Figure 22: Test Circuit For Inductive Load Switching and Diode Recovery Times
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TO-92 MECHANICAL DATA
mm. DIM. MIN. A b D E e e1 L R S1 W V 4.32 0.36 4.45 3.30 2.41 1.14 12.70 2.16 0.92 0.41 5 TYP MAX. 4.95 0.51 4.95 3.94 2.67 1.40 15.49 2.41 1.52 0.56 MIN. 0.170 0.014 0.175 0.130 0.094 0.044 0.50 0.085 0.036 0.016 5 TYP. MAX. 0.194 0.020 0.194 0.155 0.105 0.055 0.610 0.094 0.060 0.022 inch
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TO-220 MECHANICAL DATA
mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154
DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 oP Q
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TO-251 (IPAK) MECHANICAL DATA
DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033
H
C A C2
L2
D
B3 B6
A1
L
=
=
3
B5
B
A3
=
B2
=
G
=
E
L1
1
2
=
0068771-E
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STQ2NK60ZR-AP - STP2NK60Z - STD2NK60Z-1
TO-92 AMMOPACK
mm. MIN. 4.45 3.30 TYP MAX. 4.95 3.94 1.6 2.3 0.41 12.5 5.65 2.44 -2 17.5 5.7 8.5 18.5 15.5 3.8 16 4 18 6 9 12.7 6.35 2.54 0.56 12.9 7.05 2.94 2 19 6.3 9.25 0.5 20.5 16.5 25 4.2 0.9 11 3 -1 1 0.11 -0.04 0.04 0.15 0.157 0.72 0.61 0.63 0.016 0.49 0.22 0.09 -0.08 0.69 0.22 0.33 0.71 0.23 0.35 0.5 0.25 0.1 MIN. 0.170 0.130 inch TYP. MAX. 0.194 0.155 0.06 0.09 0.022 0.51 0.27 0.11 0.08 0.74 0.24 0.36 0.02 0.80 0.65 0.98 0.16 0.035 0.43
DIM. A1 T T1 T2 d P0 P2 F1, F2 delta H W W0 W1 W2 H H0 H1 D0 t L l1 delta P
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Table 10: Revision History
Date 07-Jul-2004 Revision 3 New stylesheet Description of Changes The document change from "TARGET" to "COMPLETE"
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
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