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| (R) PRELIMINARY SP3508 Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors FEATURES Fast 20Mbps Differential Transmission Rates Internal Transceiver Termination Resistors for V.11 & V.35 Interface Modes: RS-232 (V.28) X.21 (V.11) RS-449/V.36 (V.10 & V.11) EIA-530 (V.10 & V.11) EIA-530A (V.10 & V.11) V.35 (V.35 & V.28) Now Available in Lead Free Packaging Refer to page 9 for pinout Protocols are Software Selectable with 3-Bit Word Eight (8) Drivers and Eight (8) Receivers Termination Network Disable Option Internal Line or Digital Loopback for Diagnostic Testing Adheres to NET1/NET2 and TBR-2 Compliancy Requirements Easy Flow-Through Pinout +3.3V Only Operation Individual Driver and Receiver Enable/Disable Controls Operates in either DTE or DCE Mode APPLICATIONS Router Frame Relay CSU DSU PBX Secure Communication Terminals DESCRIPTION The SP3508 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP3508 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex regulated charge pump allowing +3.3V only operation. Sipex's patented charge pump provides a regulated output of +5.5V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. All necessary termination is integrated within the SP3508 and is switchable when V.35 drivers and V.35 receivers, or when V.11 receivers are used. The SP3508 provides the controls and transceiver availability for operating as either a DTE or DCE. Additional features with the SP3508 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP3508 also includes a latch enable pin with the driver and receiver address decoder. The internal V.11 or V.35 termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP3508 include separate enable pins for added convenience. The SP3508 is ideal for WAN serial ports in networking equipment such as routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices. Applicable U.S. Patents-5,306,954; and others patents pending Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS VCC ................................................................................................ +7V Input Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers ............................................. -0.3V to (VCC+0.5V) Receivers ........................................................... 15.5V Output Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers ................................................................... 12V Receivers ........................................ -0.3V to (VCC+0.5V) Storage Temperature ................................................ -65C to +150C Power Dissipation ................................................................. 1520mW (derate 19.0mW/C above +70C) Package Derating: oJA ................................................................................................................. 36.9 C/W oJC .................................................................................................................... 6.5 C/W These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. STORAGE CONSIDERATIONS Due to the relatively large package size of the 100-pin quad flatpack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125C in order to remove moisture prior to soldering. Sipex ships the 100-pin LQFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH. ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER LOGIC INPUTS VIL VIH LOGIC OUTPUTS VOL VOH MIN. TYP. MAX. UNITS CONDITIONS 0.8 2.0 V V 0.4 VCC 0.6 VCC 0.3 V V IOUT= - 3.2mA IOUT= 1.0mA V.28 DRIVER DC Parameters (Outputs) Outputs Open Circuit Voltage Loaded Voltage Short-Circuit Current Power-Off Impedance 300 5.0 15 15 100 V V mA per Figure 1 per Figure 2 per Figure 4 per Figure 5 VCC = +3.3V for AC parameters 1.5 30 0.5 0.5 120 1.0 1.0 230 3.0 3.0 s V/s s s kbps per Figure 6, +3V to -3V per Figure 3 V.28 DRIVER AC Parameters (Outputs) Transition Time Instantaneous Slew Rate Propagation Delay: tPHL Propagation Delay: tPLH Max.Transmission Rate Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 2 ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.28 RECEIVER DC Parameters (Inputs) Input Impedance Open-Circuit Bias HIGH Threshold LOW Threshold V.28 RECEIVER AC Parameters Propagation Delay: tPHL Propagation Delay: tPLH Max Transmission Rate 120 100 100 235 500 500 ns ns kbps 0.8 1.7 1.2 3 7 +2.0 3.0 k V V V VCC = +3.3V for AC parameters per Figure 7 per Figure 8 V.10 DRIVER DC Parameters (Outputs) Open Circuit Voltage Test-Terminated Voltage Short-Circuit Current Power-Off Current V.10 DRIVER AC Parameters (Outputs) Transition Time Propagation Delay: tPHL Propagation Delay: tPLH Max Transmission Rate 120 100 100 200 500 500 ns ns ns kbps 4.0 0.9VOC 150 100 6.0 V V mA A per Figure 9 per Figure 10 per Figure 11 per Figure 12 VCC = +3.3V for AC parameters per Figure 13; 10% to 90% V.10 RECEIVER DC Parameters (Inputs) Input Current Input Impedance Sensitivity V.10 RECEIVER AC Parameters Propagation Delay: tPHL Propagation Delay: tPLH Max Transmission Rate 120 120 120 250 250 ns ns kbps -3.25 4 0.3 +3.25 mA k V VCC = +3.3V for AC parameters per Figures 14 and 15 Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 3 ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.11 DRIVER DC Parameters (Outputs) Open Circuit Voltage (VOC) Test Terminated Voltage 2.0 0.5(VOC) Balance Offset Short-Circuit Current Power-Off Current V.11 DRIVER AC Parameters (Outputs) Transition Time Propagation Delay: tPHL Propagation Delay: tPLH Differential Skew Max.Transmission Rate 20 30 30 5 10 60 60 10 ns ns ns ns Mbps 0.4 +3.0 150 100 6.0 V V V V V mA A per Figure 17 per Figure 17 per Figure 18 per Figure 19 VCC = +3.3V for AC parameters per Figures 21 and 35; 10% to 90% Using CL = 50pF; per Figures 32 and 35 per Figures 32 and 35 per Figures 32 and 35 per Figure 16 per Figure 17 V.11 RECEIVER DC Parameters (Inputs) Common Mode Range Sensitivity Input Current Current w/ 100 Termination Input Impedance V.11 RECEIVER AC Parameters Propagation Delay: tPHL Propagation Delay: tPLH Skew Max Transmission Rate 20 30 30 5 60 60 10 ns ns ns Mbps 4 -3.25 -7 +7 0.2 3.25 60.75 V V mA mA k VCC = +3.3V for AC parameters Using CL = 50pF per Figures 32 and 37 per Figures 32 and 37 per Figure 32 per Figure 20 and 22; power on or off per Figure 23 and 24 Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 4 ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.35 DRIVER DC Parameters (Outputs) Open Circuit Voltage Test Terminated Voltage Offset Output Overshoot Source Impedance Short-Circuit Impedance -0.2VST 1.20 0.44 0.66 0.6 +0.2VST 150 165 V V V V per Figure 16 per Figure 25 per Figure 25 per Figure 25; VST = Steady state value per Figure 26; ZS = V2/V1 x 50 per Figure 27 VCC = +3.3V for AC parameters 50 135 V.35 DRIVER AC Parameters (Outputs) Transition Time Propagation Delay: tPHL Propagation Delay: tPLH Differential Skew Max.Transmission Rate 20 30 30 20 60 60 5 ns ns ns ns Mbps per Figures 32 and 35; CL = 20pF per Figures 32 and 35; CL = 20pF per Figures 32 and 35; CL = 20pF V.35 RECEIVER DC Parameters (Inputs) Sensitivity Source Impedance Short-Circuit Impedance V.35 RECEIVER AC Parameters Propagation Delay: tPHL Propagation Delay: tPLH Skew Max.Transmission Rate 20 30 30 5 60 60 10 ns ns ns Mbps 90 135 50 200 110 165 mV per Figure 29; ZS = V2/V1 x 50 per Figure 30 VCC = +5V for AC parameters per Figures 32 and 37; CL = 20pF per Figures 32 and 37; CL = 20pF per Figures 32; CL = 20pF TRANSCEIVER LEAKAGE CURRENTS Driver Output 3-State Current Receiver Output 3-State Current 1 200 10 A A per Figure 31; Drivers disabled DX = 111 Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 5 ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER POWER REQUIREMENTS VCC ICC (No Mode Selected) V.28/RS-232) (V.11/RS-422) (EIA-530 & RS-449) (V.35) MIN. TYP. MAX. UNITS CONDITIONS 3.15 3.3 1 95 230 270 170 3.45 V A mA mA mA mA All ICC values are with VCC = +3.3V fIN = 230kbps; Drivers active & loaded fIN = 20Mbps; Drivers active & loaded fIN = 20Mbps; Drivers active & loaded V.35 @ fIN = 20Mbps, V.28 @ 230kbps Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 6 OTHER AC CHARACTERISTICS TA = 0 to 70C and VCC = +3.3V unless otherwise noted. PARAMETER RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE 0.70 0.40 0.20 0.40 0.15 0.20 0.20 0.15 2.80 0.10 0.10 0.10 2.60 0.10 0.10 0.15 5.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 10.0 2.0 2.0 2.0 10.0 2.0 2.0 2.0 s s s s s s s s s s s s s s s s CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed CL = 100pF, Fig. 33 & 36; S1 closed CL = 100pF, Fig. 33 & 36; S2 closed CL = 15pF, Fig. 33 & 36; S1 closed CL = 15pF, Fig. 33 & 36; S2 closed CL = 100pF, Fig. 33 & 36; S1 closed CL = 100pF, Fig. 33 & 36; S2 closed CL = 15pF, Fig. 33 & 36; S1 closed CL = 15pF, Fig. 33 & 36; S2 closed RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE 0.12 0.10 0.10 0.10 0.10 0.10 0.10 0.10 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 s s s s s s s s CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 7 OTHER AC CHARACTERISTICS: Continued TA = 0 to 70C and VCC = +3.3V unless otherwise noted. PARAMETER RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state MIN. TYP. 0.10 0.10 0.10 0.10 MAX. 2.0 2.0 2.0 2.0 UNITS s s s s CONDITIONS CL = 100pF, Fig. 34 & 38; S1 closed CL = 100pF, Fig. 34 & 38; S2 closed CL = 15pF, Fig. 34 & 38; S1 closed CL = 15pF, Fig. 34 & 38; S2 closed CL = 100pF, Fig. 34 & 38; S1 closed CL = 100pF, Fig. 34 & 38; S2 closed CL = 15pF, Fig. 34 & 38; S1 closed CL = 15pF, Fig. 34 & 38; S2 closed 0.10 0.10 0.10 0.10 2.0 2.0 2.0 2.0 s s s s TRANSCEIVER TO TRANSCEIVER SKEW RS-232 Driver 100 100 RS-232 Receiver 20 20 RS-422 Driver 2 2 RS-422 Receiver 3 3 RS-423 Driver 5 5 RS-423 Receiver 5 5 V.35 Driver V.35 Receiver 4 4 6 6 (per Figures 32, 35, 37) ns [ (tphl )Tx1 - (tphl )Txn ] ns [ (tplh )Tx1 - (tplh )Txn] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Tx1 - (tphl )Txn ] ns [ (tplh )Tx1 - (tplh )Txn ] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Tx2 - (tphl )Txn ] ns [ (tplh )Tx2 - (tplh )Txn ] ns [ (tphl )Rx2 - (tphl )Rxn ] ns [ (tphl )Rx2 - (tphl )Rxn ] ns ns ns ns [ (tphl )Tx1 - (tphl )Txn ] [ (tplh )Tx1 - (tplh )Txn ] [ (tphl )Rx1 - (tphl )Rxn ] [ (tphl )Rx1 - (tphl )Rxn] Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 8 PINOUT 79 RRC(a) 77 RCC(b) 100 VCC 99 SD(b) 97 SD(a) 83 RS(b) 81 RS(a) 87 TR(b) 85 TR(a) 91 ST(b) 89 ST(a) 93 TT(a) 95 TT(b) 96 GND 92 GND 88 GND 84 GND 80 GND 94 VCC 90 VCC 86 VCC 82 VCC GND 1 SDEN 2 TTEN 3 STEN 4 RSEN 5 TREN 6 RRCEN 7 RLEN 8 LLEN 9 RDEN 10 RTEN 11 TXCEN 12 CSEN13 DMEN 14 RRTEN 15 ICEN 16 TMEN 17 D0 18 D1 19 D2 20 D_LATCH 21 TERM_OFF 22 VCC 23 C3P 24 GND 25 (R) 76 VDD 98 VCC 78 VCC 75 GND 74 C1P 73 VCC 72 C2P 71 GND 70 C1N 69 C2N 68 VSS1 67 RL(a) 66 VCC 65 LL(a) 64 TM(a) 63 IC 62 RRT(a) 61 RRT(b) SP3508 60 GNDV10 59 DM(a) 58 DM(b) 57 CS(a) 56 CS(b) 55 TXC(a) 54 GND 53 TXC(b) 52 RT(a) 51 RT(b) ST 33 RTS 34 LOOPBACK 30 TXD 31 TXCE 32 TXC 41 VSS2 27 AGND 28 DTR 35 CTS 42 TM 46 RI 45 GND 47 AVCC 29 RXD 39 RXC 40 DSR 43 VCC 48 RL 37 LL 38 RD(b) 49 Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver DCD_DCE 36 DCD_DTE 44 (c) Copyright 2004 Sipex Corporation 9 RD(a) 50 C3N 26 SP3508 Pin Designation Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Date: 06/14/04 Pin Name GND SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN RDEN RTEN TxCEN CSEN DMEN RRTEN ICEN TMEN D0 D1 D2 D_LATCH VCC C3P GND C3N VSS2 AGND AVCC TxD TxCE ST RTS DTR DCD_DCE RL LL RxD RxC TxC CTS DSR DCD_DTE RI TM GND VCC RD(B) RD(A) Description Signal Ground TxD Driver Enable Input TxCE Driver Enable Input ST Driver Enable Input RTS Driver Enable Input DTR Driver Enable Input DCD Driver Enable Input RL Driver Enable Input LL Driver Enable Input RxD Receiver Enable Input RxC Receiver Enable Input TxC Receiver Enable Input CTS Receiver Enable Input DSR Receiver Enable Input DCDDTE Receiver Enable Input RI Receiver Enable Input TM Receiver Enable Input Mode Select Input Mode Select Input Mode Select Input Decoder Latch Input Power Supply Input Charge Pump Capacitor Signal Ground Charge Pump Capacitor Minus VCC Signal Ground Power Supply Input TxD Driver TTL Input TxCE Driver TTL Input ST Driver TTL Input RTS Driver TTL Input DTR Driver TTL Input DCDDCE Driver TTL Input RL Driver TTL Input LL Driver TTL Input RxD Receiver TTL Output RxC Receiver TTLOutput TxC Receiver TTL Output CTS Receiver TTL Output DSR Receiver TTL Output DCDDTE Receiver TTL Output RI Receiver TTL Output TM Receiver TTL Output Signal Ground Power Supply Input RXD Non-Inverting Input RXD Inverting Input Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name RT(B) RT(A) TxC(B) GND TxC(A) CS(B) CS(A) DM(B) DM(A) GNDV10 RRT(B) RRT(A) IC TM(A) LL(A) VCC RL(A) VSS1 C2N C1N GND C2P VCC C1P GND VDD RRC(B) VCC RRC(A) GND RS(A) VCC RS(B) GND TR(A) VCC TR(B) GND ST(A) VCC ST(B) GND TT(A) VCC TT(B) GND SD(A) VCC SD(B) VCC Description RxC Non-Inverting Input RxC Inverting Input TxC Non-Inverting Input Signal Ground TxC Inverting Input CTS Non-Inverting Input CTS Inverting Input DSR Non-Inverting Input DSR Inverting Input V.10 Rx Reference Node DCDDTE Non-Inverting Input DCDDTE Inverting Input RI Receiver Input TM Receiver Input LL Driver Output Power Supply Input RL Driver Output -2xVCC Charge Pump Output Charge Pump Capacitor Charge Pump Capacitor Signal Ground Charge Pump Capacitor Power Supply Input Charge Pump Capacitor Signal Ground 2xVCC Charge Pump Output DCDDCE Non-Inverting Output Power Supply Input DCDDCE Inverting Output Signal Ground RTS Inverting Output Power Supply Input RTS Non-Inverting Output Signal Ground DTR Inverting Output Power Supply Input DTR Non-Inverting Output Signal Ground ST Inverting Output Power Supply Input ST Non-Inverting Output Signal Ground TxCE Inverting Output Power Supply Input TxCE Non-Inverting Output Signal Ground TxD Inverting Output Power Supply Input TxD Non-Inverting Output Power Supply Input (c) Copyright 2004 Sipex Corporation TERM_OFF Termination Disable Input LOOPBACK Loopback Mode Enable Input SP3508 Enhanced WAN Multi-Mode Serial Transceiver 10 SP3508 Driver Table Driver Output Pin MODE (D0, D1, D2) T1OUT(a) T1OUT(b) T2OUT(a) T2OUT(b) T3OUT(a) T3OUT(b) T4OUT(a) T4OUT(b) T5OUT(a) T5OUT(b) T6OUT(a) T6OUT(b) T7OUT(a) T8OUT(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 Mode (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530A Mode 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 RS-449 Mode (V.36) 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 X.21 Mode (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z TxD(a) TxD(b) TxCE(a) TxCE(b) TxC_DCE(a) TxC_DCE(b) RTS(a) RTS(b) DTR(a) DTR(b) DCD_DCE(a) DCD_DCE(b) RL LL Suggested Signal Table 1. Driver Mode Selection SP3508 Receiver Table Receiver Input Pin MODE (D0, D1, D2) R1IN(a) R1IN(b) R2IN(a) R2IN(b) R3IN(a) R3IN(b) R4IN(a) R4IN(b) R5IN(a) R5IN(b) R6IN(a) R6IN(b) R7IN(a) R8IN(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 Mode (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530A Mode 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 RS-449 Mode (V.36) 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 X.21 Mode (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z RxD(a) RxD(b) RxC(a) RxC(b) TxC_DTE(a) TxC_DTE(b) CTS(a) CTS(b) DSR(a) DSR(b) DCD_DTE(a) DCD_DTE(b) RI TM Suggested Signal Table 2. Receiver Mode Selection Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 11 TEST CIRCUITS A A VOC 3k VT C C Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage A A 7k VT Oscilloscope Isc C Scope used for slew rate measurement. C Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current VCC = 0V A Ix A 2V 3k 2500pF Oscilloscope C C Figure 5. V.28 Driver Output Power-Off Impedance Figure 6. V.28 Driver Output Rise/Fall Times Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 12 A A Iia 15V voc C C Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias A A 3.9k VOC 450 Vt C C Figure 9. V.10 Driver Output Open-Circuit Voltage Figure 10. V.10 Driver Output Test Terminated Voltage VCC = 0V A A Ix 0.25V Isc C C Figure 11. V.10 Driver Output Short-Circuit Current Figure 12. V.10 Driver Output Power-Off Current Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 13 A A Iia 10V 450 Oscilloscope C C Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current A V.10 RECEIVER +3.25mA 3.9k VOC VOCB VOCA -10V -3V B +3V +10V Maximum Input Current Versus Voltage -3.25mA C Figure 15. V.10 Receiver Input IV Graph Figure 16. V.11 Driver Output Open-Circuit Voltage A A Isa 50 VT 50 Isb B B V OS C C Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 14 VCC = 0V A A Ixa 0.25V Iia 10V B B C C VCC = 0V A A 0.25V 10V Ixb B B Iib C C Figure 19. V.11 Driver Output Power-Off Current Figure 20. V.11 Receiver Input Current A V.11 RECEIVER 50 Oscilloscope +3.25mA 50 -10V B 50 VE -3V +3V +10V C Maximum Input Current Versus Voltage -3.25mA Figure 21. V.11 Driver Output Rise/Fall Time Figure 22. V.11 Receiver Input IV Graph Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 15 A Iia 6V V.11 RECEIVER w/ Optional Cable Termination (100 to 150) i [mA] = V [V] / 0.1 100 to 150 i [mA] = V [V] - 3) / 4.0 -6V -3V +3V +6V B i [mA] = V [V] - 3) / 4.0 C i [mA] = V [V] / 0.1 Maximum Input Current versus Voltage Figure 24. V.11 Receiver Input Graph with Termination A 6V 100 to 150 A 50 B Iib VT 50 VOS B C C Figure 23. V.11 Receiver Input Current w/ Termination Figure 25. V.35 Driver Output Test Terminated Voltage V1 A 50 24kHz, 550mVp-p Sine Wave A V2 B ISC B 2V C C Figure 26. V.35 Driver Output Source Impedance Figure 27. V.35 Driver Output Short-Circuit Impedance Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 16 A A V1 50 Oscilloscope 50 24kHz, 550mVp-p Sine Wave V2 50 B 50 C B C Figure 28. V.35 Driver Output Rise/Fall Time Figure 29. V.35 Receiver Input Source Impedance Any one of the three conditions for disabling the driver. A VCC = 0V 1 1 1 D2 D1 D0 VCC A IZSC 10V B Isc Logic "1" IZSC B 10V 2V C Figure 30. V.35 Receiver Input Short-Circuit Impedance Figure 31. Driver Output Leakage Current Test CL1 TIN B A CL2 fIN (50% Duty Cycle, 2.5VP-P) B ROUT A 15pF Figure 32. Driver/Receiver Timing Test Circuit Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 17 Output Under Test 500 CL S1 VCC Receiver Output CRL Test Point S1 1K S2 1K VCC S2 Figure 33. Driver Timing Test Load Circuit Figure 34. Receiver Timing Test Load Circuit f > 10MHz; tR < 5ns; tF < 5ns DRIVER INPUT +3V 1.5V 0V A B VO+ 0V VO- tDPLH tDPHL VO 1/2VO tPLH tPHL 1/2VO 1.5V DRIVER OUTPUT DIFFERENTIAL OUTPUT VB - VA tR tF tSKEW = | tDPLH - tDPHL | Figure 35. Driver Propagation Delays Mx or Tx_Enable f = 1MHz; tR 10ns; tF 10ns +3V 1.5V 0V 5V tZL 2.3V Output normally LOW 1.5V tLZ 0.5V 0.5V tHZ A, B VOL VOH A, B 0V 2.3V tZH Output normally HIGH Figure 36. Driver Enable and Disable Times A-B V0D2+ V0D2- VOH f > 10MHz; tR < 5ns; tF < 5ns 0V INPUT OUTPUT (VOH - VOL)/2 (VOH - VOL)/2 tPHL 0V RECEIVER OUT VOL tSKEW = | tPHL - tPLH | tPLH Figure 37. Receiver Propagation Delays Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 18 f = 1MHz; tR < 10ns; tF < 10ns DECx +3V 1.5V RxENABLE 0V tZL 1.5V Output normally LOW +3.3V RECEIVER OUT VIL VIH RECEIVER OUT 0V 1.5V tZH Output normally HIGH 1.5V tLZ 0.5V 0.5V tHZ Figure 38. Receiver Enable and Disable Times +3V Tx_Enable 0V 0V TOUT VOL f = 60kHz; tR < 10ns; tF < 10ns 1.5V tZL VOL - 0.5V Output LOW 1.5V tLZ VOL - 0.5V +3V Tx_Enable 0V VOH 0V f = 60kHz; tR < 10ns; tF < 10ns 1.5V tZH Output HIGH 1.5V tHZ VOH - 0.5V TOUT Figure 39. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 19 Figure 40. Typical V.10 Driver Output Waveform. Figure 41. Typical V.11 Driver Output Waveform. Figure 42. Typical V.28 Driver Output Waveform. Figure 43. Typical V.35 Driver Output Waveform. Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 20 (See pinout assignments for GND and VCC pins) +3.3V (decoupling capacitor not shown) C1 C2 1F CVDD 1F 74 1F 70 72 69 +3.3V 76 VCC VDD C1+ C1- C2+ C2- C3+ C3- 24 1F 26 68 1F C3 Regulated Charge Pump VSS1 CVSS1 29 AVCC Inverter VSS2 27 1F CVSS2 RD(a) RxD RDEN RD(b) RT(a) RxC RTEN RT(b) TxC(a) TxC TxCEN TxC(b) CS(a) CTS CSEN CS(b) DM(a) DSR DMEN DM(b) RRT(a) DCD_DTE RRTEN RRT(b) IC RI ICEN 50 31 97 TxD SD(a) SD(b) SDEN TxCE TT(a) TT(b) TTEN ST ST(a) ST(b) STEN RTS RS(a) RS(b) RSEN DTR TR(a) TR(b) TREN DCD_DCE RRC(a) RRC(b) RRCEN RL RL(a) RLEN LL LL(a) LLEN 39 10 49 52 99 2 32 93 40 11 51 55 95 3 33 89 41 12 53 57 91 4 34 81 42 13 56 59 83 5 35 85 43 14 58 62 87 6 36 79 44 15 61 63 77 7 37 45 16 67 8 TM(a) TM TMEN 64 38 46 17 65 9 18 19 20 21 22 D0 D1 D2 D-LATCH TERM-OFF LOOPBACK GND 51ohms V.35 MODE 124ohms SP3508 V.10-GND AGND 60 28 RECEIVER TERMINATION NETWORK 30 V.35 MODE V.11 MODE RX ENABLE 51ohms 51ohms 124ohms V.35 DRIVER TERMINATION NETWORK TX ENABLE 51ohms Figure 44. Functional Diagram Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 21 FEATURES The SP3508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP3508 offers the hardware interface modes for RS-232 (V.28), RS-449/V.36 (V.11 and V.10), EIA-530 (V.11 and V.10), EIA-530A (V.11 and V.10), V.35 (V.35 and V.28) and X.21(V.11). The interface mode selection is done via three control pins, which can be latched via microprocessor control. The SP3508 has eight drivers, eight receivers, and Sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. Other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, failsafe when inputs are either open or shorted. THEORY OF OPERATION The SP3508 device is made up of 1) the drivers 2) the receivers 3) charge pumps 4) DTE/DCE switching algorithm 5) control logic. Drivers The SP3508 has eight enhanced independent drivers. Control for the mode selection is done via a three-bit control word into D0, D1, and D2. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. The mode of each driver in the different interface modes that can be selected is shown in Table 1. The third type of drivers are V.11 (RS-422) differential drivers. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential output levels with a load of 100. The strength allows the SP3508 differential driver to drive over long cable lengths with minimal signal degradation. The V.11 drivers are used in RS449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. Sipex's new driver design over its predecessors allow the SP3508 to operate over 20Mbps for differential transmission. There are four basic types of driver circuits - ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423), ITU-T-V.11 (RS-422), and CCITT-V.35. The V.28 (RS-232) drivers output single-ended signals with a minimum of +5V (with 3k & 2500pF loading), and can operate over 120kbps. Since the SP3508 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 driver architecture is similar to Sipex's standard line of RS232 transceivers. The RS-423 (V.10) drivers are also single-ended signals which produce open circuit VOL and VOH measurements of +4.0V to +6.0V. When terminated with a 450 load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 (RS-423) drivers are used in RS-449/V.36, EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. The V.10 driver can transmit over 120Kbps if necessary. Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 22 FEATURES The fourth type of drivers are V.35 differential drivers. There are only three available on the SP3508 for data and clock (TxD, TxCE, and TxC in DCE mode). These drivers are current sources that drive loop current through a differential pair resulting in a 550mV differential voltage at the receiver. These drivers also incorporate fixed termination networks for each driver in order to set the VOH and VOL depending on load conditions. This termination network is basically a "Y" configuration consisting of two 51 resistors connected in series and a 124 resistor connected between the two 50 resistors to GND. Filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. The drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable DTE/DCE. The enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on Figure 44. The enable pins have internal pull-up and pulldown devices, depending on the active polarity of the receiver, that enable the driver upon poweron if the enable lines are left floating. During disabled conditions, the driver outputs will be at a high impedance 3-state. The driver inputs are both TTL or CMOS compatible. All driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic LOW ("0"). Unused driver inputs can be left floating. The internal pull-up resistor value is approximately 500k. Receivers The SP3508 has eight enhanced independent receivers. Control for the mode selection is done via a three-bit control word that is the same as the driver control word. Therefore, the modes for the drivers and receivers are identical in the application. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. Table 1 shows the mode of each receiver in the different interface modes that can be selected. There are two basic types of receiver circuits--ITU-T-V .28 (RS-232) and ITU-T-V.11, (RS-422). The RS-232 (V.28) receiver is single-ended and accepts RS-232 signals from the RS-232 driver. The RS-232 receiver has an operating input voltage range of +15V and can receive signals downs to +3V. The input sensitivity complies with RS-232 and V.28 at +3V. The input impedance is 3k to 7k in accordance to RS232 and V.28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic "1" and a +0.4V maximum for a logic "0". The RS-232 (V.28) protocol uses these receivers for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate over 120kbps. The second type of receiver is a differential type that can be configured internally to support ITU-T-V.10 and CCITT-V.35 depending on its input conditions. This receiver has a typical input impedance of 10k and a differential threshold of less than +200mV, which complies with the ITU-T-V.11 (RS-422) specifications. V.11 receivers are used in RS-449/V.36, EIA-530, EIA-530A and X.21 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential V.11 transceiver has improved architecture that allows over 20Mbps transmission rates. Receivers dedicated for data and clock (RxD, RxC, TxC) incorporate internal termination for V.11. The termination resistor is typically 120 connected between the A and B inputs. The termination is essential for minimizing crosstalk and signal reflection over the transmission line . The minimum value is guaranteed to exceed 100, thus complying with the V.11 and RS-422 specifications. This resistor is invoked when the receiver is operating as a V.11 receiver, in modes EIA-530, EIA-530A, RS-449/V.36, and X.21. Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 23 FEATURES The same receivers also incorporate a termination network internally for V.35 applications. For V.35, the receiver input termination is a "Y" termination consisting of two 51 resistors connected in series and a 124 resistor connected between the two 50 resistors and GND. The receiver itself is identical to the V.11 receiver. The differential receivers can be configured to be ITU-T-V.10 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V10GND and can be grounded separately. The ITU-T-V.10 receivers can operate over 120Kbps and are used in RS-449/V.36, E1A530, E1A-530A and X.21 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/ disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on Figure 44. The receiver's enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs. All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. For single-ended V.28 and V.10 receivers, there are internal 5k pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. The differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic HIGH ("1") at the receiver output. CHARGE PUMP SP3508 uses an internal capacitive charge pump to generate Vdd and Vss. The design is Sipex patented (5,306,954) four-phased voltage shifting charge pump converters that converts the input voltage of 3.3V to nominal output voltages of +/-6V (Vdd & Vss1). SP3508 also includes an inverter block that inverts Vcc to -Vcc (Vss2). There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. 4-phased doubler pump Phase 1 -VSS1 charge storage -During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C1+ is then switched to ground and the charge in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2xVCC. VCC = +3V +3V C1 + - CVDD + - + C2 + - - VDD Storage Capacitor VSS1 Storage Capacitor -3V -3V CVSS1 Figure 45. Charge Pump - Phase 1. Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 24 FEATURES Phase 2 -VSS1 transfer -Phase two of the clock connects the negative terminal of C2 to the VSS1 storage capacitor and the positive terminal of C2 to ground, and transfers the negative generated voltage to CVSS1. This generated voltage is regulated to -5.5V. Simultaneously, the positive side of the capacitor C1 is switched to VCC and the negative side is connected to ground. VCC = +3V CVDD + - + C1 + - C2 + - - VDD Storage Capacitor VSS Storage Capacitor -6V CVSS1 Figure 46. Charge Pump - Phase 2. Phase 3 -VDD charge storage -The third phase of the clock is identical to the first phase-the charge transferred in C1 produces -VCC in the negative terminal of C1 which is applied to the negative side of the capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2xVCC. VCC = +3V CVDD + - + +3V C1 + - C2 + - - VDD Storage Capacitor VSS1 Storage Capacitor -3V -3V CVSS1 Figure 47.Charge Pump - Phase 3. Phase 4 -VDD transfer -The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated 5.5V across C2 to CVDD, the VDD storage capacitor. This voltage is regulated to +5.5V. At the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor C1 is switched to VCC and the negative side is connected to ground, and the cycle begins again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 1F with a 16V breakdown voltage rating. Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 25 FEATURES VCC = +3V +6V C1 + - CVDD + - + C2 + - - VDD Storage Capacitor VSS1 Storage Capacitor CVSS1 Figure 48. Charge Pump - Phase 4. 2-phased inverter pump Phase 1 Please refer to figure below: In the first phase of the clock cycle, switches S2 and S4 are opened and S1 and S3 closed. This connects the flying capacitor, C3, from Vin to ground. C3 charge up to the input voltage applied at Vcc. Phase 2 In the second phase of the clock cycle, switches S2 and S4 are closed and S1 and S3 are opened. This connects the flying capacitor, C3, in parallel with the output capacitor, CVSS2. The Charge stored in C3 is now transferred to CVSS2. Simultaneously, the negative side of CVSS2 is connected to VSS2 and the positive side is connected to ground. With the voltage across CVSS2 smaller than the voltage across C3, the charge flows from C3 to CVSS2 until the voltage at the VSS2 equals -VCC. VSS2 = -VCC VCC S1 C3 + S2 + CVSS2 S3 Figure 49. Circuit for an Ideal Voltage Inverter. S4 VSS2 Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 26 DCE CONFIGURATION SP3508 Multiprotocol Configured as DCE Interface to PortInterface to System Logic Connector Pin Pin Number Pin Mnemonic Circuit Pin Mnemonic Number 31 TxD Driver_1 SD(A) 97 2 SDEN SD(B) 99 32 TxCE Driver_2 TT(A) 93 3 TTEN TT(B) 95 33 ST Driver_3 ST(A) 89 4 STEN ST(B) 91 34 RTS Driver_4 RS(A) 81 5 RSEN RS(B) 83 35 DTR TR(A) Driver_5 85 6 TREN TR(B) 87 36 DCD_DCE RRC(A) Driver_6 79 7 RRCEN RRC(B) 77 37 RL RL(A) Driver_7 67 8 RLEN 38 LL LL(A) Driver_8 65 9 LLEN# 39 RxD RD(A) 50 Receiver_1 10 RDEN# RD(B) 49 40 RxC RT(A) 52 Receiver_2 11 RTEN# RT(B) 51 41 TxC TxC(A) 55 Receiver_3 12 TxCEN# TxC(B) 53 42 CTS CS(A) 57 Receiver_4 13 CSEN# CS(B) 56 43 DSR DM(A) 59 Receiver_5 14 DMEN# DM(B) 58 44 DCD_DTE RRT(A) 62 Receiver_6 15 RRTEN# RRT(B) 61 45 RI IC 63 Receiver_7 16 ICEN# 46 TM TM(A) 64 Receiver_8 17 TMEN Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver Recommended Signals and Port Pin Assignments RS-232 or V.24 EIA-530 RS-449 V.35 X.21 Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34 Signal Mnemo DB-15 Type nic Pin(F) Type nic Pin(F) Type Pin(F) Type nic nic Pin(F) Type nic Pin(F) V.28 BB 3 V.11 BB(A) 3 V.11 RD(A) 6 V.35 104 R V.11 R(A) 4 V.11 BB(B) 16 V.11 RD(B) 24 V.35 104 T V.11 R(B) 11 V.28 DD 17 V.11 DD(A) 17 V.11 RT(A) 8 V.35 115 V V.11 B(A) 7** V.11 DD(B) 9 V.11 RT(B) 26 V.35 115 X V.11 B(B) 14** V.28 DB 15 V.11 DB(A) 15 V.11 ST(A) 5 V.35 114 Y V.11 S(A) 6 V.11 DB(B) 12 V.11 ST(B) 23 V.35 114 AA V.11 S(B) 13 V.28 CB 5 V.11 CB(A) 5 V.11 CS(A) 9 V.28 106 D V.11 I(A) 5 V.11 CB(B) 13 V.11 CS(B) 27 V.11 I(B) 12 V.28 CC 6 V.11 CC(A) 6 V.11 DM(A) 11 V.28 107 E V.11 CC(B) 22 V.11 DM(B) 29 V.28 CF 8 V.11 CF(A) 8 V.11 RR(A) 13 V.28 109 F V.11 CF(B) 10 V.11 RR(B) 31 V.28 CE 22 V.28 125 J V.28 V.28 V.28 TM BA DA 25 2 24 V.10 V.11 V.11 V.11 V.11 TM BA(A) BA(B) DA(A) DA(B) 25 2 12 24 11 V.10 V.11 V.11 V.11 V.11 TM SD(A) SD(B) TT(A) TT(B) 18 4 22 17 35 V.28 V.35 V.35 V.35 V.35 142 103 103 113 113 NN P S U W V.11 V.11 V.11 V.11 T(A) T(B) X(A) X(B) 2 9 7** 14** SP3508 Enhanced WAN Multi-Mode Serial Transceiver Date: 06/14/04 (c) Copyright 2004 Sipex Corporation V.28 V.28 CA CD 4 20 V.11 V.11 V.11 V.11 CA(A) CA(B) CD(A) CD(B) 4 19 20 23 V.11 V.11 V.11 V.11 RS(A) RS(B) TR(A) TR(B) 7 25 12 30 V.28 V.28 105 108 C H V.11 V.11 C(A) C(B) 3 10 V.28 V.28 RL LL 21 18 V.10 V.10 RL LL 21 18 V.10 V.10 RL LL 14 10 V.28 V.28 140 141 N L Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations ** X.21 use either B() or X(), not both Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 27 27 SP3508 Multiprotocol Configured as DTE Interface to PortConnector Interface to System Logic Pin Number 31 2 32 3 33 4 34 5 35 6 36 7 37 8 38 9 39 10 40 11 41 12 42 13 43 14 44 15 45 16 46 17 Pin Mnemonic TxD SDEN TxCE TTEN ST STEN RTS RSEN DTR TREN DCD_DCE RRCEN RL RLEN LL LLEN# RxD RDEN# RxC RTEN# TxC TxCEN# CTS CSEN# DSR DMEN# DCD_DTE RRTEN# RI ICEN# TM TMEN Circuit Driver_1 Driver_2 Driver_3 Driver_4 Driver_5 Driver_6 Driver_7 Driver_8 Receiver_1 Receiver_2 Receiver_3 Receiver_4 Receiver_5 Receiver_6 Receiver_7 Receiver_8 Pin Mnemonic SD(A) SD(B) TT(A) TT(B) ST(A) ST(B) RS(A) RS(B) TR(A) TR(B) RRC(A) RRC(B) RL(A) LL(A) RD(A) RD(B) RT(A) RT(B) TxC(A) TxC(B) CS(A) CS(B) DM(A) DM(B) RRT(A) RRT(B) IC TM(A) Pin Number 97 99 93 95 89 91 81 83 85 87 79 77 67 65 50 49 52 51 55 53 57 56 59 58 62 61 63 64 Recommended Signals and Port Pin Assignments RS-232 or V.24 EIA-530 RS-449 V.35 X.21 Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34 Signal Mnemo DB-15 Pin(M) nic Pin(M) Type nic Pin(M) Type nic Pin(M) Type nic Pin(M) Type nic Type 2 T(A) V.11 P 103 V.35 4 V.11 SD(A) 2 V.11 BA(A) 2 BA V.28 9 T(B) V.11 S 103 V.35 22 V.11 SD(B) 12 V.11 BA(B) 7** X(A) V.11 U 113 V.35 17 TT(A) V.11 24 V.11 DA(A) 24 DA V.28 14** X(B) V.11 W 113 V.35 35 TT(B) V.11 11 V.11 DA(B) V.28 V.28 CA CD 4 20 V.11 V.11 V.11 V.11 CA(A) CA(B) CD(A) CD(B) 4 19 20 23 V.11 V.11 V.11 V.11 RS(A) RS(B) TR(A) TR(B) 7 25 12 30 V.28 V.28 105 108 C H V.11 V.11 C(A) C(B) 3 10 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 RL LL BB DD DB CB CC CF CE TM 21 18 3 17 15 5 6 8 22 25 V.10 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 RL LL BB(A) BB(B) DD(A) DD(B) DB(A) DB(B) CB(A) CB(B) CC(A) CC(B) CF(A) CF(B) 21 18 3 16 17 9 15 12 5 13 6 22 8 10 V.10 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 RL LL RD(A) RD(B) RT(A) RT(B) ST(A) ST(B) CS(A) CS(B) DM(A) DM(B) RR(A) RR(B) 14 10 6 24 8 26 5 23 9 27 11 29 13 31 V.28 V.28 V.35 V.35 V.35 V.35 V.35 V.35 V.28 V.28 V.28 V.28 140 141 104 104 115 115 114 114 106 107 109 125 142 N L R T V X Y AA D E F J NN V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 R(A) R(B) B(A) B(B) S(A) S(B) I(A) I(B) 4 11 7** 14** 6 13 5 12 SP3508 Enhanced WAN Multi-Mode Serial Transceiver Date: 06/14/04 (c) Copyright 2004 Sipex Corporation DTE CONFIGURATION V.10 TM 25 V.10 TM 18 V.28 Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations ** X.21 use either B() or X(), not both Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 28 28 FEATURES TERM_OFF FUNCTION The SP3508 contains a TERM_OFF pin that disables all three receiver input termination networks regardless of mode. This allows the device to be used in monitor mode applications typically found in networking test equipment. The TERM_OFF pin internally contains a pulldown device with an impedance of over 500k, which will default in a "ON" condition during power-up if V.35 receivers enable line and the SHUTDOWN mode from the decoder will disable the termination regardless of TERM_OFF. LOOPBACK FUNCTION The SP3508 contains a LOOPBACK pin that invokes a loopback path. This loopback path is illustrated in Figure 50. LOOPBACK has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. During loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. DECODER AND D_LATCH FUNCTION The SP3508 contains a D_LATCH pin that latches the data into the D0, D1 and D2 decoder inputs. If tied to a logic LOW ("0"), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP3508 accordingly. If tied to a logic HIGH ("1"), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic LOW. There are internal pull-up devices on D0, D1 and D2, which allow the device to be in SHUTDOWN mode ("111") upon power up. However, if the device is powered-up with the D_LATCH at a logic HIGH, the decoder state of the SP3508 will be undefined. CTR1/CTR2 EUROPEAN COMPLIANCY As with all of Sipex's previous multi-protocol serial transceiver IC's the drivers and receivers have been designed to meet all the requirements to NET1/NET2 and TBR2 in order to meet CTR1/ CTR2 compliancy. The SP3508 is also tested inhouse at Sipex and adheres to all the NET1/2 physical layer testing and the ITU Series V specifications before shipment. Please note that although the SP3508, as with its predecessors, adhere to CRT1/CTR2 compliancy testing, any complex or usual configuration should be doublechecked to ensure CTR1/CTR2 compliance. Consult the factory for details. Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 29 97 TxD 31 99 50 RxD 39 49 93 TxCE 32 95 52 RxC 40 51 89 ST 33 91 55 TxC 41 53 81 RTS 34 83 57 CTS 42 56 85 DTR 35 87 59 DSR 43 58 79 DCD_DCE 36 77 62 DCD_DTE 44 61 SD(a) SD(b) RD(a) RD(b) TT(a) TT(b) RT(a) RT(b) ST(a) ST(b) TxC(a) TxC(b) RS(a) RS(b) CS(a) CS(b) TR(a) TR(b) DM(a) DM(b) RRC(a) RRC(b) RRT(a) RRT(b) RL 37 67 RL(a) RI 45 63 IC LL 38 65 LL(a) TM 46 64 TM(a) Figure 50. Loopback Path Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 30 CVDD 1F C1 1F C2 1F +3.3V 10F VCC 76 VDD 74 C1+ C1- C2+ C2- C3+ 24 C3- 26 VSS1 70 72 69 1F C3 CVSS1 68 27 CVSS2 +3.3V 29 AV CC 31 32 Charge Pump Section Transceiver Section VSS2 DB-26 Serial Port Connector Pins 2 (V.11, V.35, V.28) 14 (V.11, V.35) 24 (V.11, V.35, V.28) 11 (V.11, V.35) 4 (V.11, V.28) 19 (V.11) 20 (V.11, V.28) 23 (V.11) Signal (DTE_DCE) TXD_RXD_A TXD_RXD_B TXCE_TXC_A TXCE_TXC_B RTS_CTS_A RTS_CTS_B DTR_DSR_A DTR_DSR_B TxD TxCE ST RTS DTR SD(a) 97 SD(b) 99 TT(a) 93 TT(b) 95 ST(a) 89 ST(b) 91 RS(a) 81 RS(b) 83 TR(a) 85 TR(b) 87 RRC(a) 79 RRC(b) 77 RL(a) 67 LL(a) 65 RD(a) 50 RD(b) 49 RT(a) 52 RT(b) 51 TxC(a) 55 TxC(b) 53 CS(a) 57 CS(b) 56 DM(a) 59 DM(b) 58 RRT(a) 62 RRT(b) 61 IC 63 TM(a) 64 Logic Section 18 19 20 21 22 30 33 34 35 36 37 38 DCD_DCE RL LL 21 (V.10, V.28) 18 (V.10, V.28) 3 (V.11, V.35, V.28) 16 (V.11, V.35) 17 (V.11, V.35, V.28) 9 (V.11, V.35) 15 (V.11, V.35, V.28) 12 (V.11, V.35) 5 (V.11, V.28) 13 (V.11) 6 (V.11, V.28) 22 (V.11) 8 (V.11, V.28) 10 (V.11) 22 (V.10, V.28) 25 (V.10, V.28) RL_RI LL_TM RXD_TXD_A RXD_TXD_B RXC_TXCE_A RXC_TXCE_B *TXC_RXC_A *TXC_RXC_B CTS_RTS_A CTS_RTS_B DSR_DTR_A DSR_DTR_B DCD_DCD_A DCD_DCD_B RI_RL LL_TM 39 40 RxD RxC TxC 41 42 43 44 45 46 CTS DSR DCD_DTE RI TM +3.3V DCE/DTE 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN RDEN RTEN TxCEN CSEN DMEN RRTEN ICEN TMEN D0 SP3508CF D1 D2 D_LATCH TERM_OFF LOOPBACK +3.3V AGND GND 28 * - Driver applies for DCE only on pins 15 and 12. Receiver applies for DTE only on pins 15 and 12. Driver applies for DCE only on pins 8 and 10. Receiver applies for DTE only on pins 8 and 10. Input Line Output Line I/O Lines represented by double arrowhead signifies a bi-directional bus. Figure 51. SP3508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 31 PACKAGE: 100 PIN LQFP D D1 0.2 RAD MAX. c 0.08 RAD MIN. PIN 1 11-13 0MIN C L E1 E 0-7 11-13 L L1 C L A2 b DIMENSIONS Minimum/Maximum (mm) SYMBOL A A1 A2 b D D1 e E E1 N 0.05 1.35 0.17 1.40 0.22 A e 100-PIN LQFP JEDEC MS-026 (BED) Variation MIN NOM MAX 1.60 0.15 1.45 0.27 A1 Seating Plane COMMON DIMENSIONS SYMBL MIN NOM c L L1 0.09 0.45 0.60 1.00 REF MAX 0.20 0.75 16.00 BSC 14.00 BSC 0.50 BSC 16.00 BSC 14.00 BSC 100 100 PIN LQFP Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 32 ORDERING INFORMATION Part Number Temperature Range Package Types SP3508CF ............................................. 0C to +70C ................................................. 100-pin JEDEC LQFP SP3508EF ......................................... -40C to +85C ................................................. 100-pin JEDEC LQFP Available in lead free packaging. To order add "-L" suffix to part number. Example: SP3508EF = standard; SP3508EF-L = lead free REVISION HISTORY DATE 1/12/04 2/27/04 REVISION A B DESCRIPTION Implemented tracking revision. Included Diamond column in spec table indicating which specs apply over full operating temp. range. In figure 51, fixed typo on pin 61 and 62 from an input line to a bidirectional bus. Corrected max dimension for symbol c on LQFP package. Added tables to page 27 and 28. 3/31/04 6/3/04 C D Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver (c) Copyright 2004 Sipex Corporation 33 |
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