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RT9173/A
1.5A/3A Bus Termination Regulator
General Description
The RT9173/A regulator is designed to convert voltage supplies ranging from 1.8V to 6V into a desired output voltage which adjusted by two external resistors, voltage divider. The regulator is capable of sourcing or sinking up to 1.5A/3A of current while regulating an output voltage to within 2% or less. The RT9173/A, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for DDR SDRAM. Current limits in both sourcing and sinking mode, plus on-chip thermal shutdown make the circuit tolerant of the output fault conditions.
Features
Support Both DDR 1 (1.25VTT) and DDR 2 (0.9VTT) Requirements Power TO-263-5 and SOP-8 Packages Capable of Sourcing and Sinking Current 1.5A/3A Current-limiting Protection Thermal Protection Integrated Power MOSFETs Generates Termination Voltages for SSTL-2 High Accuracy Output Voltage at Full-load Adjustable VOUT by External Resistors Minimum External Components Shutdown for Standby or Suspend Mode Operation with High-impedance Output
Pin Configurations
Part Number RT9173ACM5 (Plastic TO-263-5) Pin Configurations
TOP VIEW 1. 2. 3. 4. 5. VIN GND VCNTL (TAB) REFEN VOUT
Applications
Computers Disk Drives CD-ROM Supply Splitter Graph Card
12 34 5
RT9173CS (Plastic SOP-8)
TOP VIEW
VIN 1 GND 2
8 7 6 5
Ordering Information
RT9173/A Package type M5 : TO-263-5 S : SOP-8 Operating temperature range C: Commercial standard 3A sink & source 1.5A sink & source
VCNTL VCNTL VCNTL VCNTL
REFEN 3 VOUT 4
Function Block Diagram
VCNTL VIN
Current Limiting Sensor REFEN Thermal GND
CNTL
VOUT
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RT9173/A
Pin Description
Pin Name VIN GND VCNTL REFEN VOUT Power Input Ground Gate Drive Voltage Reference Voltage Input and Chip Enable Output Voltage Pin Function
Absolute Maximum Ratings
Input Voltage Power Dissipation ESD Rating Storage Temperature Range Lead Temperature (Soldering, 5 sec.) Package Thermal Resistance TO-263,JC TO-263,JA SOP-8, JC SOP-8, JA
Note
7V Internally Limited 2KV -65C to 150C 260C 7.7C/W 19.4C/W 15.7C/W 45C/W
2
Note: JA is measured with the component mounted on an evaluation PC board in free air that the required area of copper is 300mm or larger.
Electrical Characteristics
(Limits in standard typeface are for TA = 25C, unless otherwise specified: VIN = 2.5V, VCNTL = 3.3V, VREFEN = 1.25V, COUT = 10F (Ceramic)) Parameter Output Offset Voltage Load Regulation Input Voltage Range (DDR 1) Current In Shutdown Mode Short Circuit Protection Current limit RT9173 RT9173A ILIMIT Fig.3,4 Fig.3,4 3.3V VCNTL 5V Guaranteed by design Output = High, Fig.5 Output = Low, Fig.5 2.1 3.0 125 -0.8 ---150 50 -------0.2 A Symbol VOS VLOAD VIN VCNTL ISHDN Fig.1 IL : 0 1.5A, Fig.1 IL : 0A -1.5A Keep VCNTL VIN on operation power on and power off sequences VREFEN < 0.2V, RL = 180, Fig.2 Test Conditions Min -20 --1.8 --Typ 0 0.8 0.8 2.5 3.3 50 Max 20 2 2 -6 90 Units mV % V A
Over Temperature Protection Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis Shutdown Function Shutdown Threshold Trigger V C C
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RT9173/A
Typical Application Circuit
VCNTL= 3.3V VIN = 2.5V R1 2N7002 EN R2 CSS VIN VCNTL RT9173/A REFEN VOUT GND CCNTL CIN COUT RDUMMY RTT
R1 = R2 = 100K, RTT = 50 / 33 / 25 COUT,min = 10F (Ceramic) + 1000F under the worst case testing condition RDUMMY = 1k as for VOUT discharge when VIN is not present but VCNTL is present CSS = 1F, CIN = 470F (Low ESR), CCNTL = 47F
Test Circuit
2.5V 3.3V
VIN 1.25V REFEN GND
VCNTL RT9173/A VOUT
VOUT
IL
V COUT
Fig.1 Output Voltage Tolerance, VOUT
2.5V
A VIN
3.3V
VCNTL RT9173/A VOUT GND RL
1.25V 0.2V
REFEN
VOUT
1.25V 0V
V COUT
RL and COUT Time delay
Fig.2 Current in Shutdown Mode, ISHCLN
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RT9173/A
2.5V 3.3V
VIN 1.25V REFEN RT9173/A GND
VCNTL VOUT A IL
VOUT
V COUT
Fig.3 Current Limit for High Side, ICLHIGH
Power supply with current limit 2.5V VIN 1.25V REFEN GND
3.3V VCNTL RT9173/A VOUT
A IL
VOUT
V COUT
Fig.4 Current Limit for Low Side, ICLLOW
3.3V 2.5V VIN 1.25V VREFEN 0.2V REFEN VCNTL VOUT RL 1.25V VOUT 0V RL and COUT Time delay VOUT would be low if VREFEN < 0.2V VOUT would be high if VREFEN > 0.8V GND V COUT
RT9173/A
VOUT
Fig.5 REFEN Pin Shutdown Threshold, VTRIGGER
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RT9173/A
Typical Operating Characteristics
Sourcing Current (Peak) vs. Temp.
8.0 7.0
Sinking Current (Peak) vs. Temp.
8.0 7.0
Sourcing Current (A)
Sinking Current (A) VCNTL = 3.3V VIN = 2.5V VOUT = 1.25V
-40 -20 0 60 80 Temperature ( C) 20 40 100 120
6.0 5.0 4.0 3.0 2.0 1.0 0.0
6.0 5.0 4.0 3.0 2.0 1.0 0.0 -40 -20 0 20 40 60
VCNTL = 3.3V VIN = 2.5V VOUT = 1.25V
80 100 120
Temperature ( C)
Turn-On Threshold vs. Temp.
700 650 700 650
Turn-On Threshold vs. Temp.
Threshold Voltage (mV)
600 550 500 450 400 -40 -20 0 60 Temperature ( C) 20 40
Threshold Voltage (mV) VCNTL = 3.3V VIN = 2.5V
80 100 120
600 550 500 450 400 -40 -20 0 20 40 60
VCNTL = 5.0V VIN = 2.5V
80 100 120
Temperature ( C)
Transient Response
Output Transient Voltage (mV) 100 VIN = 2.5V 50 VREFEN = 1.25V 0 -50 2 1 0 -1 -2 Time (250S/Div) VCNTL = 3.3V Swing Frequency = 1KHz Output Short Circuit (A) 12 10 8 6 4 2 0 -2 -4 Time (5mS/Div) Force the output shorted to ground VIN = 2.5V VCNTL = 3.3V VREFEN = 1.25V
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Output Current (A)
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RT9173/A
Applications Information
Internal parasitic diode Avoid forward-bias internal parasitic diode, VOUT to VCNTL, and VOUT to VIN, the VOUT should not be forced some voltage respect to ground on this pin while the VCNTL or VIN is disappeared. Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on REFEN is below 0.2V. In addition to item 1, the capacitor and voltage divider form the low-pass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? In notebook application, using RichTek's Patent "Distributed Bus Terminator Topology" with choosing RichTek's product is encouraged. Thermal Consideration RT9173/A regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continuous normal load conditions however, the maximum junction temperature rating of 125C must not be exceeded. Higher continous currents or ambient temperature require additional heatsinking. Heat sinking to the IC package must consider the worst case power dissipation which may occur. It should also be note that with the VCNTL equal to 5V, the point of thermal shutdown will be degraded by approx. 20C compared to the VCNTL equipped with 3.3V. It is highly recommended that to use the 3.3V rail acted as the VCNTL so as to minimize the thermal concern of the RT9173CS in the SOP-8 package. Layout Consideration The RT9173CS regulator is packaged in plastic SOP8 package. This small footprint package is unable to convectively dissipate the heat generated when the regulator is operating at high current levels. In order
Distributed Bus Terminating Topology Terminator Resistor
R0 R1 R2 R3 BUS(0) BUS(1) BUS(2) BUS(3) BUS(4) BUS(5) BUS(6) BUS(7) BUS(8) BUS(9)
to control die operating temperatures, the PC board layout should allow for maximum possible copper area at the VCNTL pins of the RT9173CS. The multiple VCNTL pins on the SOP-8 package are internally connected, but lowest thermal resistance will result if these pins are tightly connected on the PC board. This will also aid heat dissipation at high power levels. If the large copper around the IC is unavailable, a buried layer may be used as a heat spreader, Use vias to conduct the heat into the buried or backside of PCB layer. The vias should be small enough to retain solder when the board is wave-soldered. (See Fig.6 shown on next page).
RT9173
VOUT
REFEN
R4 R5 R6
RT9173
VOUT
R7 R8 R9
RN RN1
BUS(N+1) BUS(N)
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RT9173/A
Use vias to conduct the heat into the buried or backside of PCB layer .
RT9173CS (SOP-8)
The PCB heat sink copper area should be solder-painted without masked. This approaches a "best case" pad heat sink.
Fig. 6 Layout Consideration To prevent this maximum junction temperature from being exceeded, the appropriate power plane heat sink MUST be used. Higher continuous currents or ambient temperature require additional heatsinking.
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RT9173/A
Package Information
D B MARK L1 A C
E
L2 e
b
b2
U
V
Symbol D B E A C U V L1 L2 b b2 e
Dimensions In Millimeters Min 9.652 1.143 8.128 4.064 1.143 Max 10.668 1.676 9.652 4.826 1.397
Dimensions In Inches Min 0.380 0.045 0.320 0.160 0.045 Max 0.420 0.066 0.380 0.190 0.055
6.223 Ref. 7.620 Ref. 14.605 2.286 0.660 0.305 1.524 15.875 2.794 0.914 0.584 1.829
0.245 Ref. 0.300 Ref. 0.575 0.090 0.026 0.012 0.060 0.625 0.110 0.036 0.023 0.072
5-Lead TO-263 Plastic Surface Mount Package
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RT9173/A
H A M
JB
F
C D I
Symbol A B C D M F I J H
Dimensions In Millimeters Min 4.801 3.810 1.346 0.330 0.406 1.194 0.102 5.791 0.178 Max 5.004 3.988 1.753 0.508 1.270 1.346 0.254 6.198 0.254
Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.016 0.047 0.004 0.228 0.007 Max 0.197 0.157 0.069 0.020 0.050 0.053 0.010 0.244 0.010
8-Lead SOP Plastic Package
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RT9173/A
RICHTEK TECHNOLOGY CORP.
Headquarter
6F, No. 35, Hsintai Road, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5510047 Fax: (8863)5537749
RICHTEK TECHNOLOGY CORP.
Taipei Office (Marketing)
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek-ic.com.tw
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