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| Datasheet File OCR Text: |
| DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS Rating -1 to +7.0 -1 to +7.0 -55 to +125 12 50 KMM372C804BS Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC*1 0.8 Unit V V V V *1 : VCC+2.0V at pulse width20ns, which is measured at VCC. *2 : -2.0V at pulse width20ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM372C804BS Min - Max 760 700 100 760 700 540 480 30 760 700 10 10 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -10 -10 2.4 - ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Fast Page mode cycle time, tPC. DRAM MODULE CAPACITANCE (TA = 25C, f = 1MHz) Item Input capacitance[A0, B0, A1 - A11] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0 - RAS3] Input capacitance[CAS0, 1,4,5] Input/Output capacitance[DQ0 - 71] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - KMM372C804BS Max 20 20 31 20 24 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referencde to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data in set-up time Data in hold time Refresh period Write command set-up time CAS to W delay time Column address to W delay time CAS prechange to W delay time Symbol -5 Min 90 133 50 18 30 5 5 1 30 50 18 45 13 18 13 10 5 8 0 10 30 0 0 -2 10 10 20 13 -2 15 64 0 36 48 53 0 40 55 60 10K 32 20 10K 18 50 5 5 1 40 60 20 55 15 18 13 10 5 8 0 10 35 0 0 -2 10 10 20 15 -2 15 64 10K 40 25 10K 20 50 Max Min 110 155 60 20 35 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 7 7,15 7 7 11 15 9,11 9,11 8 8,11 4,11 10,11 11 11 11 12 12 11 11 11 3,4 3,4,5,11 3,10,11 3,11 6,11 2 Note tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tAWD tCPWD DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Parameter RAS ro W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast page mode cycle time Fast page mode read-modify-write cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive Symbol -5 Min 73 10 8 3 35 35 76 10 50 35 15 8 18 18 5 13 18 20 5 15 200K 40 85 10 60 40 15 8 Max Min 85 10 8 3 -6 KMM372C804BS Max Unit ns ns ns ns Note 7,11 11,16 11 11 3,11 tRWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH 40 ns ns ns ns 13 11 11 11 11 11 11 200K ns ns ns ns 20 20 ns ns ns ns tPD tPDOFF 10 2 7 2 10 7 ns ns DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWDtRWD(min), tCWDtCWD(min), tAWDtAWD(min) and tCPWDtCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. KMM372C804BS 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. 12. tASC, tCAH are referenced to the earlier CAS falling edge. 13. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 14. tCWD is referenced to the later CAS falling edge at word readmodify-write cycle. 15. tCWL is specified from W falling edge to the earlier CAS rising edge. 16. tCSR is referenced to earlier CAS falling low before RAS transition low. DRAM MODULE READ CYCLE KMM372C804BS tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tOFF tAA tOEZ tOEA tCAC OE VIH VIL - DQ VOH VOL - tRAC OPEN tCLZ DATA-OUT Dont care Undefined DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM372C804BS tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tASR A VIH VIL - tRAD tRAH tASC ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN KMM372C804BS tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tASR A VIH VIL - tRAH tASC ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined DRAM MODULE READ - MODIFY - WRTIE CYCLE KMM372C804BS tRWC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tCAH tCSH tASR VIH VIL - tASC COLUMN ADDRESS A ROW ADDR tAWD tCWD W VIH VIL - tRWL tCWL tWP OE VIH VIL - tRWD tOEA tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT tDS tDH DQ VI/OH VI/OL - tRAC VALID DATA-IN Dont care Undefined DRAM MODULE FAST PAGE READ CYCLE NOTE : DOUT = OPEN KMM372C804BS tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCSH tCAH COLUMN ADDRESS tCP tCAS o tCP tRSH tCAS tASR A VIH VIL ROW ADDR tRAH tASC tCAH o o tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tRCS o tRCS tRCH OE VIH VIL - tCAC tOEA tCAC tOEA o o tCAC tOEA tAA tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ VALID DATA-OUT tOFF tOEZ DQ VOH VOL - Dont care Undefined DRAM MODULE FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM372C804BS tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCP tPC tCP tCAS o tRSH tCAS tASR A VIH VIL - tRAH tCSH tCAH COLUMN ADDRESS tASC tCAH o o tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tCWL tWCS tWP tWCH o tWCS tWCH tWP tCWL tRWL tCWL o o OE VIH VIL - tDS DQ VIH VIL - tDH tDS tDH o tDS tDH VALID DATA-IN VALID DATA-IN VALID DATA-IN o Dont care Undefined DRAM MODULE FAST PAGE READ - MODIFY - WRITE CYCLE KMM372C804BS tRASP RAS VIH VIL - tRP tCSH tRCD tRSH tCP tCAS tRAD tRAH tASR tASC COL. ADDR tCRP tCAS tPRWC CAS VIH VIL - tCAH tRAL tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tCPWD tOEA tCAC tAA tOEZ tOED tDH tDS tCWL tWP OE VIH VIL - tRAC DQ VI/OH VI/OL - tCLZ VALID DATA-OUT tCLZ VALID DATA-IN VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC KMM372C804BS tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM372C804BS tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tRCS W VIH VIL - tRRH tWRP tAA OE VIH VIL - tOEA tCAC tRAC tCLZ tOEZ DATA-OUT tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM372C804BS tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR tRAH tASC tCAH COLUMN ADDRESS A VIH VIL - ROW ADDRESS tWRH tWRP W VIH VIL - tWCS tWP tWCH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM372C804BS tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL VIH VIL - tWRP tWRH tAA tRCS tCAC tRRH tRCH OE DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tOFF WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tCWL tWCS tRWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tAWD tRCS tCAC tAA tOEA tCWD tWP tCWL tRWL OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. Undefined DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM372C804BS tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CAS VIH VIL - tCSR tOFF DQ VOH VOL - OPEN tWRP tWRH W VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWTS tWTH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE PACKAGE DIMENSIONS KMM372C804BS Units : Inches (millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) 0.054 (1.372) R 0.079 (R 2.000) 0.1570.004 (4.0000.100) 1.000 (25.40) 0.118 (3.000) .118DIA.004 (3.000DIA.100) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) ( Front view ) 0.150Max (3.81Max) 0.157 Min (3.99 Min) (2.540Min) 0.100Min A B C 0.700 (17.780) ( Back view ) 0.0500.0039 (1.2700.10) 0.250 (6.350) 0.250 (6.350) (2.540 Min) 0.100 Min 0.039.002 (1.000.050) 0.1230.0050 (3.125.125) 0.1230.0050 (3.125.125) 0.079.0040 (2.000.100) 0.01Max (0.25 Max) 0.050 (1.270) 0.079.0040 (2.000.100) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 4Mx16 & 4Mx4 DRAM with Fast Page mode, TSOP II. DRAM Part No. : KMM372C804BS -KM416C4100BS & KM44C4000CS |
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