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FEATURES 10-Bit, 18 MSPS A/D Converter 18 MSPS Full Speed Correlated Double Sampler (CDS) Low Noise, Wideband PGA Internal Voltage Reference No Missing Codes Guaranteed +3 V Single Supply Operation Low Power CMOS: 185 mW 48-Terminal TQFP Package
PBLK PIN DIN ADCIN
CCD Signal Processor For Electronic Cameras AD9802
FUNCTIONAL BLOCK DIAGRAM
CLPDM PGACONT1 PGACONT2 SHP SHD ADCCLK TIMING GENERATOR PGA 10 MUX S/H A/D DOUT DRVDD
CLAMP CDS
CLAMP REFERENCE
AD9802
DVDD
CMLEVEL VRT VRB STBY CLPOB ADCMODE ACVDD ADVDD
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9802 is a complete CCD signal processor developed for electronic cameras. It is suitable for both camcorder and consumer-level still camera applications. The signal processing chain is comprised of a high speed CDS, variable gain PGA and 10-bit ADC. Required clamping circuitry and an onboard voltage reference are provided as well as a direct ADC input. The AD9802 operates from a single +3 V supply with a typical power consumption of 185 mW. The AD9802 is packaged in a space saving 48-terminal thin quad flatpack (TQFP) and is specified over an operating temperature range of 0C to +70C.
1. On-Chip Input Clamp and CDS Clamp circuitry and high speed correlated double sampler allow for simple ac-coupling to interface a CCD sensor at full 18 MSPS conversion rate. 2. On-Chip PGA The AD9802 includes a low-noise, wideband amplifier with analog variable gain from 0 dB to 31.5 dB (linear in dB). 3. Direct ADC Input A direct input to the 10-bit A/D converter is provided for digitizing video signals. 4. 10-Bit, High Speed A/D Converter A linear 10-bit ADC is capable of digitizing CCD signals at the full 18 MSPS conversion rate. Typical DNL is 0.5 LSB and no missing code performance is guaranteed. 5. Low Power At 185 mW, and 15 mW in power-down, the AD9802 consumes a fraction of the power of presently available multichip solutions. 6. Digital I/O Functionality The AD9802 offers three-state digital output control. 7. Small Package Packaged in a 48-terminal, surface-mount thin quad flatpack, the AD9802 is well suited to very compact, low headroom designs.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997
AD9802-SPECIFICATIONS unless otherwise noted)
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE (For Functional Operation) ACVDD ADVDD DVDD DRVDD POWER SUPPLY CURRENT ACVDD ADVDD DVDD DRVDD POWER CONSUMPTION Normal Operation Power-Down Mode MAXIMUM SHP, SHD, ADCCLK RATE ADC Resolution Differential Nonlinearity No Missing Codes ADCCLK Rate Reference Top Voltage Reference Bottom Voltage Input Range CDS Maximum Input Signal Pixel Rate PGA1 Maximum Gain High Gain Medium Gain Minimum Gain CLAMP (During CLPOB. Only Stable over PGA Range 0.3 V to 2.7 V) Average Black Level Pixel-to-Pixel Offset (See Black Level Clamping for Description)
(TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V
Min 0 -65 3.00 3.00 3.00 3.00 3.15 3.15 3.15 3.15 39.5 14.6 4.7 0.07 185 15 18 10 Typ Max 70 150 3.50 3.50 3.50 3.50 Units C C V V V V mA mA mA mA mW mW MHz Bits LSBs 18 1.75 1.25 1.0 500 18 31.5 19 4.0 0 32 2 MHz V V V p-p mV p-p MHz dB dB dB dB LSBs LSBs
0.5 GUARANTEED
14.5 1.0 -4.0
23.5 7.0 +4
8
NOTES 1 PGA test conditions: maximum gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain PGACONT1 = 0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V. Specifications subject to change without notice.
DIGITAL SPECIFICATIONS noted)
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage VIH VIL IIH IIL CIN VOH VOL IOH IOL
(TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise
Symbol Min 2.4 0.6 10 10 10 2.4 0.6 50 50 -2- Typ Max Units V V A A pF V V A A REV. 0
AD9802 TIMING SPECIFICATIONS noted)
Parameter ADCCLK Clock Period ADCCLK Hi-Level Period ADCCLK Lo-Level Period SHP, SHD Clock Period SHP, SHD Minimum Pulse Width SHP Rising Edge to SHD Rising Edge Digital Output Delay
(TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise
Min 55.6 24.8 24.8 55.6 12.5 28 Typ 27.8 27.8 Max Units ns ns ns ns ns ns ns
20
Digital Output Data Control
PBLK 0 1 1 1 1
MODE1 0 0 0 1 1
MODE2 0 0 1 0 1
Digital Output Data (D9-D0) 000000 Normal Operation 101010 010101 High Impedance 0 1 0 0 0 1 0 1 0 0 0 1
ABSOLUTE MAXIMUM RATINGS*
Parameter ADVDD ACVDD DVDD DRVDD SHP, SHD ADCCLK, CLPOB, CLPDM PGACONT1, PGACONT2 PIN, DIN DOUT VRT, VRB CLAMP_BIAS CCDBYP1, CCDBYP2 STBY MODE1, MODE2 DRVSS, DVSS, ACVSS, ADVSS Junction Temperature Storage Temperature Lead Temperature (10 sec)
With Respect To ADVSS, SUBST ACVSS, SUBST DVSS, DSUBT DRVSS, DSUBST DSUBST DSUBST SUBST SUBST DSUBST SUBST SUBST SUBST DSUBST SUBST SUBST, DSUBST
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65
Max 6.5 6.5 6.5 6.5 DVDD + 2.0 DVDD + 0.3 ACVDD + 0.3 ACVDD + 0.3 DRVDD + 0.3 ADVDD + 0.3 ACVDD + 0.3 ACVDD + 0.3 DVDD + 0.3 ADVDD + 0.3 +0.3 +150 +150 +300
Units V V V V V V V V V V V V V V V C C C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
Model AD9802JST
Temperature Range 0C to +70C
Package Description 48-Terminal Plastic Thin Quad Flatpack
Package Option ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9802 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN CONFIGURATION
ADCMODE ADVSS SHABYP CMLEVEL
36 ADCIN 35 TEST2 34 TEST1 33 ACVDD 32 CLAMP_BIAS 31 ACVSS 30 PGACONT2 29 PGACONT1 28 CCDBYP1 27 PIN 26 DIN 25 CCDBYP2 13 14 15 16 17 18 19 20 21 22 23 24
VRT
ADVDD
ADVSS
VRB
48 47 46 45 44 43 42 41 40 39 38 37
ADVSS 1 (LSB) D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 (MSB) D9 11 DRVDD 12 NC = NO CONNECT
PIN 1 IDENTIFIER
AD9802
TOP VIEW (Not to Scale)
ADCCLK
DSUBST
SHP SHD CLPDM
DRVSS
DVSS
DVDD
STBY PBLK
MODE1 MODE2
SUBST
NC
PIN FUNCTION DESCRIPTIONS
Pin # 1 2-11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34, 35 36 37 38 39 40 41 42 43 44, 45 46 47 48
Pin Name ADVSS D0-D9 DRVDD DRVSS DSUBST DVSS ADCCLK DVDD STBY PBLK CLPOB SHP SHD CLPDM DVSS CCDBYP2 DIN PIN CCDBYP1 PGACONT1 PGACONT2 ACVSS CLAMP_BIAS ACVDD TEST1, TEST2 ADCIN CMLEVEL SHABYP MODE2 MODE1 ADCMODE NC ADVDD ADVSS SUBST VRB VRT
Type P DO P P P P DI P DI DI DI DI DI DI P AO AI AI AO AI AI P AO P AI AI AO AO DI DI DI P P P AO AO
Description Analog Ground Digital Data Outputs: D0 = LSB, D9 = MSB +3 V Digital Driver Supply Digital Driver Ground Digital Substrate Digital Ground ADC Sample Clock Input +3 V Digital Supply Power-Down (Active High) Pixel Blanking (Active Low) Black Level Restore Clamp (Active Low) Reference Sample Clock Input Data Sample Clock Input Input Clamp (Active Low) Digital Ground CCD Bypass. Decouple to analog ground through 0.1 F. CDS Input. Tie to Pin 27 and AC-Couple to CCD output through 0.1 F. CDS Input. See above. CCD Bypass. Decouple to analog ground through 0.1 F. Coarse PGA Gain Control (0.3 V-2.7 V). Decoupled to analog ground through 0.1 F. Fine PGA Gain Control Analog Ground Clamp Bias Level. Decouple to analog ground through 0.1 F. +3 V Analog Supply Reserved Test Pins. Should be left NC or pulled high to ACVDD. Direct ADC Analog Input (See Driving the Direct ADC Input) Common-Mode Level. Decouple to analog ground through 0.1 F. Internal Bias Level. Decouple to analog ground through 0.1 F. ADC Test Mode Control (See Digital Output Data Control.) ADC Test Mode Control (See Digital Output Data Control.) ADC Input Control. Logic low for CDS/PGA, high for direct input. No Connect +3 V Analog Supply Analog Ground Substrate. Connect to analog ground. Bottom Reference Bypass. Decouple to analog ground through 0.1 F. Top Reference Bypass
NOTE Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
CLPOB
DVSS
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EQUIVALENT INPUT CIRCUITS
DVDD DRVDD
ACVDD
50 10pF
SUBST ACVSS
Figure 6. Pin 26 (DIN) and Pin 27 (PIN)
ACVDD DVSS DRVSS PGACONT1 10k
Figure 1. Pins 2-11 (DB0-DB9)
DVDD
SUBST PGACONT2 8k ACVDD
1k
8k
200
Figure 7. Pin 29 (PGACONT1) and Pin 30 (PGACONT2)
ACVDD
DSUBST
DVSS
Figure 2. Pin 21 (SHP) and Pin 22 (SHD)
DVDD
SUBST
10k 200 30k ACVSS
200
Figure 8. Pin 32 (CLAMP BIAS)
DSUBST DVSS
3k ADVDD 1.1k
Figure 3. Pin 16 (ADCCLK)
200
ADVDD
SUBST
ADVSS
9.3k ADVSS
Figure 9. Pin 48 (VRT) and Pin 47 (VRB)
ACVDD
Figure 4. Pin 37 (CMLEVEL)
ACVDD
50 1pF
50
SUBST
SUBST
ACVSS
Figure 10. Pin 36 (ADCIN) and Pin 38 (SHABYP)
Figure 5. Pin 25 (CCDBYP2) and Pin 28 (CCDBYP1)
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EFFECTIVE PIXEL INTERVAL BLACK LEVEL INTERVAL BLANKING INTERVAL DUMMY BLACK INTERVAL EFFECTIVE PIXEL INTERVAL
CCD
SHP
SHD
CLPOB
PBLK
CLPDM
ADCCLK
ADC DATA
NOTES: CLPDM AND CLPOB OVERWRITE PBLK CLAMP TIMING NEEDS TO BE ADJUSTED RELATIVE TO CCD'S BLACK PIXELS RECOMMENDED PULSE WIDTH CLPDM = 1.5 s MIN
Figure 11. Typical Horizontal Interval Timing
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1
CCD SIGNAL (DELAYED TO MATCH ACTUAL SAMPLING EDGE)
2
3
4
5
6
7
N N+1
N+2 N+3
N+4
SHD
SHP ACTUAL SAMPLING EDGE 35ns ADCCLK 35ns
tID
tOD
DIGITAL OUT
tH
DATA N-1 DATA N
OUTPUT LOAD CL = 20pF
OUTPUT DELAY tOD = 15ns HOLD TIME tH = 2ns INTERNAL CLOCK DELAY tID = 3ns LATENCY = 5 CYCLES
Figure 12. Timing Diagram
SHP
SHD
PRE-ADC OUTPUT LATCH
5ns 10ns
PRE-ADC OUTPUT LATCH DATA TRANSITION 5ns ADCCLK 20ns INHIBITED PERIOD FOR ADCCLK RISING EDGE RISING EDGE ANYWHERE IN THIS PERIOD OK
Figure 13. ADCCLK Timing Edge
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THEORY OF OPERATION Introduction
The AD9802 is a 10-bit analog-to-digital interface for CCD cameras. The block level diagram of the system is shown in Figure 14. The device includes a correlated double sampler (CDS), 0 dB-31 dB variable gain amplifier (PGA), black level correction loop, input clamp and voltage reference. The only external analog circuitry required at the system level is an emitter follower buffer between the CCD output and AD9802 inputs.
CLAMP BLACK LEVEL CDS PGA 10-BIT ADC OUT
Programmable Gain Amplifier (PGA) The on-chip PGA provides a (linear in dB) gain range of 0 dB- 31.5 dB. A typical gain characteristic plot is shown in Figure 16. Only the range from 0.3 V to 2.7 V is intended for actual use.
35 30 25 20
GAIN - dB
15 10 5 0 -5
IN
GAIN
REF
-10 -15 0 0.5 1 1.5 2 PGACONT1 - Volts 2.5 3
Figure 14.
Correlated Double Sampling (CDS)
CDS is important in high performance CCD systems as a method for removing several types of noise. Basically, two samples of the CCD output are taken: one with the signal present (data) and one without (reference). Subtracting these two samples removes any noise that is common to--or correlates with--both. Figure 15 shows the block diagram of the AD9802's CDS. The S/H blocks are directly driven by the input and the sampling function is performed passively, without the use of amplifiers. This implementation relies on the off-chip emitter follower buffer to drive the two 10 pF sampling capacitors. Only one capacitor at a time is seen at the input pin. The AD9802 actually uses two CDS circuits in a "ping-pong" fashion to allow the system more acquisition time. In this way, the output from one of the two CDS blocks will be valid for an entire clock cycle. Thus, the bandwidth requirement of the subsequent gain stage is reduced as compared to that for a single CDS channel system. This lower bandwidth translates to lower power and noise.
S/H FROM CCD S OUT
Figure 16.
As shown in Figure 17, PGA control is provided through the PGACONT1 and PGACONT2 inputs. PGACONT1 provides coarse, and PGACONT2 fine (1/16), gain control.
PGACONT1 PGACONT2
A PGACONT1 = COARSE CONTROL PGACONT2 = FINE (1/16) CONTROL
Figure 17.
Black Level Clamping
For correct processing, the CCD signal must be referenced to a well established "black level" by the AD9802. At the edge of the CCD, there is a collection of pixels covered with metal to prevent any light penetration. As the CCD is read out, these "black pixels" provide a calibration signal that is used to establish the black level. The feedback loop shown in Figure 18 is closed around the PGA during the calibration interval (CLPOB = LOW) to set the black level. As the black pixels are being processed, an integrator block measures the difference between the input level and the desired reference level. This difference, or error, signal is amplified and passed to the CDS block where it is added to the incoming pixel data. As a result of this process, the black pixels are digitized at one end of the ADC range, taking maximum advantage of the available linear range of the system.
IN CDS
Q1 S/H
Q2 10pF
Figure 15.
PGA
ADC CLPOB
INTEGRATOR
NEG REF
Figure 18.
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The actual implementation of this loop is slightly more complicated as shown in Figure 19. Because there are two separate CDS blocks, two black level feedback loops are required and two offset voltages are developed. Figure 19 also shows an additional PGA block in the feedback loop labeled "RPGA." The RPGA uses the same control inputs as the PGA, but has the inverse gain. The RPGA functions to attenuate by the same factor as the PGA amplifies, keeping the gain and bandwidth of the loop constant. There exists an unavoidable mismatch in the two offset voltages used to correct both CDS blocks. This mismatch causes a slight difference in the offset level for odd and even pixels, called "pixel-to-pixel offset" (see Specifications). The pixel-to-pixel offset is an output referred specification, because the black level correction is done using the output of the PGA.
CDS1 IN CDS2 CLPOB RPGA2 RPGA1 INT2 INT1 PGA ADC
To avoid problems associated with processing these transients, the AD9802 includes an input blanking function. When active (PBLK = LOW) this function stops the CDS operation and allows the user to disconnect the CDS inputs from the CCD buffer. If the input voltage exceeds the supply rail by more than 0.3 V, then protection diodes will be turned on, increasing current flow into the AD9802 (see Equivalent Input Circuits). Such voltage levels should be externally clamped to prevent device damage or reliability degradation.
10-Bit Analog-to-Digital Converter (ADC)
The ADC employs a multibit pipelined architecture that is well suited for high throughput rates while being both area and power efficient. The multistep pipeline presents a low input capacitance resulting in lower on-chip drive requirements. A fully differential implementation was used to overcome headroom constraints of the single +3 V power supply.
Direct ADC Input
NEG REF
CONTROL
The analog processing circuitry may be bypassed in the AD9802. When ADCMODE (Pin 41) is taken high, the ADCIN pin provides a direct input to the SHA. This feature allows digitization of signals that do not require CDS and gain adjustment. The PGA output is disconnected from the SHA when ADCMODE is taken high.
Differential Reference
Figure 19.
Input Bias Level Clamping
The buffered CCD output is connected to the AD9802 through an external coupling capacitor. The dc bias point for this coupling capacitor is established during the clamping (CLPDM = LOW) period using the "dummy clamp" loop shown in Figure 20. When closed around the CDS, this loop establishes the desired dc bias point on the coupling capacitor.
CLPDM
The AD9802 includes a 0.5 V reference based on a differential, continuous-time bandgap cell. Use of an external bypass capacitor reduces the reference drive requirements, thus lowering the power dissipation. The differential architecture was chosen for its ability to reject supply and substrate noise. Recommended decoupling shown in Figure 21.
0.1 F 1F 0.1 F
VRT REF VRB
INPUT CLAMP CCD CDS PGA TO ADC
Figure 21.
BLACK LEVEL CLP
Internal Timing
Figure 20.
Input Blanking
In some applications, the AD9802's input may be exposed to large signals from the CCD. These signals can be very large, relative to the AD9802's input range, and could thus saturate on-chip circuit blocks. Recovery time from such saturation conditions could be substantial.
The AD9802's on-chip timing circuitry generates all clocks necessary for operation of the CDS and ADC blocks. The user needs only to synchronize the SHP and SHD clocks with the CCD waveform, as all other timing is handled internally. The ADCCLK signal is used to strobe the output data, and can be adjusted to accommodate desired timing.
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APPLICATIONS INFORMATION Generating Clock Signals
1V p-p CIN RBIAS RBIAS ADCIN CML SHABYP 1.5V SHA
For best performance, the AD9802 should be driven by 3 V logic levels. As shown in the Equivalent Input Circuits, the use of 5 V logic for ADCCLK will turn on the protection diode to DVDD, increasing the current flow into this pin. As a result, noise and power dissipation will increase. The CDS clock inputs, SHP and SHD, have a additional protection and can withstand direct 5 V levels. External clamping diodes or resistor dividers can be used to translate 5 V levels to 3 V levels, but the lowest power dissipation is achieved with a logic transceiver chip. National Semiconductor's 74LVX4245 provides a 5 V to 3 V level shift for up to eight clock signals, has a three-state option, and features low power consumption. Philips Semiconductor and Quality also manufacture similar devices. Driving the Direct ADC Input The AD9802 can be used in a "direct ADC input" mode, in which the input signal bypasses the input clamp, CDS and PGA, and is sent directly to the sample and hold amplifier (SHA) of the ADC. There are several methods that may be used to drive the direct ADC input. To enable the direct input mode of operation, ADCMODE (Pin 41) is taken to logic high. This will internally disconnect the PGA output from the SHA input, and connect ADCIN (Pin 36) to the SHA input. The SHA has a differential input, consisting of ADCIN (Pin 36) as the positive input, and SHABYP (Pin 38) as the negative input. Both pins must be properly dc biased. Figures 22 through 25 show four circuits for driving the direct ADC input. Decoupling capacitors are not shown for CML, VRT, VRB and SHABYP pins.
1V p-p CML ADCIN CML SHABYP 1.5V SHA
AD9802
+3V ADCMODE
Figure 23. AC-Coupled Input
Figure 24 shows an alternative ac-coupled configuration. By connecting SHABYP to CML, the dc bias at Pin 36 (ADCIN) will internally track to the same voltage, automatically setting the input bias level. With a given input capacitor value, CIN, the time constant in this configuration will be dependent on the sampling frequency FS. Specifically: = (CIN /FS) x 2E +12
1V p-p CIN
ADCIN CML SHABYP 1.5V SHA
AD9802
+3V ADCMODE
Figure 24. "Auto Bias" AC-Coupled Input
Figure 25 shows a true differential drive circuit. Each input would be 500 mV p-p, to achieve the 1 V full-scale input to the ADC. The common-mode input range for this configuration extends from about 500 mV to 2.5 V. This circuit could also be implemented with ac coupling, similar to Figure 23.
500mV p-p ADCIN SHA CML 500mV p-p
AD9802
+3V ADCMODE
+3V
SHABYP
AD9802
ADCMODE
Figure 22. DC-Coupled Input
Figure 22 is a single-ended, dc-coupled circuit. SHABYP is connected to CML (1.5 V) to establish a midpoint bias. The input signal of 1 V p-p should be centered around CML. Figure 23 shows an ac-coupled configuration, where both inputs are biased to CML. The input capacitor CIN and bias resistors should be sized to set the appropriate high pass cutoff frequency for the application. To minimize the differential offset voltage due to the input bias currents, both resistors should be equal.
Figure 25. Differential Input
Figure 26 shows a video clamp circuit which may be used with the direct ADC mode of the AD9802 (supplies and decoupling not shown). The circuit will clamp the reference black level of an incoming video signal to 1.25 V dc. With SHABYP connected to 1.75 V (VRT), the ADCIN range spans from 1.25 V to 2.25 V. To accomplish this, the CLAMP pulse should be asserted during the horizontal sync interval, when the video is at its reference black level. A 5 V logic high applied to the gate of the SD210 will turn on the device, and the input capacitor CIN will charge up to provide 1.25 V at the ADCIN pin of the AD9802. Other appropriate NMOS devices may be substituted for the SD210. The AD8047 op amp requires 5 V supplies; appropriate single supply op amps may be substituted. The size of capacitor CIN should be set to meet the acquisition time and REV. 0
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droop specifications needed. A capacitor value of 0.01 F will result in a droop of less than 10 LSB across one video line, and requires only a CLAMP pulse of 1 s to charge up. A larger capacitor may be used to reduce droop, but then a longer CLAMP pulse may be necessary.
1V p-p CIN AMPLITUDE - dB
0
ADCIN SHA CML
CLAMP
500
SHABYP SD210 VRT
AD8047
VRB 500 +3V ADCMODE
AD9802
-100
0
FREQUENCY - MHz
9.0
Figure 29. Direct ADC Mode Typical FFT; FIN = 3.58 MHz, FS = 18 MHz
Figure 26. Video Clamp Circuit
1.0
Figures 27-29 show the typical linearity and distortion performance of the AD9802 in direct ADC mode.
Digitally Programmable Gain Control
0.5
0
The AD9802's PGA is controlled by an analog input voltage of 0.3 V to 2.7 V. In some applications, digital gain control is preferable. Figure 30 shows a circuit using Analog Devices' AD8402 Digital Potentiometer to generate the PGA control voltage. The AD8402 functions as two individual potentiometers, with a serial digital interface to program the position of each wiper over 256 positions. The device will operate with 3 V or 5 V supplies, and features a power-down mode and a reset function. To keep external components to a minimum, the ends of the "potentiometers" can be tied to ground and +3 V. One pot is used for the coarse gain adjust, PGACONT1, with steps of about 0.2 dB/LSB. The other pot is used for fine gain control, PGACONT2, and is capable of around 0.01 dB steps if all eight bits are used. The two outputs should be filtered with 1 F or larger capacitors to minimize noise into the PGACONT pins of the AD9802.
1 2 14 13 12
0.5
1.0
0
100
200
300
400
500
600
700
800
900
1023
Figure 27. Direct ADC-Mode Typical INL
1.0
+3V PGACONT1 +3V 0.1 F 1F
0.5 +3V PGACONT2 0 1F
5 6 10 9 8 3
AD8402-10
4 11
0.5 SHDN 1.0 CS
7
SDI CLK RS
0
100
200
300
400
500
600
700
800
900
1023
Figure 30. Digital Control of PGA
Figure 28. Direct ADC-Mode Typical DNL
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The disadvantage of this circuit is that the control voltage will be supply dependent. If additional precision is required, an external op amp can be used to amplify the VREFT (1.75 V) or VREFB (1.25 V) pins on the AD9802 to the desired voltage level. These reference voltages are stable over the operating supply range of the AD9802. Low power, low cost, rail-to-rail output amplifiers like the AD820, OP150 and OP196 are specified for 3 V operation. Alternatively, a precision voltage reference may be used. The REF193 from Analog Devices features low power, low dropout performance, maintaining a 3 V output with a minimum 3.1 V supply when lightly loaded.
Power and Grounding Recommendations AD9801/AD9802 EVALUATION BOARD DESCRIPTION Power Supply Connectors
J1
VDD: +3 V supply for the AD9801/AD9802. Data sheet specifications are given for +3.15 V. Operational range is from +3 V to +3.5 V. AVCC: +5 V supply for the AD8047 buffer, and for the PGACONT and PIN potentiometers. If the buffer amplifier is not needed, AVCC may be connected to the VDD supply. AVSS: -5 V supply for the AD8047 buffer. If the buffer amplifier is not needed, AVSS may be connected to J4. AGND: This is the analog ground plane for the AD9801/AD9802 and the buffer amplifier. The two ground planes are already connected together in one place on the evaluation board. DGND: This is the digital ground plane for the LVXC3245 transceivers. The two ground planes are already connected together in one place on the evaluation board. +3D: +3 V digital supply for the LVXC3245 transceivers. +3/5D: +3 V or +5 V digital supply for the LVXC3245 transceivers. This voltage determines the logic compatibility of the evaluation board. If 3 V clock levels and 3 V digital output levels are to be used, connect +3 V to J7. If +5 V clock levels and +5 digital output levels are to be used, connect +5 V to J7. DIN: Unbuffered input to the AD9801/AD9802. This input is 50 terminated by R4, which may be removed if no termination is required. See Input Configurations for more information. VIN: Input to the AD8047 buffer amplifier. This input is 50 terminated by R5, which may be removed if no termination is required. This op amp can be used as a buffer to drive the DIN pin on the AD9801/AD9802, or as a buffer for driving the direct ADC input on the AD9802. See Input Configurations and the AD9802 data sheet for more information. CLPDM SHD SHP CLPOB PBLK ADCCLK
J2
J3 J4
The AD9802 should be treated as an analog component when used in a system. The same power supply and ground plane should be used for all of the pins. In a two-ground system, this requires that the digital supply pins be decoupled to the analog ground plane and the digital ground pins be connected to analog ground for best noise performance. If any pins on the AD9802 are connected to the system digital ground, then noise can capacitively couple inside the AD9802 (through package and die parasitics) from the digital circuitry to the analog circuitry. Separate digital supplies can be used, particularly if slightly different driver supplies are needed, but the digital power pins should still be decoupled to the same point as the digital ground pins (analog ground plane). If the AD9802 digital outputs need to drive a bus or substantial load, a buffer should be used at the AD9802's outputs, with the buffer referenced to system digital ground. In some cases, when system digital noise is not substantial, it is acceptable to split the ground pins on the AD9802 to separate analog and digital ground planes. If this is done, be sure to connect the ground pins together at the AD9802. To further improve performance, isolating the driver supply DRVDD from DVDD with a ferrite bead can help reduce kickback effects during major code transitions. Alternatively, the use of damping resistors on the digital outputs will reduce the output rise times, reducing the kickback effect.
Evaluation Board
J5
J6 J7
Input Connectors
J8
J9
An evaluation board for the AD9802 is available. The board includes circuitry for manual PGA gain adjustment, input signal buffering, and logic level translation for 3 V or 5 V digital signals. Documentation for the AD9802-EB is included, consisting of a board description, schematic and layout information.
Clock Connectors
J10 J11 J12 J13 J14 J15
All of the clock inputs are 50 terminated and buffered by an LVXC3245 transceiver. The supply level at J7 determines the input clock level compatibility. The outputs of the LVXC3245 always send +3 V clock levels to the AD9801/AD9802.
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AD9802
Jumper Descriptions Test Point Descriptions
JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8
JP9
JP10
Connect to bypass the input coupling capacitor C18. Connect to short PIN and DIN (Pins 26 and 27 of the AD9801) together. Connects PIN to the dc level set by the wiper of R1. Connect to short the input coupling capacitor to ground, for test purposes. Connects the output of the buffer amplifier to the AD9801/AD9802 input. Connects the AD9801/AD9802's DRVDD pin to the VDD supply through ferrite bead FB6. Connects the AD9801/AD9802's DRVDD pin to the +3D supply. Connects the output of the AD8047 op amp to the direct ADC input of the AD9802. This jumper should never be connected on the AD9801-EB. Selects the regular camera mode of operation on the AD9802. This jumper should always be in place on the AD9801-EB. Selects the direct ADC input mode on the AD9802. This jumper should never be connected on the AD9801-EB.
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18
Input signal at J8. Input signal at PIN/DIN of AD9801/AD9802. PGACONT1 voltage. PGACONT2 voltage. STANDBY pin, pull high to enable power-down mode. CLPDM at AD9801/AD9802. SHD at AD9801/AD9802. SHP at AD9801/AD9802. CLPOB at AD9801/AD9802. PBLK at AD9801/AD9802. ADCCLK at AD9801/AD9802. VDD AVCC AVSS AGND DGND +3D +3/5D
Prototype Area
The top left hole in the prototyping area is connected to AGND. The bottom right hole is connected to AVCC.
Input Configurations
Standard CCD Input Grounded Input Test Buffered Input* Direct ADC Input (9802 only)
Input J8 none J9 J9
JP1 JP2 JP3 open short open open short open open short open [ ... don't care...
JP4 open short open
JP5 open open short ]
JP8 open open open short
JP9 short short short open
JP10 open open open short
*When using the buffer amplifier, 5 V must be connected to AVCC and AVSS, and R4 should be removed.
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AD9802
VDD JP10 VDD C55 0.01 F C4 0.1 F C2 0.1 F C3 0.1 F C1 1F JP9 C5 0.1 F
C56 0.1 F C8 0.1 F C9 0.1 F
C6 0.1 F
48 47 46 45 44 43 42 41 40 39 38 37
MODE1
VRT
1
D0 D1 D2 D3 D4 D5 D6 D7 D8 FB6 VDD JP7 +3D C17 0.01 F JP6 D9
2 3
ADVSS D0 (LSB)
ADCMODE
MODE2 SHABYP CMLEVEL
ADVSS ADVSS
VRB SUBST
ADVDD ADVDD
ADCIN 36 TEST2 35
C10 0.1 F
D1 4 D2 D3 6 D4
5 7 8 9 10 11
TEST1 34 ACVDD 33
D5 D6 D7 D8
U1 AD9802
CLAMP_BIAS 32 ACVSS 31 PGACONT2 30 PGACONT1 29 CCDBYP1 28 PIN 27 DIN 26 CCDBYP2 25 SHD CLPDM DVSS JP2
C11 0.1 F PGACONT2 PGACONT1 C12 0.1 F TP2 JP3 C19 0.1 F
DVSS ADCCLK DVDD
D9 (MSB) 12 DRVDD DRVSS DSUBST
C16 0.1 F VDD C15 0.01 F
13 14 15 16 17 18 19 20 21 22 23 24
CLPOB SHP
PBLK
STBY
C13 0.1 F
CW
TP5 TP6 C14 0.1 F TP7 TP8 TP9 TP10 TP11 CLPOB ADCCLK CLPDM PBLK SHP SHD
C18 0.1 F TP1
AVCC R1 1k
JP1 J8 DIN
JP8 R4 50 JP5 AMP_OUT JP4
Figure 31. Evaluation Board
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AD9802
+3V J1
TP12 FB1 VDD C34 0.1 F C35 22 F C36 0.1 F
AVCC TP3 R2 10k
CW
PGACONT1 C31 0.1 F C30 10 F 16V
+5V J2
TP13 FB2 AVCC C37 0.1 F C38 22 F C39 0.1 F AVCC
-5V J3
TP14 FB3 AVSS C40 0.1 F TP15 C41 22 F C42 0.1 F R3 10k
TP4
CW
PGACONT2 C33 0.1 F C32 10 F 16V
GND J4 DGND J5
AVCC TP16 VIN J9 +3D TP17 FB4 +3D C43 0.1 F TP18 FB5 +3/5D C46 0.1 F C47 22 F C48 0.1 F C44 22 F C45 0.1 F R13 500 AVSS R5 50 C21 0.01 F C20 1.0 F R6 20 AMP_OUT
U2 AD8047
J6
C23 0.01 F
C22 1.0 F
+3/5D J7
Figure 32. Evaluation Board
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AD9802
J10 +3D +3/5D +3D +3/5D R7 50 C26 0.01 F C53 0.1 F 74LVXC3245 1 VA 2 CC T/RB 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A6 24 VCCB 23 NC 22 OEB B0 B1 B2 B3 B4 B5 B6 B7 GND 21 20 19 18 17 16 15 14 13 C50 0.1 F C27 0.01 F C24 0.01 F C54 0.1 F 74LVXC3245 1 VA 2 CC T/RB 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A6 24 VCCB 23 NC 22 OEB B0 B1 B2 B3 B4 B5 B6 B7 GND 21 20 19 18 17 16 15 14 13 R11 50 C49 0.1 F C25 0.01 F R8 50 J12 SHP R9 50 J13 CLPOB R10 50 J14 PBLK J15 ADCCLK +3D +3/5D 40-PIN HEADER C28 0.01 F C52 0.1 F 74LVXC3245 1 VCCB VA 2 CC NC T/RB OEB 3 A0 4 B0 A1 5 U5 B1 A2 6 B2 A3 7 A4 B3 8 B4 A5 9 A6 B5 10 B6 A6 B7 11 GND 12 GND GND C51 0.1 F C29 0.01 F 1 3 5 7 10 9 11 13 15 J16 17 20 19 21 23 30 CLKOUT 33 40 CLKOUT 2 R12 50 CLPDM J11 SHD
D9 D8 D7 D6 D5 D4 D3 D2
U4
11 GND 12 GND
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
CLPDM SHD SHP CLPOB PBLK ADCCLK
U3
11 GND 12 GND
24 23 22 21 20 19 18 17 16 15 14 13
D1 D0
DB1 DB0
DB9 (MSB) DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB)
ADCCLK
Figure 33. Evaluation Board
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AD9802
Figure 34. Primary Side (Layer 1)
Figure 35. Ground Plane (Layer 2)
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AD9802
Figure 36. Power Plane (Layer 3)
Figure 37. Secondary Layer (Layer 4)
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AD9802
Figure 38. Primary Side Assembly
Figure 39. Secondary Side Assembly
REV. 0
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AD9802
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Terminal Plastic Thin Quad Flatpack (TQFP) (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
48 1
0.354 (9.00) BSC 0.276 (7.0) BSC
37 36
SEATING PLANE TOP VIEW
(PINS DOWN)
0.076 MAX 0 MIN 0 - 7 0.007 (0.18) 0.004 (0.09)
12 13
25 24
0.019 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
0.354 (9.00) BSC
0.276 (7.0) BSC
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PRINTED IN U.S.A.
C3102-3-10/97

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