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Wireless Components
ASK Single Conversion Receiver 390MHz TDA 5204 E1 Version 1.0 Specification December 2000
preliminary
Revision History Current Version: 1.0 as of 12.01.01 Previous Version: none Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
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Edition 12.00 Published by Infineon Technologies AG, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG December 2000. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
TDA 5204 E1
preliminary
Product Info
Product Info
General Description The IC is a very low power consump- Package tion single chip ASK Single Conversion Receiver for receive frequencies between 385 and 406MHz. The Receiver offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
Supply voltage range 5V 10% Temperature range -40C...+85C Power down mode with very low supply current (50nA typ) Fully integrated VCO and PLL Synthesiser RF input sensitivity < -110dBm
Remote Control Systems
Ordering Information
Type TDA 5204 available on tape and reel Ordering Code Q67037-A1169 Package P-TSSOP-28-1
Wireless Components
Product Info

Application
Keyless Entry Systems

Features
Low supply current (Is = 4.8mA typ.)
390MHz band Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
Fire Alarm Systems Low Bitrate Communication Systems
Specification, December 2000
1
2.1 2.2 2.3 2.4 2.5
Table of Contents
1-i
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 2-2 2-2 2-2 2-3 2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 3-2 3-3 3-8 3-8 3-8 3-9 3-9 3-9 3-10 3-10 3-10 3-10 3-11
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 4.5 LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 4-2 4-4 4-5 4-6 4-7
5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1 5-2 5-2 5-3 5-4 5-8 5-9 5-11
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 5.3 5.4 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 2.5 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5204 E1
preliminary
Product Description
2.1 Overview
The IC is a very low power consumption single chip ASK Superheterodyne Receiver (SHR) for the frequency band 390MHz. The SHR offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
2.2 Application
Keyless Entry Systems Remote Control Systems Fire Alarm Systems Low Bitrate Communication Systems
2.3 Features
Wireless Components

Low supply current (Is = 4.8mA typ.) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ.) Fully integrated VCO and PLL Synthesiser RF input sensitivity < -110dBm frequency band 390MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold Temperature range -40C...+85C
2-2
Specification, December 2000
TDA 5204 E1
preliminary
Product Description
2.4 Possible Receive Ranges
385...406MHz (high-side injected) 406...428MHz (low-side injected) 781...823MHz (high-side injected) 803...844MHz (low-side injected)
2.5 Package Outlines
Wireless Components

P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
2-3
Specification, December 2000
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
TDA 5204 E1
preliminary
Functional Description
3.1 Pin Configuration
CRST1 VCC LNI TAGC AGND LNO VCC MI MIX AGND FSEL IFO DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26
CRST2 PWDN PDO DATA 3VOUT THRES FFB OPP SLN SLP LIMX LIM CSEL LF
TDA5204
25 24 23 22 21 20 19 18 17 16 15
Pin_Configuration.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3-2
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. 1 Symbol CRST1 Equivalent I/O-Schematic Function External Crystal Connector 1
4.15V 1
2 3
VCC LNI
5V Supply LNA Input
3
1k
4
TAGC
4.3V 4uA 1k 4 1.5uA 1.7V
AGC Time Constant Control
5 6
AGND LNO
Analogue Ground Return LNA Output
1k 6
7
VCC
5V Supply
Wireless Components
3-3
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
8
MI
1.7V
Mixer Input
2k
2k 9
9
MIX
8
Complementary Mixer Input
10 11
AGND FSEL
Analogue Ground Return 390MHz: not applicable - has to be left open
1.2V 40k 11
12
IFO
300uA 2.2V 60 12 4.5k
10.7 MHz IF Mixer Output
13 14 15
DGND VDD LF
4.8V 30uA 100
Digital Ground Return 5V Supply (PLL Counter Circuitry) PLL Filter Access Point (Loop Filter)
200 15
30uA 2.4V
Wireless Components
3-4
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
16
CSEL
6.xx or 12.xx MHz Quartz Selector
1.2V 80k 16
17
LIM
2.4V 15k
Limiter Input
17 330 18
18 19
LIMX SLP
15k
Complementary Limiter Input Data Filter Output Data Slicer Positive Input Peak Detector Input
10k
100 19 10k 40u
20
SLN
Data Slicer Negative Input
10k 20
21
OPP
OpAmp Noninverting Input
200 21
Wireless Components
3-5
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
22
FFB
Data Filter Feedback Pin
100k 22
23
THRES
AGC Threshold Input
10k 23
24
3VOUT
3V Reference Output
24 3V
25
DATA
Data Output
200 25
80k
Wireless Components
3-6
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
26
PDO
Peak Detector Output
200 26
27
PDWN
Power Down Input Vs --> Power ON GND---> Power Down
27 220k 220k
28
CRST2
External Crystal Connector 2
4.15V 28
Wireless Components
3-7
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.3 Functional Block Diagram
VCC
IF Filter
LNO 6 RF 3
MI 8
MIX IFO 9 12
LIM 17
LIMX 18
FFB 22
OPP 21
SLP 19
SLN 20 25 DATA
LNA
RSSI
SLICER
TAGC 4
26 23
PDO THRES 3VOUT
TDA 5204
VDD 14 : 1/2 DGND 13 Loop Filter VCO : 128/64 DET Crystal OSC
AGC Reference
24
UREF
Bandgap Reference
2/7 VCC
5/10 AGND
11 FSEL
15 LF
16 CSEL
1
28
27 PDWN
Crystal
Function_5204.wmf
Figure 3-2
Main Block Diagram
3.4 Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current consumption is 500A. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operat-
Wireless Components
3-8
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
ing case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 4.1.
3.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) 390MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB. A low pass filter with a corner frequency of 20MHz is built on chip in order to suppress RF signals to appear at the IF output ( IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330= to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor diodes. It's nominal centre frequency is 800MHz. The FSEL pin (Pin 11) has to be left open. No additional components are necessary. The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. The VCO signal is divided by two before it is fed to the mixer. The loop filter is also realised fully on-chip.
3.4.4
Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 6 and 12MHz range as the overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States CSEL Open Shorted to ground Crystal Frequency 6.xx MHz 12.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
Wireless Components
3-9
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80dB that has a bandpass-characteristic centred around 10.7MHz. It has an input impedance of 330 =to allow for easy interfacing to a 10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4.1. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to turn down the LNA gain by approximately 18dB in case the input signal strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100k= on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4.2.
3.4.7
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of approximately 120kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for the detector. The self-adjusting threshold on pin SLN (pin 20) its generated by RC-term or peak detector depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in Section 4.5.
3.4.8
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An external RC network is necessary. The output can be used as an indicator for the signal strength and also as a reference for the data slicer. The maximum output current is approx. 900A.
Wireless Components
3 - 10
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.4.9
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA.
Table 3-3 PDWN Pin Operating States PDWN Open or tied to ground Tied to Vs Operating State Powerdown Mode Receiver On
Wireless Components
3 - 11
Specification, December 2000
4
Applications
Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . 4-2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
TDA 5204 E1
preliminary
Applications
4.1 LNA and Automatic Gain Control (AGC)
The AGC extends the dynamic range of the receiver. The automatic gain control in the TDA5204 is a narrow-band control loop which compares the receive signal strength signal (RSSI, 0.8V to 2.8V) from the limiter with a fixed threshold voltage applied to pin 23 (THRES). In the following figure the internal circuitry of the LNA automatic gain control is shown.
R4
R5
Uthreshold Pins: 24 23 RSSI (0.8 - 2.8V)
+3V
OTA
VCC
Iload RSSI > Uthreshold: Iload=4.2A RSSI < Uthreshold: Iload= -1.5A 4 UC C Gain control voltage
LNA
Uc:< 2.6V : Gain high Uc:> 2.6V : Gain low Ucmax= VCC - 0.7V Ucmin = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The fixed voltage on pin 23 is generated on the external voltage divider. The comparator is a transimpedance amplifier (OTA), which creates a positive current (+4.2uA) in the case the RSSI level is larger than the threshold voltage. Otherwise the current is -1.5uA. This leads to an asymmetric fast-attack and slow-release behaviour and thus to fast reaction to the low gain mode and slow reaction to the high gain mode. This current is converted into a control voltage over an external capacitor C attached to pin 4 (TAGC) which defines the gain of the LNA. The limits of the control voltages for the LNA on pin4 are 1.67V for high gain mode and Vcc-0.7V for low gain mode.
Wireless Components
4-2
Specification, January 2001
TDA 5204 E1
preliminary
Applications
LNA always in high gain mode
3
2.5
UTHRES Voltage Range
2
RSSI Level Range
RSSI Level
1.5
1
LNA always in low gain mode
0.5
0 -120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level an Permissive AGC Threhold Level
The value of the capacitor defines the response time of the AGC. For a stable control loop the capacitor value should be at least 47nF. The AGC can be disabled by tying the THRES-pin either to GND or to VCC as show here: LNA high gain: LNA low gain: - pin 23 (THRES) shorted to VCC - pin 23 (THRES) shorted to GND
In these cases capacitor and voltage divider are not necessary.
Wireless Components
4-3
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100k on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1.
C1
C2
Pins: R 100k
22 R 100k
21
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
(1)
(2)
2 Q bC1 = -----------------------R 2f 3dB
with
b C2 = --------------------------------4Q R f 3dB
b Q = -----a
where in case of a Bessel filter and thus
(3)
the quality factor of the poles
a = 1.3617, b = 0.618 Q = 0.577
and in case of a Butterworth filter and thus
a = 1.41, b = 1 Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100k: C1 = 450pF, C2 = 225pF 1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4-4
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the quartz specifications given by the quartz manufacturer.
CS Pin 28 Crystal Input impedance Z1-28
TDA5204 Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
The quartz oscillator input impedance consists of a negative resistance and an inductance L. Crystal specified with load capacitance
CS =
1 1 + (2 f CL
)2 L
with CL the load capacitance (refer to the quartz crystal specification). Examples with typ. values: 6.26 MHz: 12.52 MHz: CL = 12 pF CL = 12 pF L=21uH L=19uH CS = 8.6 pF CS = 5 pF
These values may be obtained by putting two capacitors in series to the quartz.
Wireless Components
4-5
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.4 Quartz Frequency Calculation
The quartz frequency is calculated by using the following formula:
QU = (RF 10.7MHz) / r with RF +/LO QU r .... ... .... .... ....
(1),
receive frequency high-side / low-side injected local oscillator (PLL) frequency (RF 10.7) quartz oscillator frequency ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table.
Table 4-1 frequency range fRF 385...406MHz 406...428MHz 781...823MHz 803...844MHz X X high-side injected X X low-side injected FSEL Pin11 open open GND GND
Table 4-2 quartz crystal range 6.xx MHz 12.xx MHz CSEL Pin16 open GND
Table 4-3 FSEL open open GND GND CSEL open GND open GND Ratio r (fLO/fQU) 64 32 128 64
Example:
fRF=390MHz fQU=(390MHz+10.7MHz) / 64 = 6.2609375MHz fQU=(390MHz+10.7MHz) / 32 = 12.521875MHz
Wireless Components
4-6
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. In case of a signal coding scheme without DC content such as Manchester coding the threshold can be generated using an external R-C integrator as shown in the following . The cut-off frequency of the R-C integrator has to be lower than the lowest frequency appearing in the data signal. In order to keep distortion low, the minimum value for R is 20k.
R C
Pins:
19
20 Uthreshold
data out 25
data filter data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in connection with two resistors and one capacitor as shown in the following figure. The component values are depending on the coding scheme and the protocol used.
R C R data out 25 Uthreshold
Pins: peak detector
26
19
20
data slicer
data filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4-7
Specification, January 2001
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
TDA 5204 E1
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C # Parameter Symbol Limit Values min 1 2 3 4 5 Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins Vs Tj Ts RthJA VESD -1 -0.3 -40 -60 max 5.5 +125 +150 114 +1 V C C K/W kV HBM according to MIL STD 883D, method 3015.7 Unit Remarks
Wireless Components
5-2
Specification, January 2001
TDA 5204 E1
preliminary
Reference
5.1.2
Operating Range
Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 85C # Parameter Symbol Limit Values min 1 2 3 Supply Current Power Down Current Receiver Input Level IS IPWDN RFin -110 max 6.4 250 -13 mA nA dBm fRF = 390MHz Unit Test Conditions L Item
4
Receive Frequency
fRF
385
406
MHz
This value is guaranteed by design.
Wireless Components
5-3
Specification, January 2001
@ source impedance 50, BER 2E-3, average power level, Manchester encoded datarate 4kBit, 280kHz IF Bandwidth, with AGC
TDA 5204 E1
preliminary
Reference
5.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temp. range. Typical characteristics are the median were of the production. The device performance parameters marked with measured on an Infineon evaluation board as desdribed in Section 5.2. Currents flowing into the device are denoted as positive currents and vice versa.
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V # Parameter Symbol min Supply Supply Current 1 2 LNA Signal Input LNI (PIN 3), high gain mode 1 Supply current, standby mode Supply current IS PDWN IS 50 4.8 150 5.5 nA mA Pin 27 (PDWN) open or tied to 0 V Limit Values typ max Unit Test Conditions L Item
Signal Output LNO (PIN 6), high gain mode
Signal Input LNI, low gain mode
Wireless Components
5-4
Specification, January 2001
2
Input level @ 1dB C. P. fRF = 390 MHz
P1dBLNA
-7
dBm
matched input
1
Input impedance, fRF = 390 MHz
S11 LNA
0.903 / -31.8deg
4
Noise Figure
NFLNA
2
dB
excluding matching network loss - see Appendix
3
Voltage Gain Antenna to MI fRF = 390 MHz
GAntMI
21
dB
2
Output impedance, fRF = 390 MHz
S22 LNA
0.8822 / -12.13deg
1
Gain fRF = 390 MHz
S21 LNA
1.578 / 141.8deg
5
LO signal feedthrough at antenna port
LOLNI
-119
dBm
4
Input 3rd order intercept point fRF = 390 MHz
IIP3LNA
-10
dBm
fin = 390MHz
3
Input level @ 1dB C.P. fRF=390 MHz
P1dBLNA
-14
dBm
2
Input impedance, fRF = 390 MHz
S11 LNA
0.879 / -31 deg
Average Power Level at BER = 2E-3 (Sensitivity)
RFin
-112
dBm
Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
TDA 5204 E1
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min Signal Input LNI, VTHRES = GND, low gain mode Limit Values typ max Unit Test Conditions L Item
Signal Output LNO, VTHRES = GND, low gain mode
Signal 3VOUT (PIN 24) 1 2 Output voltage Load current out V3VOUT I3VOUT 2.9 3 3.1 -50 V A
Signal THRES (PIN 23) 1 2 3 4 Input Voltage range LNA low gain mode LNA high gain mode Current in VTHRES VTHRES VTHRES ITHRES_in 0 0 3.3 -5 VS 0.5 VS V V V see chapter 4.1
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out ITAGC_in -2.5 0.5 -4.2 1.5 -5.5 4 A A RSSI > VTHRES RSSI < VTHRES
MIXER Signal Input MI/MIX (PINS 8/9)
Signal Output IFO (PIN 12)
Wireless Components
5-5
Specification, January 2001
4
RF to IF isolation
ARF-IF
46
dB
3
Noise Figure, SSB (~DSB NF+3dB)
NFMIX
13
dB
2
Conversion Voltage Gain fRF=390 MHz
GMIX
+21
dB
1
Output impedance
ZIFO
330
2
Input 3rd order intercept point
IIP3MIX
-25
dBm
1
Input impedance, fRF = 390 MHz
S11 MIX
0.9413 / -13.1deg
nA
3
Voltage Gain Antenna to MI fRF = 390 MHz
GAntMI
2
dB
2
Output impedance, fRF = 390 MHz
S22 LNA
0.897 / -12.4deg
1
Gain fRF = 390 MHz
S21 LNA
0.1834 / 144deg
3
Input 3rd order intercept point fRF = 390 MHz
IIP3LNA
-13
dBm
fin = 390MHz
TDA 5204 E1
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min LIMITER Signal Input LIM/X (PINS 17/18) dB dB 23 1.2 3.2 MHz V V Limiter_in: 10uV Limiter_in: 100mV Limit Values typ max Unit Test Conditions L Item
5 6
RSSI Level at Data Filter Output SLP RSSI Level at Data Filter Output SLP
RSSIlow RSSIhigh
0.4 2.3
0.8 2.8
DATA FILTER
FILT
SLICER Signal Output DATA (PIN 25)
SLIC
2 3 4 5
LOW output voltage HIGH output voltage Output current Output impedance
VSLIC_L VSLIC_H ISLIC_out Rout
0 Vs-1.2 -400 60 VS-1 -800 80
100 Vs-0.7 -1100 100
mV V A k high level drive low level drive
PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 Load current Leakage current Iload Ileakage -500 0 -950 700 -1200 2000 A nA
Wireless Components
5-6
Specification, January 2001
1
Max. useable bandwith
BWBB
100
kHz
1
Max. useable bandwidth
BWBB
100
kHz
4
Operating frequency (3dB points)
fLIM
5
10.7
3
RSSI linearity
LINRSSI
1
2
RSSI dynamic range
DRRSSI
60
70
80
1
Input Impedance
ZLIM
264
330
396
TDA 5204 E1
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min CRYSTAL OSCILLATOR Signals CRSTL1, CRISTL 2, (PINS 1/28) 1 2 3 4 5 Operating frequency Negative Resistance @ ~6MHz Negatve Resitance @ ~12MHz Input Indutance @ ~6MHz Input Inductance @ ~12MHz fCRSTL Re{Z1-28} Re{Z1-28} Im{Z1-28}/ 2 f Im{Z1-28}/ 2 f 1 -750 -450 21 19 14 MHz uH uH fundamental mode, series resonance Limit Values typ max Unit Test Conditions L Item
PLL Signal LF (PIN 15) 1 Tuning voltage relative to Vs VTUNE 0.5 1.05 2 V
POWER DOWN Pin Signal PDWN (PIN 27) 1 2 3 4 Powerdown Mode On Powerdown Mode Off Input bias current Start-up Time until valid IF signal is detected PWDNON PWDNOff IPWD TSU 0 2.8 19 1 0.8 VS V V
ms
PLL DIVIDER Signal CSEL (PIN 16) 1 2 3 fCRSTL range 6.xxMHz fCRSTL range 12.xxMHz Bias current CSEL Measured only in lab. VCSEL VCSEL ICSEL 1.4 0 -5 4 0.2 V V or open
Wireless Components
5-7
Specification, January 2001
A
CSEL tied to GND
uA
Power On Mode

TDA 5204 E1
preliminary
Reference
5.2 Test Circuit
The device performance parameters marked with in Section 5.1.3 were measured on an Infineon evaluation board. This evaluation board can be obtained together with evaluation boards of the accompanying transmitter device TDA51xx in an evaluation kit that may be ordered on the INFINEON RKE Webpage www.infineon.com/rke
Infineon Technologies Design Center Graz
TITLE: TDA5200 /-01 /-02 Evaluatio
n Board
Test_circuit.wmf
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5-8
Specification, January 2001
DATE: Jul.19, 1999
FILE: -10 V 2.0
TDA 5204 E1
preliminary
Reference
5.3 Test Board Layouts
Figure 5-2
Top Side of the Evaluation Board (TDA5210 Testboard is the same)
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5-9
Specification, January 2001
TDA 5204 E1
preliminary
Reference
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 10
Specification, January 2001
TDA 5204 E1
preliminary
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5204 at 390MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials Ref R1 R2 R3 R4 R5 R6 L1 L2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Q2 F1 X2, X3 X1, X4, S1, S5 S4 IC1 TDA 5204 Value 100k 100k 820k 120k 180k 10k 15nH 10pF
a
Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% Toko, PTL2012-F15N0G 0805,COG, 2% 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 5% 1206, X7R, 10% Toko, PTL2012-F15N0G 0805, COG, 5% 0805, COG, 5% 0805, COG, 5% 0805, X7R, 10% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 0.1pF 0805, COG, 2% HC49/U, fundamental mode, CL = 12pF, 12.521875 MHz: Jauch Q12.521875-S11-1252-12-10/20 Murata Johnson 2-pole pin connector 3-pole pin connector, or not equipped Infineon
1.8pF 6.8pF 6.8pF 100pF 47nF 12nH
b
100pF 33pF 100pF 10nF 10nF 220pF 47nF 470pF 47nF 12pF 12pF (390MHz + 10.7MHz)/32 SFE10.7MA5-A 142-0701-801
a. / b. The coil is at the place of the capacity and vice versa.
Wireless Components
5 - 11
Specification, January 2001
TDA 5204 E1
preliminary
Reference
The following components are necessary in addition to the above mentioned ones for evaluation of the TDA5204 in conjunction with a Microchip HCS515 decoder.
Table 5-5 Bill of Materials Addendum Ref R21 R22 R23 R24 R25 C21 C22 IC2 T1 D1 Value 22k 100k 22k 820k 560k 100nF 100nF HCS515 BC 847B LS T670-JL Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 1206, X7R, 10% 1206, X7R, 10% Microchip Infineon Infineon
Wireless Components
5 - 12
Specification, January 2001
TDA 5204 E1
preliminary
List of Figures
List of Figures
Figure 2-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI Level an Permissive AGC Threhold Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Side of the Evaluation Board (TDA5210 Testboard is the same) . . . . . . . . . . . . . . Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3-2 3-8 4-2 4-3 4-4 4-5 4-7 4-7 5-8 5-9 5-9 5-10
Wireless Components
List of Figures - 1
Specification, December 2000
TDA 5204 E1
preliminary
List of Tables
List of Tables
Table 3-1 Table 3-3 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C . . . . . . . . . Operating Range, Ambient temperature TAMB= -40C ... + 85C . . . . . . . . . . . . . . . . . AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-11 5-2 5-3 5-4 5-11 5-12
Wireless Components
List of Tables - 1
Specification, December 2000

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