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| DATA SHEET MICRONAS MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec June 30, 2004 6251-505-1DS MICRONAS MAS 35x9F Contents Page 5 6 6 7 8 8 8 8 9 9 9 9 10 10 10 10 10 10 10 11 11 11 11 11 12 12 12 13 15 15 15 15 15 15 15 15 16 17 17 18 18 18 18 18 18 19 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.2.1. 2.3.2.2. 2.4. 2.4.1. 2.4.2. 2.4.2.1. 2.4.2.2. 2.4.2.3. 2.4.2.4. 2.4.3. 2.4.4. 2.5. 2.5.1. 2.5.2. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.8.5. 2.8.6. 2.9. 2.10. 2.10.1. 2.10.2. 2.10.2.1. 2.10.2.2. 2.11. 2.11.1. 2.11.2. 2.11.2.1. Title Introduction Features Features of the MAS 35x9F Family Application Overview Functional Description Overview Architecture of the MAS 35x9F DSP Core RAM and Registers Firmware and Software Internal Program ROM and Firmware, MPEG-Decoding Program Download Feature Audio Codec A/D Converter and Microphone Amplifier Baseband Processing Bass, Treble, and Loudness Micronas Bass (MB) Automatic Volume Control (AVC) Balance and Volume D/A Converters Output Amplifiers Clock Management DSP Clock Clock Output At CLKO Power Supply Concept Power Supply Regions DC/DC Converters Power Supply Configurations Battery Voltage Supervision Interfaces I2C Control Interface S/PDIF Input Interface S/PDIF Output Multiline Serial Audio Input (SDI, SDIB) Multiline Serial Output (SDO) Parallel Input/Output Interface (PIO) MPEG Synchronization Output MP3 Block Input Mode Functional Description of the MP3 Block Input Mode Setup Resync Timeout Detailed Setup Default Operation Stand-by Functions Power-Up of the DC/DC Converters and Reset Important Advice for Turn-on and Operating Voltage DATA SHEET 2 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Contents, continued Page 20 21 21 21 22 22 22 22 22 22 23 23 27 27 28 28 28 28 29 29 29 29 29 30 30 30 31 31 31 32 32 43 43 44 44 45 45 45 46 52 Section 2.11.3. 2.11.4. 2.11.5. 2.11.6. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.2. 3.2.1. 3.2.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.3.2.8. 3.3.2.9. 3.3.2.10. 3.3.2.11. 3.3.2.12. 3.3.3. 3.3.4. 3.3.4.1. 3.3.4.2. 3.3.5. 3.3.6. 3.3.7. 3.3.8. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. Title Reset Signal Specification Control of the Signal Processing Start-up of the Audio Codec Power-Down Controlling I2C Interface Device Address I2C Registers and Subaddresses Naming Convention Direct Configuration Registers Write Direct Configuration Registers Read Direct Configuration Register DSP Core Access Protocol Data Formats Run and Freeze (Codes 0hex to 3hex) Read Register (Code Ahex) Write Register (Code Bhex) Read Memory (Codes Chex and Dhex) Short Read Memory (Codes C4hex and D4hex) Write Memory (Codes Ehex and Fhex) Short Write Memory (Codes E4hex and F4hex) Clear SYNC Signal (Code 5hex) Default Read Fast Program Download (Code 6hex) Serial Program Download Read IC Version (Code 7hex) List of DSP Registers List of DSP Memory Cells Application Selection and Application Running Application Specific Control Ancillary Data Reading of the Memory Cells "Number of Bits in Ancillary Data" and "Ancillary Data" DSP Volume Control Explanation of the G.729A Data Format Audio Codec Access Protocol Write Codec Register Read Codec Register Codec Registers Basic MB Configuration Micronas June 30, 2004; 6251-505-1DS 3 MAS 35x9F Contents, continued Page 54 54 57 60 60 60 60 60 60 60 61 61 61 61 61 61 61 61 62 62 63 64 65 65 67 71 72 73 74 76 77 77 79 80 81 84 86 89 89 90 92 Section 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.3.6.1. 4.3.7. 4.3.8. 4.3.9. 4.3.10. 4.3.11. 4.3.12. 4.3.13. 4.3.14. 4.4. 4.5. 4.5.1. 4.6. 4.6.1. 4.6.1.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.2.5. 4.6.2.6. 4.6.2.7. 4.6.2.8. 4.6.3. 4.6.4. 4.6.5. 5. 5.1. 5.2. 6. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Reference Pins DC/DC Converters and Battery Voltage Supervision Oscillator Pins and Clocking Control Lines Parallel Interface Lines PIO Handshake Lines Serial Input Interface (SDI) Serial Input Interface B (SDIB) Serial Output Interface (SDO) S/PDIF Input Interface S/PDIF Output Interface Analog Input Interfaces Analog Output Interfaces Miscellaneous Pin Configuration Internal Pin Circuits Reset Pin Configuration for MAS 3529F and MAS 3539F Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Digital Characteristics I2C Characteristics Serial (I2S) Input Interface Characteristics (SDI, SDIB) Serial Output Interface Characteristics (SDO) S/PDIF Input Characteristics S/PDIF Output Characteristics PIO as Parallel Input Interface: DMA Mode PIO as Parallel Input Interface: Program Download Mode PIO as Parallel Output Interface Analog Characteristics DC/DC Converter Characteristics Typical Performance Characteristics Application Typical Application in a Portable Player Recommended DC/DC Converter Application Circuit Data Sheet History DATA SHEET 4 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. Layer 2 (widely used, e.g., in DVD) achieves a compression of 8:1 without significant losses in audio quality. The MAS 35x9F supports the "Advanced Audio Coding" (AAC) that is defined as a part of MPEG 2. AAC provides compression rates up to 16:1. It defines several profiles for different applications. This IC decodes the "low complexity profile" that is especially optimized for portable applications. The MAS 35x9F also implements a voice encoder and decoder that is compliant to the ITU Standard G.729 Annex A. SC4 is a proprietary Micronas speech codec technology that can be downloaded to the MAS 35x9F, to allow recording and playing back speech at various sampling rates. MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec Release Note: Revision bars indicate significant changes to the previous edition. This data sheet applies to the MAS 35x9F version B4. 1. Introduction The MAS 35x9F is a single-chip, low-power MPEG layer 2/3 and MPEG2-AAC audio stereo decoder. It also contains the G.729 Annex A speech compression and decompression technology for use in memorybased or broadcast applications. Additional functionality is achievable via download software (e.g., CELP voice decoder, Micronas SC4 (ADPCM) encoder/ decoder). The MAS 35x9F decoding block accepts compressed digital data streams as serial bit streams or in parallel format, and provides serial PCM and S/PDIF output of decompressed audio. In addition to the signal processing function, the IC incorporates a high-performance stereo D/A converter, headphone amplifiers, a stereo A/D converter, a microphone amplifier, and two DC/DC converters. Thus, the MAS 35x9F provides a true "all-in-one" solution that is ideally suited for highly optimized memory-based portable music players with integrated speech recording and playback function. Micronas June 30, 2004; 6251-505-1DS 5 MAS 35x9F 1.1. Features Firmware - MPEG 1/2 layer 2 and layer 3 decoder - Extension to MPEG 2 layer 3 for low sampling rates ("MPEG 2.5") - Extraction of MPEG Ancillary Data - MPEG 2 AAC decoder (low-complexity profile) - Micronas G.729 Annex A speech compression and decompression - Master or slave clock operation - Adaptive bit rates (bit rate switching) - Intelligent power management (processor clock is dependent on sampling frequencies) - SDMI-compliant security technology - Stereo channel mixer - Bass, treble, and loudness function - Micronas Bass (MB) - Automatic Volume Control (AVC) Interfaces - Two serial asynchronous interfaces for bit streams and uncompressed digital audio - Parallel handshake bit stream input - Serial audio output via I2S and related formats - S/PDIF data input and output - Controlling via I2C interface Hardware Features DATA SHEET - Two independent embedded DC/DC converters, (e.g., for DSP and flash RAM supply) - Low DC/DC converter start-up voltage (0.9 V) - DC converter efficiency up to 95% - Battery voltage monitor - Low supply voltage down to 2.2 V - Low power dissipation, e.g., 87 mW (128kBit/s, 44.1 kHz, Headphone playback) - High-performance RISC DSP core - On-chip crystal oscillator - Hardware power management and power-off functions - Microphone amplifier - Stereo A/D converter for FM/AM-radio and speech input - CD quality stereo D/A converter - Headphone amplifier - Noise and power-optimized volume - External clock or crystal frequency of 13...28 MHz - Standby current < 10 A 1.2. Features of the MAS 35x9F Family Feature Layer 3 Decoder G.729 Encoder/Decoder AAC Decoder 3509 X X X 3519 X X X 3529 X 3539 X X X 3549 3559 6 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 1.3. Application Overview The following block diagram shows an example application for the MAS 35x9F in a portable audio player device. Besides a simple controller and the external flash memories, all required components are integrated in the MAS 35x9F. The MAS 35x9F supports both speech and radio quality audio encoding, as well as compressed-audio decoding tasks. Fig. 1-1 depicts a portable power-optimized audio application. The two embedded DC/DC converters of the MAS 35x9F generate optimum power supply voltages for the DSP core and also for state-of-the art flash memories that typically require 2.7 to 3.3 V supply. The performance of the DC/DC converters reaches efficiencies of up to 95%. Portable Digital Music Player MAS 35x9F optional line in A/D Audio baseband features DSP Core D/A Microphone amplifier MP3 AAC G.729 Optional SC4 Downloads Headphone amplifier Volume Headphone optional digital in S/PDIF or serial digital out S/PDIF and serial Crystal Osc./PLL I2C Battery Voltage Monitor DC/DC1 DC/DC2 Parallel I/O Bus System clock I2C Control e.g. 1.0 V e.g. 2.2 V e.g. 3.0 V I 2C Display Keyboard C PC Connector Fig. 1-1: Example of an application for the MAS 35x9F in a portable audio player device Micronas Flash RAM June 30, 2004; 6251-505-1DS 7 MAS 35x9F 2. Functional Description 2.1. Overview The MAS 35x9F is intended for use in portable consumer audio applications. It receives parallel or serial data streams and decodes MPEG Layer 2 and 3 (including the low sampling frequency extensions) and MPEG 2 AAC. A low bit-rate speech codec, compliant to the ITU Standard G.729 Annex A, is integrated. Additional downloadable software modules (SDMI, other audio/speech encoders/decoders) are available on request. 2.2. Architecture of the MAS 35x9F DATA SHEET The hardware of the MAS 35x9F consists of a highperformance RISC Digital Signal Processor (DSP), and appropriate interfaces. A hardware overview of the IC is shown in Fig. 2-1. 2.3. DSP Core The internal processor is a dedicated DSP for advanced audio applications. Mic. Input (incl. Bias) 1 Line Input 2 Audio Codec 2 A/D MIX Audio Proc. D/A 2 Audio Output DSP Core S/PDIF Input 1 S/PDIF Input 2 Serial Audio (I S, SDI) 2 ALU MAC Serial Audio (I2S, SDO) Accumulators ROM Output Select Input Select S/PDIF Output Control DCCF DCFR DSP Codec Serial Audio (stream, SDIB) VBAT Volt. Mon. D0 D1 IC Interface 2 I 2C control V1 DC/DC 2 DC/DC 1 Registers Div. Div. V2 Parallel I/O Bus (PIO) Xtal 18.432 MHz Osc. PLL Synth. Synthesizer Clock Scaler /2 CLKO Fig. 2-1: The MAS 35x9F architecture 8 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F selected, the Layer 2, Layer 3 or AAC bit stream is recognized and decoded automatically. To add/remove MPEG layers while running in MPEG decoding mode (e.g. Layer 2, Layer 3 (0x0c) to Layer 2, Layer 3, AAC (0x1c)), the application selection has to be reset before writing the new value. For general control purposes, the operation system provides a set of I2C instructions that give access to internal DSP registers and memory areas. An auxiliary digital volume control and mixer matrix is applied to the digital stereo audio data. This matrix is capable of performing the balance control and a simple kind of stereo basewidth enhancement. All four factors LL, LR, RL, and RR are adjustable, please refer to Fig. 3-3 on page 44. 2.3.2.2. Program Download Feature The standard functions of the MAS 35x9F can be extended or substituted by downloading up to 4 kWords (1 Word = 20 bits) of program code and additionally up to 4 kWords of coefficients into the internal RAM. 2.3.1. RAM and Registers The DSP core has access to two RAM banks denoted D0 and D1. All RAM addresses can be accessed in a 20-bit or a 16-bit mode via I2C bus. For fast access of internal DSP states the processor core has an address space of 256 data registers which also can be accessed via I2C bus. For more details, please refer to Section 3.3. on page 27. 2.3.2. Firmware and Software 2.3.2.1. Internal Program ROM and Firmware, MPEG-Decoding The firmware implemented in the program ROM of the MAS 35x9F provides MPEG 1/2 Layer 2, MPEG 1/2/ 2.5 Layer 3 and MPEG 2 AAC-decoding as well as a G.729 encoder and decoder. The DSP operating system starts the firmware in the "Application Selection Mode". By setting the appropriate bit in the Application Select memory cell (see Table 3-8 on page 32), the MPEG audio decoder or the G.729 Codec can be activated. The MPEG decoder provides an automatic standard detection mode. If all MPEG audio decoders are SDI Encoder PIO LINE IN MIC IN A/D MIX Audio Proc. D/A OUT Fig. 2-2: Encoder signal flow PIO Decoder SDIB DSP Volume Matrix S/PDIF SDO LINE IN MIC IN A/D MIX Audio Proc. D/A OUT Fig. 2-3: Decoder signal flow Micronas June 30, 2004; 6251-505-1DS 9 MAS 35x9F 2.4. Audio Codec A sophisticated set of audio converters and sound features has been implemented to comply with various kinds of operating environments that range up to highend equipment (see Fig. 2-4). 2.4.2.2. Micronas Bass (MB) DATA SHEET Mic-In Mic-Amplifier incl. Bias Deemphasis 50s / 75s Line-In A D D Q-peak Mixer Mono/Stereo Q-peak AVC Bass/Treble Headphone Amplifier DSP A Mono The Micronas Bass system (MB) was developed to extend the frequency range of loudspeakers or headphones below the cutoff frequency of the speakers. Apart from dynamically amplifying the low-frequency bass signals, the MB exploits the psycho-acoustic phenomenon of the `missing fundamental'. Adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental, while at the same time retaining the loudness of the original signal. Due to the parametric implementation of the MB, it can be customized to create different bass effects and adapted to various loudspeaker characteristics (see Section 3.4.4. and Table 3-16). 2.4.2.3. Automatic Volume Control (AVC) In a collection of tracks from different sources fairly often the average volume level varies. Especially in a noisy listening environment the user must adjust the volume to comfortably enjoy listening. The Automatic Volume Correction (AVC) solves this problem by equalizing the volume level. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see Table 3-16 on page 46). For input levels of -18 dBr to 0 dBr, the AVC maintains a fixed output level of -9 dBr. Fig. 2-5 shows the AVC output level versus its input level. For volume and baseband registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. Audio Codec D A D A Volume Balance Loudness MB Right invert Output Fig. 2-4: Signal flow block diagram of Audio Codec 2.4.1. A/D Converter and Microphone Amplifier A pair of A/D converters is provided for recording or loop-through purposes. In addition, a microphone amplifier including voltage supply function for an electret type microphone has been integrated. 2.4.2. Baseband Processing The several baseband functions are applied to the digital audio signal immediately before D/A conversion. 2.4.2.1. Bass, Treble, and Loudness Standard baseband functions such as bass, treble, and loudness are provided (refer to Table 3-16 for details). output level dBr -9 -15 -21 AVCoff AVCon -30 -24 -18 -12 -6 0 +6 input level dBr Fig. 2-5: Simplified AVC characteristics 2.4.2.4. Balance and Volume To minimize quantization noise, the main volume control is automatically split into a digital and an analog part. The volume range is -114...+12 dB with an additional mute position. A balance function is provided. 10 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.5.1. DSP Clock The DSP clock has a separate divider. In order to reduce the power consumption, it is set to the lowest acceptable rate of the synthesizer clock which is capable to allow the processor core to perform all tasks. 2.5.2. Clock Output At CLKO If the DSP or audio codec functions are enabled (bits[11] or [10] in the Control Register at I2C subaddress 6Ahex), the reference clock at pin CLKO is derived from the synthesizer clock. Dependent on the sample rate of the decoded signal a scaler is applied which automatically divides the clockout by 1, 2, or 4, as shown in Table 2-1. An additional division by 2 may be selected by setting bit[17] of the OutClkConfig memory cell (see Table 3-8 on page 32). The scaler can be disabled by setting bit[8] of this cell. The controlling at OutClkConfig is only possible as long as the DSP is operational (bit[10] of the Control Register). Settings remain valid if the DSP is disabled by clearing bit[10]. R 32 Table 2-1: Settings of bits[8] and [17] in OutClkConfig and resulting CLKO output frequencies Output Frequency at CLKO/MHz Synth. Scaler On Scaler Plus Clock bit[8]=0, bit[17]=0 Extra Division bit[8]=1 bit[8]=0, bit[17]=1 24.576 512fs 44.1 32 24.576 24 512fs 22.05 16 24.576 12 512fs 11.025 8 22.5792 24.576 768fs 5.6448 6.144 384fs 22.5792 768fs 11.2896 12.288 6.144 256fs 2.8224 3.072 384fs 22.5792 768fs 22.5792 24.576 12.288 256fs 5.6448 6.144 3.072 384fs 24.576 256fs 11.2896 12.288 6.144 12.288 2.4.3. D/A Converters One pair of Micronas' unique multibit sigma-delta D/A converters is used to convert the audio data with high linearity and a superior S/N. In order to attenuate highfrequency noise caused by noise-shaping, internal low-pass filters are included. They require additional external capacitors between pins FILTx and OUTx (see Section 5.1. on page 89). 2.4.4. Output Amplifiers The integrated output amplifiers are capable of directly driving stereo headphones or loudspeakers of 16 to 32 impedance via 22 series resistors. If more output power is required, the right output signal can be inverted and a single loudspeaker can be connected as a bridge between pins OUTL and OUTR. In this case, the source should be set to mono for optimized power. MASF DAC DAC OUTL OUTR Fig. 2-6: Bridge operation mode 2.5. Clock Management The MAS 35x9F is driven by a single crystal-controlled clock with a frequency of 18.432 MHz. It is possible to drive the MAS 35x9F with other reference clocks. In this case, the nominal crystal frequency must be written into memory location D0:348. The crystal clock acts as a reference for the embedded synthesizer that generates the internal clock. For compressed audio data reception, the MAS 35x9F may act either as the clock master (Demand Mode) or as a slave (Broadcast Mode) as defined by bit[1] in IOControlMain memory cell (see Table 3-8 on page 32). In both modes, the output of the clock synthesizer depends on the sample rate of the decoded data stream as shown in Table 2-1. In the BROADCAST MODE (PLL on), the incoming audio data controls the clock synthesizer via a PLL. In the DEMAND MODE (PLL off) the MAS 35x9F acts as the system master clock. The data transfer is triggered by a demand signal at pin EOD. fs/kHz 48 Micronas June 30, 2004; 6251-505-1DS 11 MAS 35x9F 2.6. Power Supply Concept The MAS 35x9F was designed for minimal power dissipation. In order to optimize the battery management in portable players, two DC/DC converters were implemented to supply the complete portable audio player with regulated voltages. 2.6.1. Power Supply Regions The MAS 35x9F has five power supply regions. The VDD/VSS pin pair supplies all digital parts including the DSP core, the XVDD/XVSS pin pair is connected to the digital signal pin output buffers, the AVDD0/AVSS0 supply is for the analog output amplifiers, AVDD1/AVSS1 for all other analog circuits like clock oscillator, PLL circuits, system clock synthesizer and A/D and D/A converters. The I2C interface has an own supply region via pin I2CVDD. Connecting this to the microcontroller supply assures that the I2C bus always works as long as the microcontroller is alive so that the operating modes can be selected. Beside these regions, the DC/DC converters have start-up circuits of their own which get their power via pin VSENSx. 2.6.2. DC/DC Converters The MAS 35x9F has two embedded high-performance step-up DC/DC converters with synchronous rectifiers to supply both the DSP core itself and external circuitry such as a controller or flash memory at two different voltage levels. An overview is given in Fig. 2-7 on page 13. The DC/DC converters are designed to generate an output voltage between 2.0 V and 3.5 V which can be programmed separately for each converter via the I2C interface (see table 3.3). Both converters are of bootstrapped type allowing to start up from a voltage down to 0.9 V for use with a single battery or NiCd/NiMH cell. The default output voltages are 3.0 V. Both converters are enabled with a high level at pin DCEN and enabled/disabled by the I2C interface. The MAS 35x9F DC/DC converters feature a constantfrequency, low noise pulse width modulation (PWM) mode and a low quiescent current, pulse frequency modulation (PFM) mode for improved efficiencies at low current loads. Both modes - PWM or PFM - can be selected independently for each converter via I2C interface. The default mode is PWM. In PWM mode the switching frequency of the powerMOSFET-switches is derived from the crystal oscillator. Switching harmonics generated by constant frequency operation are consistent and predictable. DATA SHEET When the audio codec is enabled, the switching frequency of the converters is synchronised to the audio codec clock to avoid interferences into the audio band. The actual switching frequency can be selected via the I2C-interface between 300 kHz and 580 kHz (for details see DCFR Register in Table 3-3 on page 24). In the PFM operation mode, the switching frequency is controlled by the converters themselves. It will be just high enough to service the output load, thus resulting in the best possible efficiency at low current loads. The PFM mode does not need a clock signal from the crystal oscillator. If both converters do not use the PWMmode, the crystal clock will be shut down as long it is not needed by other internal blocks. The synchronous rectifier bypasses the external Schottky diode to reduce losses caused by the diode forward voltage providing up to 5% efficiency improvement. By default, the P-channel synchronous rectifier switch is turned on when the voltage at pin(s) DCSOn exceeds the converter's output voltage at pin(s) VSENSn, and is turned off when the inductor current drops below a threshold. If one or both converters are disabled, the corresponding P-channel switch will be turned on, connecting the battery voltage to the DC/ DC converters output voltage at pin VSENSn. However, it is possible to individually disable both synchronous rectifier switches by setting the corresponding bits (bit[8] and [0] in DCCF-register). If both DC/DC-converters are off, a high signal may be applied at pin DCEN. This will start the converters in their default mode (PWM with 3.0 V output voltage). The PUP signal will change from low to high when both converters have reached their nominal output voltage and will return to low when both converters output voltages have dropped 200 mV below their programmed output voltage. The signal at pin PUP can be used to control the reset of an external microcontroller (see Section 2.11.2. on page 18 for details on the startup procedure). If only DC/DC-converter 1 is used, the output of the unused converter 2 (VSENS2) must be connected to the output of converter 1 (VSENS1) to make the PUP signal work properly. Also, if a DC/DC-converter is not used (no inductor connected), the pin DCSO must be left vacant. 12 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F If DC/DC converter 1 is used, it must supply the analog circuits (pins AVDD0, AVDD1) of the MAS 35x9F. If only one DC/DC converter is required, DC/DC1 must be used. Pin DCSO2 must be left vacant, pin VSENS2 should be connected to pin VSENS1. If the DC/DC converters are not used, pin DCEN must be connected to VSS, DCSOx must be left vacant. 2.6.3. Power Supply Configurations One of the following supply configurations may be used: - Power-optimized solution (recommended operation). DC/DC 1 (e.g. 2.2 V) drives the MAS 35x9F DSP and the audio circuitry, DC/DC 2 (e.g. 2.7 V) supplies controller and flash (see Fig. 2-8 on page 14) - Volume-optimized solution. DC/DC 1 (e.g. 2.7 V) supplies controller, flash and MAS 35x9F audio parts, DC/DC 2 generates e.g. 2.2 V for the MAS 35x9F DSP (see Fig. 2-9 on page 14). - Minimized external components. DC/DC 1 operates on, e.g., 2.7 V and feeds all components, DC/DC 2 remains off (see Fig. 2-10 on page 14). - External power supply. All components are powered by an external source, no DC/DC converter is used (see Fig. 2-11 on page 14). battery voltage monitor to I2C interface DCCF (76hex) 15 8 VBAT supply output 1 DCSO2 L1 22 H I2CVDD DC/DC converter 2 DCSG2 D1 VSENS2 + - C1 330 F set voltage PUP2 voltage monitor DCEN S PUP Start + - + - Vin system or crystal clock frequency divider factor 0 R 3 voltage monitor DCFR (77hex) DCCF (76hex) 7 0 DC/DC converter 1 VSS Fig. 2-7: DC/DC converter overview. The DCEN input must be connected to pin I2CVDD via start-up push button. Micronas June 30, 2004; 6251-505-1DS 13 MAS 35x9F DATA SHEET Flash VSENS1 DC/DC 1 on Flash e.g. 2.7 V VSENS1 DC/DC1 on C I2CVDD I 2C DSP C I2CVDD I 2C DSP XVDD VDD VSENS2 XVDD VDD VSENS2 DC/DC 2 on DC/DC2 off AVDD0/1 e.g. 2.7 V e.g. 2.2 V Analog Parts AVDD0/1 Analog Parts Fig. 2-8: Solution 1: Power-optimized Fig. 2-10: Solution 3: Minimized components Flash VSENS1 DC/DC1 on Flash VSENS1 DC/DC1 off C I2CVDD I2C DSP C I2CVDD I2C DSP XVDD VDD VSENS2 XVDD VDD DC/DC2 on VSENS2 DC/DC2 off External Supply AVDD0/1 e.g. 2.7 V e.g. 2.2 V Analog Parts AVDD0/1 e.g. 2.7 V Analog Parts Fig. 2-9: Solution 2: Volume-optimized Fig. 2-11: Solution 4: External power supply 14 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.8.4. Multiline Serial Audio Input (SDI, SDIB) There are two multiline serial audio input interfaces (SDI, SDIB) each consisting of the three pins SI(B)C, SI(B)I, and SI(B)D. The standard firmware only supports SDIB for bit-stream signals, while PCM-inputs should be routed to SDI. The interfaces can be configured as continuous bitstream or word-oriented inputs. For the MPEG bit streams, the word strobe pin SIBI must always be connected to VSS; bits must be sent MSB first as created by the encoder. If the download software (refer to Download Software Supplement I2SPDIF (6251-505-1PDS)) is used, the interface acts as an I2S-type with SI(B)I as a wordstrobe for PCM data. For the Demand Mode (see Section 2.5.), the signal clock coming from the data source must be higher than the nominal data transmission rate (e.g. 128 kbit/s). Pin EOD is used to interrupt the data flow whenever the input buffer of the MAS 35x9F is filled. For controlling details, please refer to Table 3-8 on page 32. 2.8.5. Multiline Serial Output (SDO) The serial audio output interface of the MAS 35x9F is a standard I2S-like interface consisting of the data lines SOD, the word strobe SOI and the clock signal SOC. It is possible to choose between two standard interface configurations (16-bit data words with word strobe time offset or 32-bit data words with inverted SOI signal). If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default. 2.8.6. Parallel Input/Output Interface (PIO) The parallel interface of the MAS 35x9F consists of the 8 data lines PI12...PI19 (MSB) and the control lines PCS, PR, PRTR, PRTW, and EOD. It can be used for data exchange with an external memory, for fast program download and for other special purposes as defined by the DSP software. For MPEG data input, the PIO interface is activated by setting bits[9] and [8] in D0:346 to 01. For the handshake protocol, please refer to Section 4.6.2.8. on page 80. 2.7. Battery Voltage Supervision Independent of the DC/DC converters, a battery voltage supervision circuit (at pin VBAT) is provided. It can be programmed to supervise one or two battery cells. The voltage is measured by subsequently setting a series of voltage thresholds and checking the respective comparison result in register 77hex. 2.8. Interfaces The MAS 35x9F uses an I2C control interface, a serial input interface for MPEG bit streams, and digital audio output interfaces for the decoded audio data (I2S and S/PDIF). S/PDIF input is available after Software download. A parallel I/O interface (PIO) may be used for fast data exchange. 2.8.1. I2C Control Interface For controlling and program download purposes, a standard I2C slave interface is implemented. A detailed description of all functions can be found in Section 3. 2.8.2. S/PDIF Input Interface The S/PDIF interface receives a one-wire serial bus signal. In addition to the signal input pin SPDI1/SPDI2, a reference pin SPDIR is provided to support balanced signal sources or twisted pair transmission lines. The synchronization time on the input signal is < 50 ms. S/PDIF input is not supported for MPEG 1/2 Layer 2/3 and MPEG 2 AAC. Micronas has developed a download software for flexible usage of the S/PDIF I/O and SDI/SDO interfaces. It is described in Download Software Supplement I2SPDIF (6251-505-1PDS). 2.8.3. S/PDIF Output The S/PDIF output of the baseband audio signals is implemented at pin SPDO since version B4. The channel status bits can be set as described in Table 3-8. Micronas June 30, 2004; 6251-505-1DS 15 MAS 35x9F 2.9. MPEG Synchronization Output The signal at pin SYNC is set to `1' after the internal decoding for the MPEG header has been finished for one frame. The rising edge of this signal can be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. As soon as the MAS 35x9F has received the SYNC reset command (see Section 4.6.2.6. on page 77), the SYNC signal is cleared. If the controller does not issue a reset command, the SYNC signal returns to `0' as soon as the decoding of the next MPEG frame is started. MPEG status and ancillary data become invalid until the frame is completely decoded and the signal at pin SYNC rises again. The controller must have finished reading all MPEG information before it becomes invalid. The MPEG Layer 2/3 frame lengths are given in Table 2-2. AAC has no fixed frame length. DATA SHEET tframe = 24...72 ms Vh Vl tread Fig. 2-12: Schematic timing of the signal at pin SYNC. The signal is cleared at tread when the controller has issued a Clear SYNC Signal command (see Section 4.6.2.6. on page 77). If no command is issued, the signal returns to `0' just before the decoding of the next MPEG frame. Table 2-2: Frame length in MPEG Layer 2/3 fs/kHz 48 44.1 32 24 22.05 16 12 11.025 8 Frame Length Layer 2 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms not available not available not available Frame Length Layer 3 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms 48 ms 52.24 ms 72 ms 16 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.10.MP3 Block Input Mode A new so-called MP3 block input mode is now available which improves the input timing behavior of the MAS 35x9F MPEG 1/2/2.5 Layer 3 decoder. The following sections provide a detailed description of this new mode. 2.10.1.Functional Description of the MP3 Block Input Mode In MP3 block input, the MAS 35x9F generates a demand for new input data each time one of its two input buffers becomes available. The controller then has to send one block of input data via the serial interface SDIB. The block size is 2048 byte. The demand is signalized via a pulse on the EOD pin. Fig. 2-13 shows that the number of interrupts per second does not depend on the data rate at the serial interface. The maximum input data bit clock rate supported by the MAS 35x9F for all MPEG audio sampling rates is 1.4 MHz. Table 2-3 shows the average number of interrupts per second for several typical MP3 bit rates. The time period between two interrupts may vary slightly even for fixed bit rate input streams due to the MP3 specific bit reservoir. Table 2-3: MP3 bit rate vs. number of interrupts Bit Rate [kbit/s] 320 256 224 192 160 128 112 96 80 64 Number of Interrupts [1/s] 20 16 14 12 10 8 7 6 5 4 Interrupt a) SIC Interrupt b) SIC Data blocks in a) and b) contain the same number of bytes. Data block a) is sent with a lower data rate than data block b). t Fig. 2-13: Data Block Timing Diagram Micronas June 30, 2004; 6251-505-1DS 17 MAS 35x9F 2.10.2.Setup Table 3-10 on page 39 lists the new bits, UIC cells, and registers to setup the MP3 block input mode. 2.10.2.1.Resync Timeout In case the MP3 decoder loses the synchronization (e.g. due to corrupted input data), the output is softly muted and a resync loop is entered where the MAS 35x9F can be accessed via I2C. The loop is left and the re-synchronization procedure continues in any of the following cases: - the last input data block is fully sent, - the Validate bit of IOControlMain is set (D0:346, bit[0]), - the timeout is reached (ResyncTimeout in Table 3-10), the end bit is set (this bit will be reset by the MAS 35x9F). 2.10.2.2.Detailed Setup After the MPEG audio decoder application has been selected, the following settings enable the MP3 block decoding process. Play MP3 1. Write 0x318 into SerialInConfig. 2. Write IOControlMain with bit[2] and bit[0] equal one. 3. Write IOControlMain with bit[2] equals zero and bit[0] equals one. 4. Write 0x0 into ResyncTimeout. 5. Write 0x0 into SoftMute. 6. Enable EODQ interrupt for sending data in controller. 7. Set StartBit in MP3BlockConfig. 8. Send data block of 2048 byte when EODQ goes high. Stop/Pause MP3 1. Write 0x1 into SoftMute. 2. Clear start bit in MP3BlockConfig. 2.11.Default Operation DATA SHEET This sections refers to the standard operation mode "power-optimized solution" (see Section 2.6.3.). 2.11.1. Stand-by Functions After applying the battery voltage, the system will remain stand-by, as long as the DCEN pin level is kept low. Due to the low stand-by current of CMOS circuits, the battery may remain connected to DCSOn/VSENSn at all times. 2.11.2.Power-Up of the DC/DC Converters and Reset The battery voltage must be applied to pin DCSOn via the 22 H inductor and, furthermore, to the sense pin VSENSn via a Schottky diode (see Fig. 2-7 on page 13). For start-up, the pin DCEN must be connected via an external "start" push button to the I2CVDD supply, which is equivalent to the battery supply voltage (> 0.9 V) at start-up. The supply at DCEN must be applied until the DC/DC converters have started up (signal at pin PUP) and then removed for normal operation. As soon as the output voltage at VSENSn reaches the default voltage monitor reset level of 3.0 V, the respective internal PUPn bit will be set. When both PUPn bits are set, the signal at pin PUP will go high and can be used to start and reset the microcontroller. Before transmitting any I2C commands, the controller must issue a power-on reset to pin POR. The separate supply pin I2CVDD ensures that the I2C interface works independently from the DSP or the audio codec. Now the desired supply voltage can be programmed at I2C subaddress 76hex. 18 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.11.2.1.Important Advice for Turn-on and Operating Voltage Before the 2.2 V are programmed at the DCDC converter, DSP+Codec must be enabled. Operating and Turn-Off is possible down to 2.2 V. The sequence should be similar to the following: 1. Start DCDC 2. Set DCDC to 2.5 V Turn on DSP+Codec Write App-Select memory cell Read App-Running Mem cell If okay: Set DCDC to 2.2 V Set other mem cells Set other codec registers ..... 3. Demute...send data 4. Mute...stop data.....loop "3)" "4)"... 5. Turn off DSP+Codec goto "2)" etc..... The signal at pin PUP will return to low only when both PUPn flags (I2C subaddress 76hex) have returned to zero. Care must be taken when changing both DC/DC output voltages to higher values. In this case, both output voltages are momentarily insufficient to keep the PUPn flags up; the resulting dip in the signal at the PUP pin may, in turn, reset the microcontroller. To avoid this condition, only one DC/DC output voltage should be changed at a time. Before modifying the second voltage, the microcontroller must wait for the PUPn flag of the first voltage to be set again. If only DC/DC converter 1 is used, the reference voltage of the second, unused converter should be set to a lower value than that of converter 1, and its pin VSENS2 should be connected to VDD. The operating mode pulse width modulation, or pulse frequency modulation, are controlled at I2C subaddress 76hex, the operating frequency at I2C subaddress 77hex. Micronas June 30, 2004; 6251-505-1DS 19 MAS 35x9F 2.11.3. Reset Signal Specification After power-up, a reset signal should be applied to the pin POR by the microcontroller as follows: DATA SHEET VDD 2.2 V min. VDD POR 2.2 V min. POR see Note 1 0.5 s min. delay I2C access works without additional delay from this point time Fig. 2-14: Reset signal at pin POR Note: The slew rate of POR should be as high as possible, but must be glitch-free in any case. Slew rate typ.: 1 s for 10% to 90% level transition, Slew rate max.: 20 s for 10% to 90% level transition. 20 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.11.5.Start-up of the Audio Codec Before enabling the audio codec, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The audio codec is enabled by setting the appropriate bit at the Control register (I2C subaddress 6Ahex). After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C. The A/D and the D/A converters must be switched on explicitly (register 00 00hex at I2C subaddress 6Chex). The D/A converters may either accept data from the A/D converters or the output of the DSP, or a mix of both1) (register 00 06hex and 00 07hex at I2C subaddress 6Chex). Finally, an appropriate output volume (register 00 10hex at I2C subaddress 6Chex) must be selected. 2.11.6.Power-Down All analog outputs should be muted and the A/D and the D/A converters must be switched off (register 00 10hex and 00 00hex at I2C subaddress 6Chex). The DSP and the audio codec must be disabled (clear DSP_EN and CODEC_EN bits in the Control register, I2C subaddress 6Ahex). By clearing both DC/DC enable flags in the Control register (I2C subaddress 6Ahex), the microcontroller can power down the complete system. 2.11.4.Control of the Signal Processing Before starting the DSP, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The DSP is enabled by setting the appropriate bit in the Control register (I2C subaddress 6Ahex). The nominal frequency of the crystal oscillator must be written into D0:348. After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C. Input and output control is performed via memory location D0:346 and D0:347. The serial input interface SDIB is the default. The decoded audio can be routed to either the S/PDIF, the SDO and the analog outputs. The output clock signal at pin CLKO is defined in D0:349. All changes in the D0 memory cells become effective synchronously upon setting the LSB of Main I/O Control (see Table 3-8 on page 32). Therefore, this cell should always be written last. The digital volume control (see Table 3-8 on page 32) is applied to the output signal of the DSP. The decoded audio data will be available at the SPDO output interface in the next version. The DSP does not have to be started if its functions are not required, e.g., for routing audio through the codec part of the IC via the A/D and the D/A converters. 1) mixer available in version A2 and later; in version A1, please use selector 00 0Fhex. Micronas 21 June 30, 2004; 6251-505-1DS MAS 35x9F 3. Controlling 3.1. I2C Interface Controlling between the MAS 35x9F and the external controller is done via an I2C slave interface. 3.1.1. Device Address The device addresses are 3C/3Ehex (device write "DW") and 3D/3Fhex (device read, "DR") as shown in Table 3-1. The device address pair 3C/3Dhex applies if the DVS pin is connected to VSS, the device address pair 3E/3Fhex applies if the DVS pin is connected to I2CVDD. Table 3-1: I2C device address A7 0 A6 0 A5 1 A4 1 A3 1 A2 1 A1 DVS W/R 0/1 nibble. DATA SHEET - Data values in nibbles are always shown in hexadecimal notation. - A hexadecimal 20-bit number d is written, e.g. as d = 17C63hex, its five nibbles are d0 = 3hex, d1 = 6hex, d2 = Chex, d3 = 7hex, and d4 = 1hex. - Variables used in the following descriptions: IC address: DW3C/3EhexI2C device write DR3D/3FhexI2C device read DSP core: data_write68hexDSP data write data_read69hexDSP data read Codec: codec_write6Chexcodec write codec_read6Dhexcodec read - Bus signals S Start P Stop A ACK = N NAK = W Wait = I2C clock synchronization is used to slow down the interface if required. 3.1.2. I2C Registers and Subaddresses The interface uses one level of subaddresses. The MAS 35x9F interface has 7 subaddresses allocated for the corresponding I2C registers. The registers can be divided into three categories as shown in Table 3- 2. The address 6Ahex is used for basic control, i.e. reset and task select. The other addresses are used for data transfer from/to the MAS 35x9F. The I2C registers of the MAS 35x9F are 16 bits wide, the MSB is denoted as bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, MSB sent first); thus, for each register access, two 8-bit data words must be sent/received via I2C bus. 3.1.3. Naming Convention The description of the various controller commands uses the following formalism: - Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don't care - Memory addresses, like D1:89f, are always in hexadecimal notation. - A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant Acknowledge Not acknowledge I2C clock line is held low while the MAS 35x9F is processing the current I2C command - Symbols in the telegram examples < Start Condition > Stop dd data bytes xx ignore All telegram numbers are hexadecimal, data originating from the MAS 35x9F are represented as gray letters. Example: 3.2. Direct Configuration Registers The task selection of the DSP and the DC/DC converters are controlled in the direct configuration registers CONTROL, DCCF, and DCFR. 22 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 3.2.1. Write Direct Configuration Registers S DW W A subaddr. A d3,d2 A d1,d0 A P Table 3-2: I2C subaddresses Subaddress (hex) I2CRegister Name Function Direct Configuration 6A CONTROL Controller writes to MAS 35x9F CONTROL register Controller writes to first DC/DC configuration register Controller writes to second DC/DC configuration register The write protocol for the direct configuration registers only consists of device address, subaddress and one 16-bit data word. 3.2.2. Read Direct Configuration Register S DW W A subaddr. A S d3,d2 DR A W A N P 76 DCCF d1,d0 77 DCFR To check the PUP1 and PUP2 power-up flags, it is necessary to read back the content of the direct configuration registers. DSP Core Access 68 69 data_write data_read Controller writes to MAS 35x9F DSP Controller reads from MAS 35x9F DSP Codec Access 6C codec_write Controller writes to MAS 35x9F codec register Controller reads from MAS 35x9F codec register 6D codec_read Example: I2C write access S DW W A subaddress A high byte data A low byte data W A P Example: I2C read access S DW W A subaddress A S DR A W A W N P high byte data low byte data SDA SCL S 1 0 P W = Wait A = Acknowledge (Ack) N = Not Acknowledge (NAK) S = Start P = Stop Fig. 3-1: Example of an I2C bus protocol for the MAS 35x9F (MSB first; data must be stable while clock is high) Micronas June 30, 2004; 6251-505-1DS 23 MAS 35x9F DATA SHEET Table 3-3: Direct configuration registers I2C Subaddress (hex) 6A Function Name Control Register (reset value = 3000hex) bit[15:14] Analog supply voltage range Code 00 01 10 11 AGNDC 1.1 V 1.3 V 1.6 V reserved recommended for voltage range of AVDD 2.0 ... 2.4 V (reset) 2.4 ... 3.0 V 3.0 ... 3.6 V reserved CONTROL Higher voltage ranges permit higher output levels and thus a better signal-tonoise ratio. bit[13] bit[12] Enable DC/DC 2 (reset=1) Enable DC/DC 1 (reset=1) Enable and reset audio codec2) Enable and reset DSP core2) Both DC/DC converters are switched on by default with DCEN = high (1). bit[11] bit[10] For normal operation (MPEG-decoding and D/A conversion), both, the DSP core and the audio codec have to be enabled after the power-up procedure. The DSP can be left off if an audio signal is routed from the analog inputs to the analog outputs (set bit[15] in codec register 00 0Fhex). The audio codec can be left off if the DSP uses digital inputs and outputs only. bit[9] bit[8] bit[7] bit[6:0] 1) 2) Reset codec Reset DSP core Enable crystal input clock divider of 1.5 (extended range up to 28 MHz)1) Reserved, must be set to zero refer to Section 4.6.3. on page 81 refer to Section 2.11.2.1. 24 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-3: Direct configuration registers, continued I2C Subaddress (hex) 76 Function Name DCCF Register (reset = 5050hex) DC/DC Converter 2 bit[15] bit[14:11] PUP2: Voltage monitor 2 flag (readback) Converter 2 output voltage with respect to VREF2) Code 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 01001) 00111) 00101) bit[10] Mode 1 0 Nominal output volt. 3.5 V 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V set level of PUP2 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V reset level of PUP2 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V (reset) 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.0 V DCCF pulse frequency modulation (PFM) pulse width modulation (PWM) (reset) bit[9:8] Reserved, must be set to zero The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. DC/DC Converter 1 bit[7] bit[6:3] bit[2] PUP1: Voltage monitor 1 flag (readback) Converter 1 output voltage at VSENS1 with respect to VREF (see bits 14 to 11)2) Mode 1 0 pulse frequency modulation (PFM) pulse width modulation (PWM) (reset) bit[1:0] Reserved, must be set to zero Note, that the reference voltage for DC/DC converter 1 is derived from the main reference source supplied via pin AVDD1. Therefore, if this DC/DC converter is used, its output must be connected to the analog supply. The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 1) 2) refer to Section 4.3.3. on page 60 refer to Section 2.11.2.1. Micronas June 30, 2004; 6251-505-1DS 25 MAS 35x9F Table 3-3: Direct configuration registers, continued I2C Subaddress (hex) 77 Function Name DATA SHEET DCFR Register (reset = 00hex) Battery Voltage Monitor bit[15] Comparison result (readback) 1 input voltage at pin VBAT above defined threshold 0 input voltage at pin VBAT below defined threshold Number of battery cells 0 1 cell (range 0.8...1.5 V) (reset) 1 2 cells (range 1.6...3.0 V) Voltage threshold level 1 cell 2 cells 1111 1.5 3.0 V 1110 1.45 2.9 V ... 0010 0.85 1.7 V 0001 0.8 1.6 V 0000 battery voltage supervision off (reset) Reserved, must be set to 0 DCFR bit[14] bit[13:10] bit[9:8] The result is stable 1 ms after enabling. The setup time for switching between two thresholds is negligibly small. For power management reasons, the battery voltage monitor should be switched off by setting bit[13:10] to zero when the measurement is completed. DC/DC Converter Frequency Control (PWM) bit[7:4] bit[3:0] Reserved, must be set to 0 Frequency of DC/DC converter Reference: 24.576 0111 315.1 0110 323.4 0101 332.1 0100 341.3 0011 351.1 0010 361.4 0001 372.4 0000 384.0 1111 396.4 1110 409.6 1101 423.7 1100 438.9 1011 455.1 1010 472.6 1001 491.5 1000 512.0 22.5792 289.5 297.1 305.1 313.6 322.6 332.0 342.1 352.8 364.2 376.3 389.3 403.2 418.1 434.2 451.6 470.4 18.432 MHz 297.3 kHz 307.2 kHz 317.8 kHz 329.1 kHz 341.3 kHz 354.5 kHz 368.6 kHz 384.0 kHz (reset) 400.7 kHz 418.9 kHz 438.9 kHz 460.8 kHz 485.1 kHz 512.0 kHz 542.1 kHz 576.0 kHz If the audio codec is not enabled (bit[11] of the CONTROL register at I2C-subaddress 6Ahex is zero), the clock for the DC/DC converters is directly derived from the crystal frequency (nominal 18.432 MHz). Otherwise, the synthesizer clock is used as the reference (please refer to the respective column in Table 2-1 on page 11). 26 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 3.3. DSP Core 3.3.1. Access Protocol The I2C data register is used to communicate with the internal firmware of the MAS 35x9F. It is readable (subaddress "data_read") and writable (subaddress "data_write") and also has a length of 16 bits. The data transfer is done with the most significant bit (m) first. Table 3-4: Data register bit assignment 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 m l S DW W A data_write A Code,... A ...,... A ... Fig. 3-2: General core access protocol Table 3-5 gives an overview over the different commands which the DSP Core receives via the I2C data register. The "Code" is always the first data nibble transmitted after the "data_write" subaddress byte. A second auxiliary code nibble is used for the short memory (16-bit) access commands. The MAS 35x9F firmware scans the I2C interface periodically and checks for pending or new commands. The commands are then executed by the DSP during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. However, due to some time critical firmware parts, a certain latency time for the response has to be expected at the locations marked with a "W" (= wait). The theoretical worst case response time does not exceed 4 ms. However, the typical response time is less than 0.5 ms. Due to the 16-bit width of the I2C data register, all actions transmit telegrams with multiples of 16 data bits. A special command language is used that allows the controller to access the DSP registers and RAM cells and thus monitor internal states, set the parameters for the DSP firmware, control the hardware, and even provide a download of alternative software modules. The DSP commands consist of a "Code" which is sent to the I2C data register together with additional parameters. Table 3-5: Basic controller command codes Code (hex) 0...3 5 6 7 a b c d e f Command Run Read Ancillary Data Fast Program Download Read IC Version Read from Register Write to Register Read D0 Memory Read D1 Memory Write D0 Memory Write D1 Memory Function Start execution of an internal program. Run with start address 0 means freeze the operating system. The controller reads a block of MPEG Ancillary Data from the MAS 35x9F The controller downloads custom software via the PIO interface The controller reads the version information of the IC The controller reads an internal register of the MAS 35x9F The controller writes an internal register of the MAS 35x9F The controller reads a block of the DSP memory The controller reads a block of the DSP memory The controller writes a block of the DSP memory The controller writes a block of the DSP memory Micronas June 30, 2004; 6251-505-1DS 27 MAS 35x9F 3.3.2. Data Formats The internal data word size is 20 bits. All RAMaddresses can be accessed in a 20-bit mode via I2C bus. Because of the 16-bit width of the I2C data register the full transfer of all 20 bits requires two 16-bit I2C words. Some commands only access the lower 16 bits of a cell. For fast access of internal DSP states the processor core also has an address space of 256 data registers. The internal data format is a 20 bit two's complement denoted "r". If in some cases a fixed point notation "v" is necessary. The conversion between the two forms of notation is done as follows: r = v*524288.0+0.5; (-1.0 v < 1.0) v = r/524288.0; (-524288 < r < 524287) 3.3.2.1. Run and Freeze (Codes 0hex to 3hex) S DW W A data_write A a3,a2 A a1,a0 W A P DATA SHEET The entry point of the default software will be accessed automatically after a reset, thus issuing a Run or Freeze command is only necessary for starting downloaded software or special program modules which are not part of the standard set. 3.3.2.2. Read Register (Code Ahex) 1) send command S DW W A data_write A a,r1 A r0,0 W A P 2) get register value S DW x,x W A A data_read A x,d4 W A S d3,d2 DR A W A W N P d1,d0 The MAS 35x9F has an address space of 256 DSPregisters. Some of the registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the internal program flow. In Table 3-7, the registers of interest are described in detail. In contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. Example: Read the content of register C8hex: S DW W A data_write A b,r1 d3,d2 A A r0,d4 d1,d0 W W A A P The Run command causes the start of a program part at address a = (a3,a2,a1,a0). Since nibble a3 is also the command code (see Table 3-5), it is restricted to values between 0 and 3. This command is used to start alternate code or downloaded code from a RAMarea that has been configured as program RAM. If the start address is 1000hex a < 3FFFhex and the respective RAM area has been configured as program RAM (see Table 3-7 on page 31), the MAS 35x9F continues execution with a custom program already downloaded to this area. Example 1: Start program execution at address 345hex: define register and read The controller writes the 20-bit value (d = d4,d3,d2, d1,d0) into the MAS 35x9F register (r = r1,r0). A list of registers needed for control purposes is given in Table 3-7. Example: Writing the value 81234hex into the register with the number AAhex: 28 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 3.3.2.6. Write Memory (Codes Ehex and Fhex) The memory areas D0 and D1 can be written by using the codes Ehex and Fhex, respectively. S DW W A data_write A e,0 n3,n2 c,0 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P x,x S d3,d2 DR A W A W A A x,x A x,d4 W A a3,a2 d3,d2 A A A A 0,0 n1,n0 a1,a0 d1,d0 W W W W A A A A 3.3.2.4. Read Memory (Codes Chex and Dhex) The MAS 35x9F has 2 memory areas of 2048 words denoted D0 and D1. The memory areas D0 and D1 can be written by using the codes Chex and Dhex, respectively. 1) send command (Read D0) S DW W A data_write A ....repeat for n data values.... x,d4 W A d3,d2 A d1,d0 W A P 2) get register value S DW x,x W A A data_read A x,d4 W A d1,d0 ....repeat for n data values.... x,x A x,d4 W A d3,d2 A d1,d0 W N P With the Write D0/D1 Memory command n 20-bit memory cells in D0 can be initialized with new data. Example: Write 80234hex to D1:456 has the following I2C protocol: <3a 68 f0 00 00 01 04 56 00 08 02 34> write D1 memory 1 word to write start address value = 80234hex The Read D0 Memory command gives the controller access to all 20 bits of the D0/D1 memory cells. The telegram to read 3 words starting at location D1:100 is 1) send command (e.g. Short Read D0) S DW W A data_write A c,4 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 3.3.2.7. Short Write Memory (Codes E4hex and F4hex) S DW W A data_write A A A A e,4 n3,n2 a3,a2 d3,d2 A A A A 0,0 n1,n0 a1,a0 d1,d0 W W W W A A A A ....repeat for n data values.... A d3,d2 A d1,d0 W A P 2) get register value S DW W A data_read A S d3,d2 DR A W A W A For faster access only the lower 16 bits of each memory cell are written. The 4 MSBs of the cell are cleared. The command uses the same codes Ehex and Fhex for D0/D1 as for the 20-bit command but followed by a 4 rather than a 0. 3.3.2.8. Clear SYNC Signal (Code 5hex) S DW W A data_write A 5,0 A 0,0 W A P d1,d0 ....repeat for n data values.... d3,d2 A d1,d0 W N P This command is similar to the normal 20 bit read command and uses the same command code Chex and Dhex for D0 and D1 memory, respectively, however it is followed by a 4hex rather than a 0hex. Example: Read 16 bits of D1:123 has the following I2C protocol: After a successful decoding of an MPEG frame the signal at pin SYNC rises and thus generates an interrupt event for the microcontroller. Issuing this command lets the signal at pin SYNC return to `0'. Micronas June 30, 2004; 6251-505-1DS 29 MAS 35x9F 3.3.2.9. Default Read The Default Read command is the fastest way to get information from the MAS 35x9F. Executing the Default Read in a polling loop can be used to detect a special state during decoding. S DW W A data_read A S DR d3,d2 W A A d1,d0 W N P DATA SHEET - Issue a Run command to start program execution at entry point of downloaded code Example for Fast Program Download command: Download 5 words starting at D0:800, then download 4 words starting at D1:200: The Default Read command immediately returns the lower 16 bit content of a specific RAM location as defined by the pointer D0:ffb. The pointer must be loaded before the first Default Read action occurs. If the MSB of the pointer is set, it points to a memory location in D1 rather than to one in D0. Example: For watching D1:123 the pointer D0:ffb must be loaded with 8123hex: Now transfer 5 20-bit words via the parallel PIO-port: d4,d3 d4,d3 d4,d3 d2,d1 d2,d1 d2,d1 d0,d4 d0,d4 d0,x d3,d2 d3,d2 d1,d0 d1,d0 Now the Default Read commands can be issued as often as desired: initiate download of 4 words start at address D1:200 Now transfer 4 20-bit words via the parallel PIO-port: d4,d3 d4,d3 d2,d1 d2,d1 d0,d4 d0,d4 d3,d2 d3,d2 d1,d0 d1,d0 3.3.2.10.Fast Program Download (Code 6hex) S DW W A data_write A 6,n2 a3,a2 A A n1,n0 a1,a0 W W A A P The Fast Program Download command introduces a data transfer via the parallel port. n = n2,n1,n0 denotes the number of 20-bit data words to be transferred, a = a3,a2,a1,a0 gives the start address. The data must be organized in two times five nibbles to get two words of 20-bit length. If the number n of 20-bit data words is odd, the very last word has to be padded with one additional nibble. The download must be initiated in the following order: - Issue Freeze command - Stop all DMA-transfers - Issue Fast Program Download command - Download code via PIO-interface - Switch appropriate memory area to act as program RAM (register EDhex) 3.3.2.11.Serial Program Download Program downloads may also be performed via the I2C-interface by using the Write D0/D1 Memory commands. A similar command sequence as in the Fast Program Download (Freeze, stop transfers...) applies. 30 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 01 0 7,0 A 0,0 W A P 3.3.2.12.Read IC Version (Code 7hex) 1) send command S DW W A data_write A 02 (hex) Derivate (0..F) Version character (0 = "A",.., F = "P") 1 02 2) get version information S DW W A data_read A S n3,n2 d3,d2 DR A A W A W W A N P Version number (01..FF) n1,n0 d1,d0 3.3.3. List of DSP Registers The PSelect_Shadow register in Table 3-7 is used to switch four RAM areas from data to program usage and thus enabling the DSP's program counter to access downloaded program code stored at these locations. For normal operation (firmware in ROM), this register must be kept to zero. Note: DSP registers not given in Table 3-7 must not be written. With this command the version of the IC is read in two 16 bit words. The first word n = n3,n2,n1,n0 contains the IC's major number (one nibble for each digit). The second word (d = d3,d2,d1,d0) returns the version as shown in Table 3-6. Table 3-6: Second word of version information Bit 15:12 11:8 Nibble d3 d2 Content IC family derivate Coded character of order version (add 41hex to the content of d2 to get ASCII) Digit of order version 3.3.4. List of DSP Memory Cells Among the user interface control memory cells there are some which have a global meaning and some which control application specific parts of the DSP core. In Table 3-8 and Table 3-9, this is reflected by the key words All, MPEG, and G.729. 7:0 d1,d0 Example: Read the version information for MAS 35x9F, derivate 0, order version B2: Table 3-7: Program Download registers Address (hex) 6B R/W R/W Function Configuration of Variable RAM Areas bit[19] bit[18] bit[17] bit[16] Affected RAM area D0:800 ... D0:BFF D0:C00 ... D0:FFF D1:800 ... D1:BFF D1:C00 ... D1:FFF Mode Download Default (hex) 0000 Name PSelect_Shadow For details of program code download please refer to Section 3.3.2.10. on page 30. Micronas June 30, 2004; 6251-505-1DS 31 MAS 35x9F 3.3.4.1. Application Selection and Application Running The AppSelect cell is a global user interface configuration cell, which has to be written in order to start a specific application. The AppRunning cell is a global user interface status cell, which indicates, which application loop is actually running. 1. Write "0" to AppSelect 2. Check AppRunning for "0" 3. Write value to AppSelect according to Table 3-8 (determines start time of Application program) 4. Apply necessary/wanted control settings (D0:346..357) 3.3.4.2. Application Specific Control DATA SHEET The configuration of the MPEG Layer 2/3, AAC decoding and the G.729 codec firmware is done via the control memory cells described in Table 3-9. The changes applied to any of the control memory cells have to be validated by setting bit[0] of memory cell Main I/O Control. This bit will be reset automatically after the changes have been taken over by the DSP. The status memory cells in Table 3-11 are used to read the decoder status and to get additional MPEG bitstream information. Note: DSP memory cells not given in Table 3-8 or Table 3-9 must not be written. Table 3-8: D0 control memory cells: mode selection Memory Address (hex) D0:34b Function Name Application Selection All AppSelect AppSelect is used for selecting an application. This is done by setting the appropriate bit to one. It is principally allowed to set more than one bit to one, e.g. setting AppSelect to 1Chex will select all MPEG audio decoders. The auto-detection feature will automatically detect the Layer 2, Layer 3, or AAC data. Setting bit[0] or bit[1] will make the DSP loop in the OS loop or the Top Level loop respectively. To add/remove MPEG layers while running in MPEG decoding mode (e.g. change from Layer 2, Layer 3 (0Chex) to Layer 2, Layer 3, AAC (1Chex)), the application selection has to be reset to 00hex before writing the new value. bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] D0:34c G.729 Codec MPEG AAC Decoder MPEG Layer 3 Decoder MPEG Layer 2 Decoder Top Level Operating System All AppRunning Application Running The AppRunning cell is a global user interface status cell, that indicates which application loop is actually running. Prior to writing any of the configuration registers or memory cells (except AppSelect), it has to be checked whether the appropriate bit(s) in the AppRunning cell is set. bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] G.729 Codec MPEG AAC Decoder MPEG Layer 3 Decoder MPEG Layer 2 Decoder Top Level Operating System 32 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-9: D0 control memory cells Memory Address (hex) D0:346 Function Name Main I/O Control (reset = 8025hex) MPEG IOControlMain IOControlMain is used for selecting/deselecting the appropriate data input interface and for setting up the serial data output interface. In serial input mode the coded audio data (Layer 2, Layer 3, AAC) is expected at the serial input interface SDIB (default). In the 8-bit-parallel input mode the PIO pins PI[19:12] are used. bit[15] MP3 block input selection 0: MP3 block input mode OFF 1: MP3 block input mode ON Invert serial output clock (SOC) 0 (reset) do not invert SOC 1 invert SOC Reserved, must be set to zero Serial data output delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe Reserved, must be set to zero Input Select Main 00 (reset) serial input at interface B 01 parallel input at PIO pins PI[19...12] 10 reserved for future use 11 reserved for future use Reserved, must be set to zero SDO Word Strobe Invert 0 do not invert 1 (reset) invert outgoing word strobe signal Bits per Sample at SDO 0 (reset) 32 bits/sample 1 16 bits/sample Reserved, must be set to zero Serial data input interface B clock invert (pin SIBC) 0 not inverted (data latched at rising clock edge) 1 (reset) incoming clock signal is inverted (data latched at falling clock edge) 0 (reset) 1 bit[0] Validate 0 (reset) 1 DEMAND MODE (PLL off, MAS 35x9F is clock master) BROADCAST MODE (PLL on, clock of MAS 35x9F locks on data stream) no forced evaluation of control memory cells changes in control memory will become effective bit[14] bit[13:12] bit[11] bit[10] bit[9:8] bit[7:6] bit[5] bit[4] bit[3] bit[2] bit[1] Bit[0] is reset after the DSP has recognized the changes. The controller should set this bit after the other D0 control memory cells have been initialized with the desired values. Micronas June 30, 2004; 6251-505-1DS 33 MAS 35x9F Table 3-9: D0 control memory cells, continued Memory Address (hex) D0:347 Function Name DATA SHEET Interface Status Control (reset = 05hex) MPEG InterfaceControl This control cell allows to enable/disable the data I/O interfaces. In addition, the clock of the output data interface interfaces, S/PDIF and SDO, can be set to a low-impedance mode. bit[6] S/PDIF input selection (used for download modules) 0 (reset) select S/PDIF input 1 1 select S/PDIF input 2 Enable/disable S/PDIF output 0 (reset) enable S/PDIF output 1 S/PDIF output (invalid) Reserved, must be set to zero Enable/disable serial data output SDO 0 (reset) SDO valid data 1 SDO invalid data Output clock characteristic (SDO and S/PDIF outputs) 0 low impedance 1 (reset) high impedance reserved, must be set to zero Enable/Disable SDI1) 0 enable 1 (reset) disable bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] Both digital outputs, S/PDIF and I2S, and the D/A converters may use the decoded audio independent of each other. Changes at this memory address must be validated by setting bit[0] of D0:346hex. D0:348 Oscillator Frequency (reset = 18432dec) bit[19:0] oscillator frequency in kHz All OfreqControl In order to achieve a correct internal operating frequency of the DSP, the nominal crystal frequency has to be deposited into this memory cell. Changes at this memory address must be validated by setting bit[0] of D0:346hex. 1) Note: The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value). 34 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-9: D0 control memory cells, continued Memory Address (hex) D0:349 Function Name Output Clock Configuration (affects pin CLKO) (reset = 80000hex) bit[19] CLKO configuration 0 output clock signal at CLKO 1 (reset) CLKO is tristate All OutClkConfig The CLKO output pin of the MAS 35x9F can be disabled via bit[19]. bit[18] bit[17] Reserved, must be set to zero Additional division by 2 if scaler is on (bit[8] cleared) 0 (reset) oversampling factor 512/768 1 oversampling factor 256/384 Reserved, must be set to zero Output clock scaler 0 (reset) set output clock according to audio sample rate (see Table 2-1) 1 output clock fixed at 24.576 or 22.5792 MHz bit[16:9] bit[8] For a list of output frequencies at pin CLKO please refer to Table 2-1. bit[7:0] reserved, must be set to zero Changes at this memory address must be validated by setting bit[0] of D0:346. D0:350 Soft Mute %0 (reset) %1 D0:351 mute off mute on SpdOutBits MPEG SoftMute S/PDIF channel status bits category code setting (reset = 8200hex) All Micronas June 30, 2004; 6251-505-1DS 35 MAS 35x9F Table 3-9: D0 control memory cells, continued Memory Address (hex) D0:34d Function Name DATA SHEET Operation Mode Selection (reset = 0hex) bit[19:7] bit[6] Reserved, set to 0 Page headers 0 enable 1 disable G.729 UserControl The register is used to switch between basic G.729 operation modes. If the page headers bit is 0, a header frame is transfered before each page of 50 data frames. If the header bit is 1, all the frames are G.729 data frames. Please (see Section 3.3.8. on page 44). bit[5:4] Decoding speed 00 8 kHz (normal) 01 6 kHz (slow) 10 12 kHz (fast) 11 not allowed The recording (encoding) is always done with a sampling rate of 8 kHz. During decoding this control can be used to speed up or slow down the playback. bit[3] bit[2] Reserved, set to 0 Pause encoder/decoder 0 normal operation 1 pause If the pause bit is set, the processing continues until the current page is finished and then en-/decoding is paused. The pause mode lasts until the pause bit is cleared again or the mode is set to 0. bit[1:0] Mode 00 01 10 11 idle decode not allowed encode To switch to encoder operation mode, UserControl has to be set to 3hex. Then 50 frames are encoded and sent via the PIO interface. This is repeated until the UserControl register is changed. If the transmission of headers is enabled, each page of 50 frames is preceeded by a header frame as shown in Fig. 3-4 on page 44. To switch to decoder operation mode, UserControl has to be set to 1hex. For decoding with slow speed, UserControl must be 11hex, for decoding with fast speed it must be 21hex. Then the decoder is requesting several frames via the PIO interface to fill its internal buffer. If enough data is available, 50 frames are decoded. This is repeated until the UserControl register is changed. If the transmission of headers is enabled, a header frame has to be sent before each page of 50 frames (see Fig. 3-4 on page 44). To switch off the encoder or decoder, UserControl has to be set to 0hex. Then the encoding/decoding and sending/receiving of frames continues until the end of the current page and the operation mode is set to stop. 36 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-9: D0 control memory cells, continued Memory Address (hex) D0:34e Function Name I2S Audio Input/Output Interface (reset = 60hex) bit[19:15] bit[14] Reserved, set to 0 Output clock signal 0 standard signal 1 inverted signal Reserved, set to 0 Additional delay of input data related to word strobe 0 no delay 1 1 bit delay Additional delay of output data related to word strobe 0 no delay 1 1 bit delay Reserveded, set to 0 Input word strobe signal 0 standard signal 1 inverted signal Output word strobe signal 0 standard signal 1 inverted signal Wordlength 0 32 bits/sample 1 16 bits/sample G.729 SDISDOConfig bit[13] bit[12] bit[11] bit[10:7] bit[6] bit[5] bit[4] This setting affects the wordlength on the SDI and SDO interfaces. bit[3] Input clock signal 0 standard signal 1 inverted signal Reserved, set to 0 bit[2:0] Changes become effective when the codec is started or the mode is changed by writing to the UserControl memory cell. Micronas June 30, 2004; 6251-505-1DS 37 MAS 35x9F Table 3-9: D0 control memory cells, continued Memory Address (hex) D0:34f Function Name DATA SHEET Interface Status Control (reset = 25hex) This control cell is used to enable/disable interfaces in G.729 mode. bit[6],[4] bit [5] bit[3] reserved, must be set to zero reserved, must be set to one Enable/disable serial data output SDO 0 (reset) SDO valid data 1 SDO invalid data Output clock characteristic (SDO and S/PDIF outputs) 0 low impedance 1 (reset) high impedance reserved, must be set to zero Enable/Disable SDI1) 0 enable 1 (reset) disable (reset=80000hex) (reset=0hex) G.729 g729_InterfaceCont rol bit[2] bit[1] bit[0] D0:352 D0:353 D0:354 D0:355 D0:356 D0:357 1) Volume input control: left gain Volume input control: right gain G.729 G.729 All All All All in_L in_R out_LL out_LR out_RL out_RR Volume output control: left left gain (reset=80000hex) Volume output control: left right gain (reset=0hex) Volume output control: right left gain(reset=0hex) Volume control: right right gain (reset=80000hex) Note: The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value). 38 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-10: MP3 block input mode user interface (all addresses in hex notation) Addr. D0:346 Name IOControlMain Description bit[15] MP3 block input select 0: MP3 block input mode OFF 1: MP3 block input mode ON works for input at serial input interface B (bit[9:8] of IOControlMain = 00bin) Reset value is 0x8024 (see Table 3-2). R0:68 MP3BlockConfig bit[17] data end bit Disables resync timeout. Should be set by the controller at the end of an input file (file end, stop, or pause) when the last requested data block has been fully sent. 0: resync timeout enabled 1: resync timeout disable no wait for end of block reserved, set to "0" start data request 0: MP3 decoder does not send data requests (wait loop) 1: MP3 decoder in operational mode, new input data will be requested via pulses at the demand pin. bit[16] bit[15] bit[14:0] input block size specific value, do not modify Reset value is 0x6670. To set the start bit, the controller must write 0xe670. R0:7e D0:34e PulseDelayCounter ResyncTimeout bit[13:0] determines the variable fraction of the demand pulse length. pulseLenVar[ns] = value * 88.58. bit[19:0] timeout after resync: timeout[s] = value * 3.32. The default value is 219-1, which results in a timeout of 1.74 seconds. For an optimized resync behavior, it is recommended to set this value to zero. bit[14:0] configuration of the serial input interface bit[0] MP3 soft mute 0: audio output on 1: audio output soft muted R0:5b D0:350 SerialInConfig SoftMute Micronas June 30, 2004; 6251-505-1DS 39 MAS 35x9F Table 3-11: D0 status memory cells Memory Address D0:FCF D0:FD0 Function AAC bitrate in bit/s MPEG Frame Counter bit[19:0] number of MPEG frames after synchronization Name DATA SHEET AACbitrate MPEGFrameCount The counter will be incremented with every new frame that is decoded. With an invalid MPEG bit stream at its input (e.g. an invalid header is detected), the MAS 35x9F resets the MPEGFrameCount to `0'. D0:FD1 MPEG Header and Status Information bit[15] bit[14:13] reserved, must be set to zero MPEG ID, Bits 12, 11 of the MPEG header 00 MPEG 2.5 01 reserved 10 MPEG 2 11 MPEG 1 not valid in case of AAC decoding (bit[12:11] = 00) Bits 14 and 13 of the MPEG header 00 AAC 01 Layer 3 10 Layer 2 11 Layer 1 CRC Protection 0 bitstream protected by CRC 1 bitstream not protected by CRC Reserved CRC error 0 1 no CRC error CRC error MPEGStatus1 bit[12:11] bit[10] bit[9:2] bit[1] bit[0] Invalid frame 0 no invalid frame 1 invalid frame This location contains bits 15...11 of the original MPEG header and other status bits. It will be set each frame directly after the header has been decoded from the bit stream. 40 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-11: D0 status memory cells, continued Memory Address D0:FD2 Function MPEG Header Information bit[15:12] MPEG Layer 2/3 Bitrate MPEG1, L2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 bit[13:10] free 32 48 56 64 80 96 112 128 160 192 224 256 320 384 forbidden MPEG1, L3 free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden MPEG2+2.5, L2/3 free 8 16 24 32 40 48 56 64 80 96 112 128 144 160 forbidden Name MPEGStatus2 Sampling frequency for MPEG2-AAC in Hz 0000..0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100..1111 reserved 48000 44100 32000 24000 22050 16000 12000 11025 8000 reserved ... Micronas June 30, 2004; 6251-505-1DS 41 MAS 35x9F Table 3-11: D0 status memory cells, continued Memory Address D0:FD2 (continued) DATA SHEET Function MPEG Header Information, continued bit[11:10] Sampling frequencies in Hz MPEG1 00 01 10 11 bit[9] bit[8] bit[7:6] Padding Bit reserved Mode 00 01 10 11 stereo joint_stereo (intensity stereo / m/s stereo) dual channel single channel 44100 48000 32000 reserved MPEG2 22050 24000 16000 reserved MPEG2.5 11025 12000 8000 reserved Name MPEGStatus2 bit[5:4] Mode extension (applies to joint stereo only) intensity stereo off on off on m/s stereo off off on on 00 01 10 11 bit[3] bit[2] bit[1:0] Copyright Protect Bit 0/1 not copyright protected/copyright protected Copy/Original Bit 0/1 bitstream is a copy/bitstream is an original Emphasis, indicates the type of emphasis 00 none 01 50/15 s 10 reserved 11 CCITT J.17 This memory cell contains the 16 LSBs of the MPEG header. It will be set directly after synchronizing to the bit stream. Note that for AAC four bits are needed to define the sampling frequency while for Layer2/Layer3 two bits are sufficient. This leads to an inconsistency in the format of bits 13...10. D0:FD3 MPEG CRC Error Counter The counter will be increased by each CRC error detected in the MPEG bisstream. It will not be reset when losing the synchronization. D0:FD4 Number of Bits in Ancillary Data Number of valid ancillary bits in the current MPEG frame. D0:FD5 ... D0:FF1 Ancillary Data (see Section 3.3.6. on page 43). NumberOfAncillaryBits AncillaryData CRCErrorCount 42 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 3.3.6. Reading of the Memory Cells "Number of Bits in Ancillary Data" and "Ancillary Data" When in Broadcast Mode, reading of the cells "Number of Bits in Ancillary Data" and "Ancillary Data" will lead to unpredictable results. These cells are described in Table 3-11 on page 43. The same applies to the "Number of Bits in Ancillary Data" and "Ancillary Data" of the preliminary data sheet MAS 3587F. 3.3.5. Ancillary Data The memory fields D0:FD5...D0:ff1 contain the ancillary data. It is organized in 28 words of 16 bit each. The last ancillary bit of a frame is placed at bit 0 in D0:FD5. The position of the first ancillary data bit received can be located via the content of NumberOfAncillaryBits because int[(NumberOfAncillaryBits-1)/16] + 1 of memory words are used. Example: First get the content of `NumberOfAncillaryBits' Table 3-12: Content of D0:fd5 after reception of 19 ancillary bits. D0:fd5 Ancillary Data MSB 4th bit 14 5th bit 13 6th bit 12 ... 11 ... 10 ... 9 ... 8 ... 7 ... 6 ... 5 ... 4 ... 3 ... 2 17th bit 1 18th bit LSB last bit Table 3-13: Content of D0:fd6 after reception of 19 ancillary bits. D0:fd6 Ancillary Data MSB x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 first bit 1 2nd bit LSB 3rd bit Micronas June 30, 2004; 6251-505-1DS 43 MAS 35x9F 3.3.7. DSP Volume Control The digital baseband volume matrix is used for controlling the digital gain as shown in Fig. 3-3. This volume control is effective on both, the digital audio output and the data stream to the D/A converters. The values are in 20-bit 2's complement notation. Table 3-14 shows the proposed settings for the 4 volume matrix coefficients for stereo, left and right mono. The gain factors are given in fixed point notation (-1.0x219 = 80000hex). If channels are mixed, care must be taken to prevent clipping at high amplitudes. Therefore, the sum of the absolute values of coefficients for one output channel must be less than 1.0. For normal operating conditions it is recommended to use the main volume control of the audio codec instead (register 00 10hex of the audio codec). DATA SHEET Table 3-14: Settings for the digital volume matrix Memory Name Stereo (default) Mono left Mono right D0:354 LL -1.0 -1.0 0 D0:355 LR 0 -1.0 0 D0:356 RL 0 0 -1.0 D0:357 RR -1.0 0 -1.0 3.3.8. Explanation of the G.729A Data Format The codec is working on a page basis where the encoding and decoding is performed in blocks of 50 G.729 frames, whereas each frame consists of 10 bytes in byte-swapped order (see Fig. 3-4). Therefore most changes to the UserControl register become effective when processing of the current page is finished. The pages are optionally preceeded by 10 byte header frames (see Table 3-15). Table 3-15: Content of page header Byte 1 2 3 4 5 6 7 8 9 10 left audio -1 LL + -1 LR to digital output and D/A from MPEG decoder Value 64 6d 72 31 64 61 74 61 F4 01 (hex) -1 RL right audio -1 RR + Fig. 3-3: Digital volume matrix Switching directly from encoding to decoding mode (or vice versa) is not allowed. Instead, the controller has to send a stop request to the MAS 35x9F (writing 0hex to UserControl) and must keep on sending data in decoding mode or receive data in encoding mode until the current page of 50 frames is finished. After this run-out time, the encoding or decoding can be started again. page frame frame header 1 2 frame 3 ... frame frame page frame 49 49 header 51 frame 52 ... frame frame page frame frame 99 100 header 101 102 ... ... 10 ms 10 ms ... 64 6D 72 31 64 61 74 61 F4 01 byte byte byte byte byte byte byte byte byte byte 2 1 4 3 6 5 8 7 10 9 Fig. 3-4: Schematic timing of the data transmission with preceeding header 44 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 3.4. Audio Codec Access Protocol The MAS 35x9F has 16-bit wide registers for the control of the audio codec. These registers are accessed via the I2C subaddresses codec_write (6Chex) and codec_read (6Dhex). 3.4.1. Write Codec Register S DW W A codec_write A r3,r2 d3,d2 A A r1,r0 d1,d0 A A P The controller writes the 16-bit value (d = d3,d2,d1,d0) into the MAS 35x9F codec register (r = r3,r2,r1,r0). A list of registers is given in Table 3-16. Example: Writing the value 1234hex into the codec register with the number 00 1Bhex: 1) send command S DW W A codec_write A r3,r2 A r1,r0 A P 2) get register value S DW W A codec_read A S DR A W d1,d0 A N P d3,d2 Reading the codec registers also needs a set-up for the register address and an additional start condition during the actual read cycle. A list of status registers is given in Table 3-17. Micronas June 30, 2004; 6251-505-1DS 45 MAS 35x9F 3.4.3. Codec Registers Table 3-16: Codec control registers on I2C subaddress 6Chex Register Address (hex) Function Name DATA SHEET CONVERTER CONFIGURATION 00 00 Audio Codec Configuration 0 dB is related to the D/A full-scale output voltage Please refer to (see Section 4.6.3. on page 81). bit[15:12] bit[11:8] A/D converter left amplifier gain = n*1.5-3 [dB] A/D converter right amplifier gain = n*1.5-3 [dB] 1111 +19.5 dB 1110 +18.0 dB ... ... 0011 +1.5 dB 0010 0.0 dB 0001 -1.5 dB 0000 - 3.0 dB Microphone amplifier gain = n*1.5+21 [dB] 1111 +43.5 dB 1110 +42.0 dB ... ... 0001 +22.5 dB 0000 +21.0 dB Input selection for left A/D converter channel 0 line-in 1 microphone Enable left A/D converter1) Enable right A/D converter1) Enable D/A converter1) CONV_CONF bit[7:4] bit[3] bit[2] bit[1] bit[0] 1) The generation of the internal DC reference voltage for the D/A converter is also controlled with this bit. In order to avoid click noise, the reference voltage at pin AGNDC should have reached a near ground potential before repowering the D/A converter after a short down phase. Alternatively, at least one of the A/D converters (bits[2] or [1]) should remain set during short power-down phases of the D/A. Then the DC reference voltage generation for the D/A converter will not be interrupted. 46 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-16: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) Function Name INPUT MODE SELECT 00 08 Input Mode Setting bit[15] Mono switch 0 stereo input mode 1 left channel is copied into the right channel Reserved, must be set to 0 Deemphasis select 0 deemphasis off 1 deemphasis 50 s 2 deemphasis 75 s ADC_IN_MODE bit[14:2] bit[1:0] OUTPUT MODE SELECT D/A Converter Source Mixer 00 06 00 07 MIX ADC scale MIX DSP scale bit[15:8] Linear scaling factor (hex) 0 off 20 50 % (-6 dB gain) 40 100 % (0 dB gain) 7f 200 % (+6 dB gain) DAC_IN_ADC DAC_IN_DSP In the sum of both mixing inputs exceeds 100 %, clipping may occur in the successive audio processing. 00 0E D/A Converter Output Mode bit[15] Mono switch 0 stereo through 1 mono matrix applied Invert right channel 0 through 1 right channel is inverted Reserved, must be set to 0 DAC_OUT_MODE bit[14] bit[1:0] In order to achieve more output power a single loudspeaker can be connected as a bridge between pins OUTL and OUTR. In this mode bit[15] and bit[14] must be set. Micronas June 30, 2004; 6251-505-1DS 47 MAS 35x9F Table 3-16: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) Function Name DATA SHEET BASSBAND FEATURES 00 14 Bass bit[15:8] Bass range 60hex 58hex ... 08hex 00hex F8hex ... A8hex A0hex +12 dB +11 dB +1 dB 0 dB -1 dB -11 dB -12 dB BASS Higher resolution is possible, one LSB step results in a gain step of about 1/8 dB. With positive bass settings clipping of the output signal may occur. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. The settings require: max (bass, treble) + loudness + volume 0 dB bit[7:0] 00 15 Treble bit[15:8] Treble range 60hex +12 dB 58hex +11 dB ... 08hex +1 dB 00hex 0 dB F8hex -1 dB ... A8hex -11 dB A0hex -12 dB Not used, must be set to 0 TREBLE Higher resolution is possible, one LSB step results in a gain step of about 1/8 dB. With positive treble settings, clipping of the output signal may occur. Therefore, it is not recommended to set treble to a value that, in conjunction with loudness and volume, would result in an overall positive gain. The settings require: max (bass, treble) + loudness + volume 0 dB bit[7:0] Not used, must be set to 0 48 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-16: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) 00 1E Function Name Loudness bit[15:8] Loudness Gain 44hex +17 dB 40hex +16 dB ... 04hex +1 dB 00hex 0 dB Loudness Mode 00hex normal (constant volume at 1 kHz) 04hex Super Bass (constant volume at 2 kHz) LDNESS bit[7:0] Higher resolution of Loudness Gain is possible: An LSB step results in a gain step of about 1/4 dB. Loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the 1-kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. The settings should be: max (bass, treble) + loudness + volume 0 dB The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. Micronas June 30, 2004; 6251-505-1DS 49 MAS 35x9F Table 3-16: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) Function Name DATA SHEET Micronas Bass (MB) 00 22 MB Effect Strength bit[15:8] 00hex 7Fhex MB off (default) maximum MB MB_STR The MB effect strength can be adjusted in 1dB steps. A value of 40hex will yield a medium MB effect. 00 23 MB Harmonics bit[15:8] 00hex 64hex 7Fhex no harmonics are added (default) 50% fundamentals + 50% harmonics 100% harmonics MB_HAR The MB exploits the psychoacoustic phenomenon of the `missing fundamental by creating harmonics of the frequencies below the center frequency of the bandpass filter (MB_FC). This enables a loudspeaker to display frequencies that are below its cutoff frequency. The Variable MB_HAR describes the ratio of the harmonics towards the original signal. 00 24 MB Center Frequency bit[15:8] 2 3 ... 30 20 Hz 30 Hz 300 Hz MB_FC The MB Center Frequency defines the center frequency of the MB bandpass filter (see Fig. 3-5 on page 52). The center frequency should approximately match the cutoff frequency of the loudspeakers. For high end loudspeakers, this frequency is around 50 Hz, for low end speakers around 90 Hz 00 21 MB Shape bit[15:8] 5...30 corner frequency in 10-Hz steps (range: 50...300 Hz) MB_SHAPE With a second lowpass filter the steepness of the falling edge of the MB bandpass can be increased (see Fig. 3-5 on page 52). Choosing the corner frequency of this filter close to the center frequency of the bandpass filter (MB_FC) results in a narrow MB frequency range. The smaller this range, the harder the bass sounds. The recommended value is around 1.5 x MB_FC MB Switch bit[7:2] bit[1] 0 1 bit [0] reserved, must be set to zero MB switch MB off MB on reserved,must be set to zero MB_SWITCH 50 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 3-16: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) VOLUME 00 12 Automatic Volume Correction (AVC) Loudspeaker Channel bit[15:12] 0hex 8hex bit[11:8] 8hex 4hex 2hex 1hex AVC off (and reset internal variables) AVC on 8 s decay time 4 s decay time 2 s decay time 20 ms decay time (intended for quick adaptation to the average volume level after track or source change) AVC Function Name Note: To reset the internal variables, the AVC should be switched off and then on again during any track or source change. For standard applications, the recommended decay time is 4 s. 00 11 Balance bit[15:8] Balance range 7Fhex left -127 dB, right 0 dB 7Ehex left -126 dB, right 0 dB ... 01hex left -1 dB, right 0 dB 00hex left 0 dB, right 0 dB FFhex left 0 dB, right -1 dB ... 81hex left 0 dB, right -127 dB 80hex left 0 dB, right -128 dB BALANCE Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. 00 10 Volume Control bit[15:8] Volume table with 1 dB step size 7Fhex +12 dB (maximum volume) 7Ehex +11 dB ... 74hex +1 dB 73hex 0 dB 72hex -1 dB ... 02hex -113 dB 01hex -114 dB 00hex mute (reset) Not used, must be set to 0 VOLUME bit[7:0] This main volume control is applied to the analog outputs only. It is split between a digital and an analog function. In order to avoid noise due to large changes of the setting, the actual setting is internally low-pass filtered. With large scale input signals, positive volume settings may lead to signal clipping. Micronas June 30, 2004; 6251-505-1DS 51 MAS 35x9F Table 3-17: Codec status registers on I2C subaddress 6Dhex Register Address (hex) Function Name DATA SHEET INPUT QUASI-PEAK 00 0A A/D Converter Quasi-Peak Detector Readout Left bit[14:0] 0000 2000 4000 7FFF 00 0B positive 15-bit value, linear scale 0% 25% (-12 dBFS) 50% (-6 dBFS) 100% (0 dBFS) QPEAK_R QPEAK_L A/D Converter Quasi-Peak Detector Readout Right bit[14:0] 0000 2000 4000 7FFF positive 15-bit value, linear scale 0% 25% (-12 dBFS) 50% (-6 dBFS) 100% (0 dBFS) OUTPUT QUASI-PEAK 00 0C Audio Processing Input Quasi-Peak Detector Readout Left bit[14:0] 00 0D positive 15-bit value, linear scale DQPEAK_R DQPEAK_L Audio Processing Input Quasi-Peak Detector Readout Right bit[14:0] positive 15-bit value, linear scale 3.4.4. Basic MB Configuration With the parameters described in Table 3-16, the Micronas Bass system (MB) can be customized to create different bass effects, as well as to fit the MB to various loudspeaker characteristics. The easiest way to find a good set of parameter is by selecting one of the settings below, listening to music with strong bass content and adjusting the MB parameters: - MB_STR: Increase/decrease the strength of the MB effect - MB_HAR: Increase/decrease the content of low frequency harmonics - MB_FC: Shift the MB effect to lower/higher frequencies - MB_SHAPE: Widen/narrow MB frequency range Table 3-18: Suggested MB settings Function MB off Low end headphones, medium effect MB_STR (22hex) xxxxhex 5000hex (which results in a softer/harder bass sound), turn on/off the MB Amplitude (db) Frequency MB_FC MB_SHAPE Fig. 3-5: Micronas Bass (MB): Bass boost in relation to input signal level MB_HAR (23hex) xxxxhex 3000hex MB_FC (24hex) xxxxhex 0600hex MB_SHAPE (21hex) xx00hex 0902hex 52 June 30, 2004; 6251-505-1DS Micronas Signal Level DATA SHEET MAS 35x9F Micronas June 30, 2004; 6251-505-1DS 53 MAS 35x9F 4. Specifications 4.1. Outline Dimensions DATA SHEET Fig. 4-1: PLQFP64-1: Plastic Low Quad Flat Package, 64 leads, 10 x 10 x 1.4 mm3 Ordering code: FH Weight approximately 0.66 g 54 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Fig. 4-2: PMQFP64-2: Plastic Metric Quad Flat Package, 64 leads, 10 x 10 x 2 mm3 Ordering code: QI Weight approximately 0.5 g Micronas June 30, 2004; 6251-505-1DS 55 MAS 35x9F DATA SHEET Fig. 4-3: PQFN64-1: Plastic Quad Flat Non-leaded package, 64 pins, 9 x 9 x 0.85 mm3, 0.5 mm pitch Ordering code: XK Weight approximately 0.23 g 56 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant S.T.B. = shorted to BAGNDI if not used DVSS = if not used, connect to DVSS OBL = obligatory; connect as described in circuit diagram AHVSS = connect to AHVSS Pin No. PLQFP 64-1 PMQFP 64-2 PQFN 64-1 Pin Name Type Connection (If not used) Short Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AGNDC MICIN MICBI INL INR TE XTI XTO POR VSS XVSS VDD XVDD I2CVDD DVS VSENS1 IN IN IN IN IN IN OUT IN SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY IN IN/OUT OBL LV LV LV LV OBL OBL LV OBL OBL OBL OBL OBL OBL OBL VDD Analog reference voltage Input for internal microphone amplifier Bias for internal microphone Left A/D input Right A/D input Test enable Crystal oscillator (ext. clock) input Crystal oscillator output Power on reset, active low DSP supply ground Digital output supply ground DSP supply Digital output supply I2C supply I2C device address selector Sense input and power output of DC/DC 1 converter DC/DC 1 switch output DC/DC 1 switch ground DC/DC 2 switch ground DC/DC 2 switch output Sense input and power output of DC/DC 2 converter DC/DC enable (both converters) 17 18 19 20 21 17 18 19 20 21 17 18 19 20 21 DCSO1 DCSG1 DCSG2 DCSO2 VSENS2 SUPPLY SUPPLY SUPPLY SUPPLY IN/OUT LV VSS VSS LV VDD 22 22 22 DCEN IN VSS Micronas June 30, 2004; 6251-505-1DS 57 MAS 35x9F DATA SHEET Pin No. PLQFP 64-1 PMQFP 64-2 PQFN 64-1 Pin Name Type Connection (If not used) Short Description 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 CLKO I2CC I2CD SYNC VBAT PUP EOD PRTR PRTW PR PCS PI19 PI18 PI17 PI16 PI15 PI14 PI13 PI12 SOD SOI SOC SID SII SIC SPDO SIBD OUT IN/OUT IN/OUT OUT IN OUT OUT OUT OUT IN IN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT OUT IN LV OBL OBL LV LV LV LV LV LV VDD VSS LV LV LV LV LV LV LV LV LV LV LV OBL OBL OBL LV VSS Clock output I2C clock I2C data Sync output Battery voltage monitor input DC Converters Power-Up Signal PIO end of DMA, active low PIO ready to read, active low PIO ready to write, active low PIO DMA request, active high PIO chip select, active low PIO data bit[7] (MSB) PIO data bit[6] PIO data bit[5] PIO data bit[4] PIO data bit[3] PIO data bit[2] PIO data bit[1] PIO data bit[0] (LSB) Serial output data Serial output word identification Serial output clock Serial input data, interface A Serial input word identification, interface A Serial input clock, interface A S/PDIF output interface Serial input data, interface B 58 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Pin No. PLQFP 64-1 PMQFP 64-2 PQFN 64-1 Pin Name Type Connection (If not used) Short Description 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SIBC SIBI SPDI2 SPDI1 SPDIR FILTL AVDD0 OUTL OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 IN IN IN IN IN IN SUPPLY OUT OUT SUPPLY IN SUPPLY VSS VSS LV LV LV OBL OBL LV LV OBL OBL OBL OBL Serial input clock, interface B Serial input word identification, interface B Active differential S/PDIF input 2 Active differential S/PDIF input 1 Reference differential S/ PDIF input 1 and 2 Feedback input for left amplifier Analog supply for output amplifiers Left analog output Right analog output Analog ground for output amplifiers Feedback for right output amplifier Analog ground Analog reference ground Internal power supply Analog Supply SUPPLY SUPPLY OBL OBL Micronas June 30, 2004; 6251-505-1DS 59 MAS 35x9F 4.3. Pin Descriptions 4.3.1. Power Supply Pins The use of all power supply pins is mandatory to achieve correct function of the MAS 35x9F. VDD, VSS Digital supply pins. XVDD, XVSS Supply for digital output pins. SUPPLY SUPPLY DATA SHEET VSENS1/VSENS2 IN Sense input and power output of DC/DC converters. If the respective DC/DC converter is not used, this pin should be connected to a supply to enable proper function of the PUP-signals. DCEN IN Enable signal for both DC/DC converters. If none of the DC/DC converters is used, this pin must be connected to VSS. PUP OUT Power-up. This signal is set when the required voltages are available at both DC/DC converter output pins VSENS1 and VSENS2. The signal is cleared when both voltages have dropped below the reset level in the DCCF Register. VBAT Analog input for battery voltage supervision. 4.3.4. Oscillator Pins and Clocking XTI IN XTO OUT The XTI pin is connected to the input of the internal crystal oscillator, the XTO pin to its output. Each pin should be directly connected to the crystal and to a ground-connected capacitor (see application diagram, Fig. 5-1 on page 89). CLKO The CLKO can drive an output clock line. 4.3.5. Control Lines I2CC SCL I2CD SDA Standard I2C control lines. IN/OUT IN/OUT OUT IN I2CVDD SUPPLY Supply for I2C interface circuitry. This net uses VSS or XVSS as the ground return line. PVDD SUPPLY Auxiliary pin for analog circuitry. This pin has to be connected via a 3 nF capacitor to AVDD1. Extra care should be taken to achieve a low-inductance PCB line. AVDD0/AVSS0 Supply for analog output amplifier. SUPPLY AVDD1/AVSS1 SUPPLY Supply for internal analog circuits (A/D, D/A converters, clock, PLL, S/PDIF input). AVDD0/AVSS0 and AVDD1/AVSS1 should receive the same supply voltages. 4.3.2. Analog Reference Pins AGNDC Internal analog reference voltage. This pin serves as the internal ground connection for the analog circuitry. VREF Analog reference ground. All analog inputs and outputs should drive their return currents using separate traces to a ground starpoint close to this pin. Connect to AVSS1. This reference pin should be as noise-free as possible. 4.3.3. DC/DC Converters and Battery Voltage Supervision DCSG1/DCSG2 SUPPLY DC/DC converters switch ground. Connect using separate wide trace to negative pole of battery cell. Connect also to AVSS0/1 and VSS/XVSS, VREF. DCSO1/DCSO2 SUPPLY DC/DC converter switch connection. If the respective DC/DC converter is not used, this pin must be left vacant. DVS IN I2C device address selector. Connect this pin either to VDD (I2C device address: 3E/3Fhex) or VSS (I2C device address: 3C/3Dhex) to select a proper I2C device address (see also Table 3-2 on page 23). 4.3.6. Parallel Interface Lines PI12..PI19 IN/OUT The PIO input pins PI12..PI19 are used as 8-bit I/O interface to a microcontroller in order to transfer compressed and uncompressed data. PI12 is the LSB, PI19 the MSB. 60 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F specification are used in conjunction with download software only. A switch at D0:ff6 selects one of these pins at a time. The SPDIR pin is a common reference for both input lines (see Fig. 5-1 on page 89). 4.3.11. S/PDIF Output Interface SPDO OUT The SPDO pin provides an digital output with standard CMOS level that is compliant to the IEC 958 consumer specification. 4.3.12. Analog Input Interfaces In the standard MPEG-decoding DSP firmware the analog inputs are not used. However, they can be selected as a source for the D/A converters (set MIX ADC scale of the D/A Converter Source Mixer, Register 00 06hex in Table 3-16). MICIN IN MICBI IN The MICIN input may be directly used as electret microphone input, which should be connected as described in application information (see Fig. 5-1 on page 89). The MICBI signal provides the supply voltage for these microphones. INL IN INR IN INL and INR are analog line-in input lines. They are connected to the embedded stereo A/D converter of the MAS 35x9F. The sources should be AC-coupled. The reference ground for these analog input pins is the VREF pin. 4.3.13. Analog Output Interfaces OUTL OUT OUTR OUT OUTL and OUTR are left and right analog outputs, that may be directly connected to the headphones as described in the application information (see Fig. 5-1 on page 89). FILTL IN FILTR IN Connection to input terminal of output amplifier.Can be used to connect a capacitance from OUTL respectively OUTR to FILTL respectively FILTR in parallel to feedback resistor and thus implement a low pass filter to reduce the out-of-band noise of the DAC. 4.3.6.1. PIO Handshake Lines PCS IN The PIO chip select PCS must be set to `0' to activate the PIO in operation mode. PR IN Pin PR must be set to `1' to validate data output from MAS 35x9F PIO pins. PRTR OUT Ready to read. This signal indicates that the MAS 35x9F is able to receive data in PIO input mode. PRTW OUT Ready to write. This pin indicates that MAS 35x9F has data available for PIO output mode. EOD OUT EOD indicates the end of an DMA cycle in the IC's PIO input mode. In 'serial' input mode it is used as Demand signal, that indicates that new input data are required. 4.3.7. Serial Input Interface (SDI) SID DATA IN/OUT SII WORD STROBE IN/OUT SIC CLOCK IN/OUT I2S compatible serial interface A for digital audio data. In the standard firmware this interface is not used. Note: Please refer to Bit [0] of Table 3-5 4.3.8. Serial Input Interface B (SDIB) SIBD DATA IN SIBI WORD STROBE IN SIBC CLOCK IN The serial interface B is primarily used as bitstream input interface. The SIBI line must be connected to VSS in the standard application. 4.3.9. Serial Output Interface (SDO) SOD DATA OUT SOI WORD STROBE OUT SOC CLOCK IN/OUT Data, Frame Indication, and Clock line of the serial output interface. The SOI is reconfigurable and can be adapted to several I2S compliant modes. 4.3.10. S/PDIF Input Interface SPDI1 IN SPDI2 IN SPDIR IN SPDIF1 and SPDIF2 are alternative input pins for S/PDIF sources according to the IEC 958 consumer Micronas June 30, 2004; 6251-505-1DS 61 MAS 35x9F 4.3.14. Miscellaneous SYNC OUT The SYNC signal indicates the detection of a frame start in the input data of MAS 35x9F. Usually this signal generates an interrupt in the controller. POR IN The Power-On Reset pin is used to reset the whole MAS 35x9F. The POR is an active-low signal (see Fig. 5-1 on page 89). TE IN The TE pin is for production test only and must be connected with VSS in all applications. DATA SHEET 4.4. Pin Configuration PI12 SOD SOI SOC SID SII SIC SPDO PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SIBD SIBC SIBI SPDI2 SPDI1 SPDIR FILTL AVDD0 OUTL OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 AGNDC MICIN MICBI INL INR TE XTI XTO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSENS1 DVS I2CVDD XVDD VDD XVSS VSS POR 32 31 30 29 28 27 26 PR PRTW PRTR EOD PUP VBAT SYNC I2CD I2CC CLKO DCEN VSENS2 DCSO2 DCSG2 DCSG1 DCSO1 MAS 35x9F 25 24 23 22 21 20 19 18 17 Fig. 4-4: PLQFP64-1/PMQFP64-2 and PQFN64-1 package 62 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.5. Internal Pin Circuits VDD TTLIN N Fig. 4-5: Input pins PCS, PR VSS Fig. 4-10: Input/output pins I2CC, I2CD VSENS Fig. 4-6: Input pin TE, DVS, POR P DCSO N DCSG Fig. 4-11: Input/output pins DCSO1/2, DCSG1/2, VSENS1/2 Fig. 4-7: Input pin DCEN XVDD XVDD P N N XVSS Fig. 4-8: Input/output pins SOC, SOI, SOD, PI12...PI19, SPDO XVSS Fig. 4-12: Output pins PRTW, EOD, PRTR, CLKO, SYNC, PUP P AVDD XVDD P XTI P N N Enable N AVSS Fig. 4-13: Clock oscillator XTI, XTO P P XTO N XVSS Fig. 4-9: Input pins SIC, SII, SID Micronas June 30, 2004; 6251-505-1DS 63 MAS 35x9F DATA SHEET MICIN INL INR XVDD - + A D SPDI1, SPDI2 SPDIR - + XVDD Bias AGNDC Fig. 4-14: Analog input pins MICIN, INL, INR Fig. 4-18: S/PDIF inputs AGNDC + - MICBI VBAT VREF Fig. 4-15: Microphone bias pin (MICBI) VSS = VSS FILTL(R) + - programmable Fig. 4-19: Battery voltage monitor VBAT 4.5.1.Reset Pin Configuration for MAS 3529F and MAS 3539F OUTL(R) The Power-On Reset pin POR is used to reset the entire MAS 35x9F. The POR is an active-low signal. Note: If a pull-up resistor is used for building a delay time here (see Fig. 5-1 on page 89), referred to the VDD pins, the maximum allowed value for this resistor is 3.3 kOhm! D A I - + AGNDC Fig. 4-16: Analog outputs OUTL(R) and connections for filter capacitors FILTL(R) + - AGNDC 1.25 V VREF Fig. 4-17: Analog ground generation with pin to connect external capacitor 64 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip 4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (VSUP1, VSUP2, VSUP3 = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in Section 2.6. of this document. Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min. TA1) Ambient Temperature - operating conditions - extended temperature range1) Case Temperature PLQFP64-1 PMQFP64-2 PQFN64-1 Storage Temperature Maximum Power Dissipation PLQFP64-1 PMQFP64-2 PQFN64-1 Supply Voltage 1 VDD, XVDD, AVDD0/1, I2CVDD VDD, XVDD, I2CVDD, AVDD0/14) -0.3 -10 -40 -10 -10 -10 -40 Limit Values Max. 2) Unit C 85 85 C 115 120 120 125 3) TC TS PMAX C W 0.67 0.63 0.87 6 V VSUP1 1) Data sheet parameters are valid for "operating conditions" only. The functionality of the device in the "extended temperature range" was checked by electrical characterization on sample base. A power-optimized board layout is recommended. The Case Temperature mentioned in the "Absolute Maximum Ratings" must not be exceeded at worst case conditions of the application. Package limits AVDD0 and AVDD1 have to be connected together! 2) 3) 4) Both Micronas June 30, 2004; 6251-505-1DS 65 MAS 35x9F Table 4-1: Absolute Maximum Ratings, continued Symbol Parameter Pin Name Min. VSUP2 Supply Voltage 2 VDD, XVDD, I2CVDD, AVDD0/11) VDD, XVDD, I2CVDD, AVDD0/11) I2CC, I2CD all digital inputs all digital inputs all analog inputs all analog inputs OUTL/R -0.3 Limit Values Max. 6 DATA SHEET Unit V VSUP3 Supply Voltage 3 -0.3 6 V VII2C VID IID VIA IIA IOaudio IOdig IOdcdc1 IOdcdc2 1) Both 2) 3) Input Voltage, I2C pins Input Voltage Input Current Input Voltage Input Current Output Current, audio output2) Output Current, all digital outputs3) Output Current DCDC converter 1 Output Current DCDC converter 2 -0.3 -0.3 -20 -0.3 -5 -0.2 -50 6 VSUP + 0.3 +20 VSUP + 0.3 +5 0.2 +50 1.5 1.5 V V mA V mA A mA A A DCSO1 DCSO2 AVDD0 and AVDD1 have to be connected together! These pins are not short-circuit-proof! Total chip power dissipation must not exceed maximum rating. 66 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.6.1.1. Recommended Operating Conditions Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (VSUP1, VSUP2, VSUP3 = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in section Section 2.11.2. of this document. Symbol Parameter Pin Name Min. TA Ambient Operating Temperature PLQFP64-1 PMQFP64-2 PQFN64-1 Case Operating Temperature PLQFP64-1 PMQFP64-2 PQFN64-1 MP3 Decoder (SC4 En-/Decoder) AAC Decoder/G729 Encoder G.729 Decoder DAC-Headphone Playback Digital supply voltage (MP3 decoder, G729 Decoder) Digital supply voltage (G.729 A encoder/MP3 Decoder and SD Decryption/AAC Decoder) I2C bus supply voltage PIN supply voltage PIN supply voltage in relation to digital supply voltage VSUPA Analog audio supply voltage Analog audio supply voltage in relation to the digital supply voltage VSUPDX 1) Limit Values Typ. 25 25 25 95 100 95 80 122 50 7 2.2 2.5 2.5 2.7 3.6 3.6 Max. 1) Unit C 0 0 0 15 20 15 VDD VDD VDD AVDD0/1 VDD 85 85 85 C 100 105 100 mW mW mW mW V TC PMAX_D1 PMAX_D2 PMAX_D3 PMAX_A VSUPD11) VSUPD2 VSUPI2C VSUPx I2CVDD XVDD VSUPDn2) at VDD 2.2 0.62 * VSUPDn2) 2.5 3.9 3.6 1.6 * VSUPDn2) 2.7 3.6 1.6 * VSUPDn2) V V V V V V AVDD0/1 2.2 0.62 * VSUPDn2) Voltage differences within supply domains A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the "Recommended Operating Conditions" must not be exceeded at worst case conditions of the application. For turn-on voltage of DSP and codec, please refer to Section 2.11.2.1. n = 1 or 2 2) Micronas June 30, 2004; 6251-505-1DS 67 MAS 35x9F DATA SHEET Table 4-2: Reference Frequency Generation and Crystal Recommendation Symbol Parameter Pin Name Min. Typ. Max. Unit External Clock Input Recommendations fCLK VCLKI Clock frequency Clockamplitude of external clock fed into XTI at VAVDD = 2.2 V Clockamplitude of external clock fed into XTI at VAVDD = 2.7 V Clockamplitude of external clock fed into XTI at VAVDD = 3.3 V Clockamplitude of external clock fed into XTO at VAVDD = 2.2 V Clockamplitude of external clock fed into XTO at VAVDD = 2.7 V Clockamplitude of external clock fed into XTO at VAVDD = 3.3 V Duty cycle Crystal Recommendations fP f/fS f/fS REQ C0 Load resonance frequency at CI = 20 pF Accuracy of frequency adjustment Frequency variation vs. temperature Equivalent series resistance Shunt (parallel) capacitance XTI, XTO -50 -50 12 3 18.432 50 50 30 5 MHz ppm ppm pF XTI, XTO XTO XTI, XTO XTI 13.00 0.7 0.55 0.45 1.25 0.75 0.55 45 50 18.432 20.00 1.05 1.5 1.75 2.2 2.7 3.3 55 % MHz VPP 68 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 4-3: Input clock frequency Symbol Parameter Pin Name Min. fCLK1) G.729 Decoder G.729 Encoder MPEG Decoder (SC4 EnDecoder) 1) Limit Values Typ. Max. Unit XTI, XTO 16.4 13.7 11.0 MHz MHz MHz Minimum FCLK for SD-card decryption is defined in a supplement. Table 4-4: Input levels Symbol Parameter Pin Name Min. VIL VIH VIL VIH VILD VIHD Input low voltage Input high voltage Input low voltage Input high voltage Input low voltage Input high voltage PI, SI(B)I, SI(B)C, SI(B)D, PR, PCS, TE, DVS POR, DCEN 0.9 0.3 VSUPx -0.5 I2CC, I2CD 1.4 0.2 Limit Values Typ. Max. 0.3 V V V V V V Unit Micronas June 30, 2004; 6251-505-1DS 69 MAS 35x9F Table 4-5: Analog input and output recommendations Symbol Parameter Pin Name Min. Analog Reference CAGNDC1 CAGNDC2 CPVDD Analog filter capacitor Ceramic capacitor in parallel Capacitor for analog circuitry PVDD 3 AGNDC 1.0 3.3 10 Limit Values Typ. Max. DATA SHEET Unit F nF nF Analog Audio Inputs CinAD CinMI CLMICBI DC-decoupling capacitor at A/Dconverter inputs DC-decoupling capacitor at microphone-input Minimum-Capacitance at microphone bias INL/R MICIN MICBI 3.3 390 390 nF nF nF Analog Audio Filter Outputs CFILT Filter capacitor for headphone amplifier high-Q type, NP0 or C0G material FILTL/R OUTL/R -20 % 470 +20 % pF Analog Audio Output ZAOL_HP Analog output load with stereo headphones OUTL/R 16 100 DC/DC-Converter External Circuitry (please refer to application example) C1 VTH L VSENS blocking (<100 m ESR) Schottky diode threshold voltage Ferrite core coil inductance VSENS1/2 DCSO1/2 VSENS1/2 DCSO1/2 0.39 22 330 F V H pF S/PDIF Interface Analog Input CSPI S/PDIF coupling capacitor SPDI1/2 SPDIR 100 nF 70 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.6.2. Digital Characteristics at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C in P(L/M)QFP package Symbol Parameter Pin Name Min. Limit Values Typ. Max. Unit Test Conditions Digital Supply Voltage ISUPD ISUPD ISUPD Current consumption Current consumption Current consumption VDD, XVDD, I2CVDD 36 23 15 mA mA mA 2.2 V, sampling frequency 32 kHz 2.2 V, sampling frequency 24 kHz 2.2 V, sampling frequency 12 kHz DSP off, Codec off, DC/DC off, AD and DAC off, no I2C access ISTANDBY Total current at stand-by 10 A Digital Outputs and Inputs ODigL ODigH Output low voltage Output low voltage PI, SOI, SOC, SOD, EOD, PRTR, PRTW, CLKO, SYNC, PUP, SPDO ALL DIGITAL INPUTS 0.3 VSUPx -0.3 V V Iload = 2 mA Iload = -2 mA ZDigI IDLeak Input impedance Digital input leakage current 7 -1 1 pF A 0 V < Vpin < VSUPD Micronas June 30, 2004; 6251-505-1DS 71 MAS 35x9F 4.6.2.1. I2C Characteristics at T = 25C, VSUPI2C = 2.2...3.6 V in P(L/M)QFP package Symbol Parameter Pin Name Min. I2C Input Specifications fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2COL II2COH tI2COL1 tI2COL2 VI2CIL VI2CIH tW Upper limit I2C bus frequency operation I2C START condition setup time I2C STOP condition setup time I2C clock low pulse time I2C clock high pulse time I2C data setup time before rising edge of clock I2C data hold time after falling edge of clock I2C output low voltage I2C output high leakage current I2C data output hold time after falling edge of clock I2C data output setup time before rising edge of clock I2C input low voltage I2C input high voltage Wait time I2CC I2CC, I2CD I2CC, I2CD I2CC I2CC I2CC I2CC I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD 0.6 0 0.5 4 20 250 0.3 400 300 300 1250 1250 80 80 0.4 1 kHz ns ns ns ns ns ns V A ns ns VSUPI2C VSUPI2C ms Limit Values Typ. Max. Unit DATA SHEET Test Conditions Iload = 3 mA fI2C = 400 kHz 1/fI2C tI2C4 H L tI2C3 I2CC tI2C1 tI2C5 tI2C6 tI2C2 H L I2CD as input tI2COL2 tIC2OL1 H L I2CD as output Fig. 4-20: I2C timing diagram 72 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.6.2.2. Serial (I2S) Input Interface Characteristics (SDI, SDIB) at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCRYSTAL = 18.432 MHz, Typ. values for TA = 25 C in P(L/M)QFP package Symbol Parameter Pin Name Min. tSICLK I2S clock input clock period SI(B)C Limit Values Typ. 325 Max. ns fS = 48 kHz Stereo, 32 bits per sample (for demand mode see Table 4-6) Unit Test Conditions tSIDS I2S data setup time before rising edge of clock (for continuous data stream: falling edge) I2S data hold time I2S ident setup time before rising edge of clock (for continuous data stream: falling edge) I2S ident hold time Burst wait time SI(B)C, SI(B)D 50 ns tSIDH tSIIS SI(B)D SI(B)C, SI(B)I 50 50 ns ns tSIIH tbw SI(B)I SI(B)C, SI(B)D 50 480 ns Table 4-6: Maximum allowed sample clock frequency in Demand Mode fSample (kHz) 48, 32 44.1 24, 16 22.05 12, 8 11.025 fC (MHz) 6.144 5.6448 3.072 2.8224 1.536 1.4112 min. tSICLK (ns) 162 177 325 354 651 708 TSICLK H SI(B)C L H SI(B)I L SI(B)D H L TSIDS TSIDH Fig. 4-21: Continuous data stream at serial input A or B. In this mode, the word strobe SI(B)I is not used and the data are read at the falling edge of the clock (bit[2] in D0:346 is set). Micronas June 30, 2004; 6251-505-1DS 73 MAS 35x9F Table 4-7: Allowed transmission delays of external data source MPEG1/2 Layer 2/3 Symbol Parameter Pin Name Min. tSTART48-320 tSTART48-64 tSTART24-320 tSTART24-32 tSTART12-64 tSTART12-16 tSTART8-64 tSTART8-8 tSTOP Allowed delay time before stop of serial data transmission after deassertion of signal at EOD Allowed delay time before start of serial data transmission after assertion of signal at EOD EOD Limit Values Typ. Max. 3.1 5.7 4.2 9.2 23.1 25.6 34.8 38.4 ms ms ms ms ms ms ms ms ms Unit DATA SHEET Test Conditions 48 kHz/s, 320 kbit/s 48 kHz/s, 64 kbit/s 24 kHz/s, 320 kbit/s 24 kHz/s, 32 kbit/s 12 kHz/s, 64 kbit/s 12 kHz/s, 16 kbit/s 8 kHz/s, 64 kbit/s 8 kHz/s, 8 kbit/s Clock rate of input data 1 Mbit/s EOD 1.3 TSICLK SI(B)C H L SI(B)I H L TSIIS SI(B)D H L TSIIH TSIDS Fig. 4-22: Serial input of I2S signal 4.6.2.3. Serial Output Interface Characteristics (SDO) TSIDH at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCRYSTAL = 18.432 MHz, Typ. values for TA = 25 C in P(L/M)QFP package Symbol Parameter Pin Name Min. tSOCLK tSOISS tSOODC I2S clock output frequency I2S word strobe delay time after falling edge of clock I2S data delay time after falling edge of clock SOC SOC, SOI SOC, SOD 0 0 Limit Values Typ. 325 Max. ns ns ns fS = 48 kHz Stereo 32 bits per sample Unit Test Conditions 74 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F TSOCLK H SOC L SOI H L TSOISS SOD H L TSOISS TSOODC Fig. 4-23: Serial output interface timing Vh SOC Vl Vh SOD V l Vh Vl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 76543210 SOI left 16-bit audio sample right 16-bit audio sample Fig. 4-24: Sample timing of the SDO interface in 16 bit/sample mode D0:346 settings are bit[14] = 0 (SOC not inverted) bit[11] = 1 (SOI delay) bit[5] = 0 (word strobe not inverted) bit[4] = 1 (16 bits/sample) SOC Vh Vl ... ... Vh SOD Vl 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 Vh SOI Vl left 32-bit audio sample right 32-bit audio sample Fig. 4-25: Sample timing of the SDO interface in 32 bit/sample mode D0:346 settings are bit[14] = 0 (SOC not inverted) bit[11] = 0 (no SOI delay) bit[5] = 1 (word strobe inverted) bit[4] = 0 (32 bits/sample) Micronas June 30, 2004; 6251-505-1DS 75 MAS 35x9F 4.6.2.4. S/PDIF Input Characteristics DATA SHEET at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C in P(L/M)QFP package. Symbol Parameter Pin Name Min. VS fs1 fs2 fs3 tP tR tF Signal amplitude Bi-phase frequency Bi-phase frequency Bi-phase frequency Bi-phase period Rise time Fall time Duty cycle tH1,L1 SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI SPDI 0 0 40 81 50 200 Limit Values Typ. 500 2.048 2.822 3.072 326 65 65 60 163 Max. 1000 mVpp MHz MHz MHz ns ns ns % ns 1000 ppm, fs = 48 kHz 1000 ppm, fs = 44.1 kHz 1000 ppm, fs = 32 kHz at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at bit value=1 and fs = 48 kHz minimum/maximum pulse duration with a level above 90 % or below 10 % and at fs = 48 kHz minimum/maximum pulse duration with a level above 90 % or below 10 % and at fs = 48 kHz Unit Test Conditions tH0,L0 SPDI 163 244 ns tR tH1 Bit value = 1 tH0 Bit value = 0 tP tF tL1 tL0 Fig. 4-26: Timing of the S/PDIF input 76 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.6.2.5. S/PDIF Output Characteristics at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCRYSTAL = 18.432 MHz, Typ. values for TA = 25 C in P(L/M)QFP package. Symbol Parameter Pin Name Min. fs1 fs2 fs3 tP tR tF Bi-phase frequency Bi-phase frequency Bi-phase frequency Bi-phase period Rise time Fall time Duty cycle tH1,L1 SPDO SPDO SPDO SPDO SPDO SPDO SPDO SPDO 0 0 50 163 Limit Values Typ. 3.072 2.822 2.048 326 2 2 Max. MHz MHz MHz ns ns ns % ns minimum/maximum pulse duration with a level above 90% or below 10% and at fs = 48 kHz minimum/maximum pulse duration with a level above 90% or below 10% and at fs = 48 kHz fs = 48 kHz fs = 44.1 kHz fs = 32 kHz at fs = 48 kHz, (highest sampling rate) Cload = 10 pF Cload = 10 pF Unit Test Conditions tH0,L0 SPDO 326 ns VS Signal amplitude SPDO VSUPD tR tH1 Bit value = 1 tH0 Bit value = 0 tP tF tL1 tL0 Fig. 4-27: Timing of the S/PDIF output 4.6.2.6. PIO as Parallel Input Interface: DMA Mode In decoding mode, the data transfer can be started after the EOD pin of the MAS 35x9F is set to "high". After verifying this, the controller signalizes the sending of data by activating the PR line. The MAS 35x9F responds by setting the RTR line to the "low" level. The MAS 35x9F reads the data PI[19:12] and sets RTR to low after rising edge of PR. After RTR is set to high, the mC sets PR to low. The next data word write operation will be initialized again by setting the PR line via the controller. Please refer to Figure for the exact timing. The procedure above will be repeated until the MAS 35x9F sets the EOD signal to "0" which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to "0", wait until EOD rises again and then repeat the procedure to send the next block of data. The DMA buffer for MPEG decoding is 30 bytes long. The size for G.729 is 10 bytes. Micronas June 30, 2004; 6251-505-1DS 77 MAS 35x9F DATA SHEET Table 4-8: PIO input DMA mode timing Symbol tst tr tset1 tset2 th trtrq Pin Name PR, EOD PR, RTR PI[19:12] PI[19:12] PI[19:12] RTR dep. on appl. 5*t_ clm 5*t_ clm MP3: 60*t_clm AAC: 140*t_clm Table 4-9: t_clm in MP3 Max. 2000 s t_clm 44.1 2*t_clm33 ns 24 or 16 22.05 12 or 8 11.025 44 81 89 163 177 22.5792 12.2880 11.2896 6.1440 5.6448 Sample rate [kHz] 48 or 32 t_clm [ns] 41 f_clm [MHz] 24.5760 Min. 10 ns Table 4-10: t_clm in AAC Sample rate [kHz] 48 or 32 44.1 t_clm [ns] 33 35 65 71 130 142 f_clm [MHz] 30.720 28.224 15.360 14.112 7.680 7.056 tpr trpr teod teodq 1) PR PR, RTR PR, EOD EOD 5*t_ clm t_clm t_clm 150*t_clm1) 200 ms1) 24 or 16 22.05 12 or 8 11.025 See Parallel I/O Application Note, Order no. 6251-590-2-1IC. tst teod teodq GPIO /EOD tpr = Twr tr /EOD /CS /WR PR trtrq trpr PR MAS3509F /RTR Customer IC GPIO /RTR tset1 = Tchl_dov th D7-D0 PI(19:12) Twrh _csh tset2 PI(19:12) Fig. 4-28: Handshake protocol for writing MPEG data to the PIO-DMA 78 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Table 4-11: PIO Program Download Mode timing Symbol t0 t1 t2 t3 t4 t5 Pin RTR, PCS PCS PCS, RTR RTR PI PI Min. 0 150 0 0.4 50 50 30 5 Max. Unit s ns ns s ns ns 4.6.2.7. PIO as Parallel Input Interface: Program Download Mode Handshake for PIO input in Program Download Mode is accomplished through the RTR, PCS, and PI12..PI19 signal lines (see Fig. 4-29). The PR line should be set to low level. The MAS 35x9F will drive RTR low as soon as it is ready to receive a byte and RTR will stay low until one byte has been written. Writing of a byte is performed with a PCS pulse, driven by the microcontroller. The MAS 35x9F reads data after the falling edge of PCS and will finish the cycle by setting RTR to high level after the rising edge of PCS. The next data transfer is initialized by the MAS 35x9F by driving the RTR line. t0 RTW t1 t2 t3 PIxx t4 PCS Fig. 4-29: PIO program download mode timing t5 Micronas June 30, 2004; 6251-505-1DS 79 MAS 35x9F 4.6.2.8. PIO as Parallel Output Interface Some downloadable software may use the PIO interface (lines PI19...PI12) as output. The data transfer rate and conditions are defines by the software function. Handshaking for PIO output mode is accomplished through the RTW, PCS, and PI12..PI19 signal lines (see Fig. 4-30). The PR line has to be set to high level. RTW will go low as soon as a byte is available in the output buffer and will stay low until a byte has been read. Reading of a byte is performed with a PCS pulse. Data is latched out from the MAS on the falling edge of PCS and removed from the bus on the rising edge of PCS. Table 4-12: PIO output mode timing Symbol t0 t1 t2 t3 t4 t5 Pin RTW, PCS PCS PCS, RTW RTW PI PI Min. 0.010 0.330 0.010 0.330 0.330 0.081 DATA SHEET Max. 1800 Unit s s s 10000 s s s t0 RTW t1 t2 t3 PIxx t4 PCS Fig. 4-30: Output timing t5 80 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 4.6.3. Analog Characteristics at T = TA, VSUPDn, VSUPx = 2.2 to 3.6 V, VSUPA = 2.2 to 3.6 V, fCRYSTAL = 13 to 20 MHz, typical values at TA = 25 C and fCRYSTAL = 18.432 MHz in P(L/M)QFP package Symbol Parameter Pin Name Min. Analog Supply IAVDD IQOSC Current consumption analog audio Current consumption crystal oscillator AVDD0/1 AVDD0/1 5 200 mA A VSUPA = 2.2 V, Mute Codec = off DSP = off DC/DC = on Codec = off DSP = off DC/DC = off Limit Values Typ. Max. Unit Test Conditions ISTANDBY 10 Crystal Oscillator VDCCLK VACLK CIN ROUT DC voltage at oscillator pins Clock amplitude Input capacitance Output resistance XTO XTI, XTO 0.5 3 220 125 94 Analog Reference VAGNDC Analog Reference Voltage AGNDC V RL >> 10 M, referred to VREF VSUPA 1.1 1.3 1.6 VMICBI Bias voltage for microphone MICBI 1.8 2.13 2.62 RMICBI IMAX Source resistance Maximum current microphone bias MICBI MICBI 300 180 A VSUPA >2.2 V bits[15], [14] in register 6Ahex 00 >2.2 V >2.4 V >3.0 V VSUPA >2.2 V >2.4 V >3.0 V bits[15], [14] in register 6Ahex 00 01 10 bits[15], [14] in register 6Ahex 00 01 10 0.5 VSUPA -0.5 VSUPA VPP pF VSUPA = 2.2 V VSUPA = 2.7 V VSUPA = 3.3 V if crystal is used Micronas June 30, 2004; 6251-505-1DS 81 MAS 35x9F DATA SHEET Symbol Parameter Pin Name Min. Limit Values Typ. Max. Unit Test Conditions Analog Audio Input VAI Analog line input clipping level (at minimum analog input gain, i.e. -3 dB) INL/R 2.2 2.6 3.2 VMI Microphone input clipping level (at minimum analog input gain, i.e. +21 dB) MICIN 141 167 282 RinAI Analog line input resistance INL/R 97 20 67 RinMI Microphone input resistance MICIN 94 8 94 SNRAI Signal-to-noise ratio of line input Signal-to-noise ratio of microphone input Total harmonic distortion of analog inputs INL/R 74 dB(A) k k mVpp Vpp VSUPA >2.2 V >2.4 V >3.0 V VSUPA >2.0 V >2.4 V >3.0 V bits[15], [14] in register 6Ahex 00 01 10 bits[15], [14] in register 6Ahex 00 01 10 at minimum analog input gain, i.e. -3 dB at maximum analog input gain, i.e. +19.5 dB not selected at minimum analog input gain, i.e. -21 dB at maximum analog input gain, i.e. +43.5 dB not selected BW = 20 Hz...20 kHz, analog gain = 0 dB, input 1 kHz at VAI-20 dB BW = 20 Hz...20 kHz, analog gain = +21 dB, input 1 kHz at VMI-20 dB BW = 20 Hz...20 kHz, analog gain = 0 dB, resp. 24 dB, input 1 kHz at -3 dBFS = VAI-6 dB resp. VMI-6 dB f = 1 kHz, sine wave, analog gain = 0 dB, input = -3 dBFS 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms SNRMI MICIN 73 dB(A) THDAI INL/R MICIN 0.01 0.02 % XTALKAI Crosstalk attenuation left/right channel (analog inputs) Power supply rejection ratio for analog audio inputs INL/R MICIN AVDD0/1, INL/R MICIN 80 dB PSRRAI 45 20 dB dB 82 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Symbol Parameter Pin Name Min. Limit Values Typ. Max. Unit Test Conditions Audio Output VAO1 Analog output voltage AC OUTL/R RL 1 k input = 0 dBFS digital VSUPA at 0 dB output gain 1.56 1.84 2.27 at +3 dB output gain 2.20 2.60 3.20 dVAO1 Deviation of DC-level at analog output for AGNDCVoltage Analog output voltage AC OUTL/R -20 20 mV Vpp Vpp >2.2 V >2.4 V >3.0 V >2.2 V >2.6 V >3.2 V bits[15], [14] in register 6Ahex 00 01 10 00 01 10 VAO2 OUTL/R RLis 16 headphone and 22 series resistor Input = 0 dBFS digital (see Fig. 5-1 on page 89) VSUPA bits[15], [14] in register 6Ahex 00 01 10 00 01 10 at 0 dB output gain 1.56 1.84 2.27 Vpp >2.2 V >2.4 V >3.0 V at +3 dB output gain 2.00 2.40 3.00 Vpp >2.2 V >2.6 V >3.2 V RoutAO SNRAO Analog output resistance Signal-to-noise ratio of analog output OUTL/R OUTL/R 94 6 dB(A) analog gain = +3 dB, input = 0 dBFS digital RL16 BW = 20 Hz...20 kHz, analog gain = 0 dB input = -20 dBFS for RL16 plus 22 series resistor (see Fig. 5-1 on page 89) for RL1 k THDAO Total harmonic distortion (headphone) OUTL/R 0.03 0.05 % 0.003 LevMuteAO Mute level OUTL/R -113 0.01 dBV A-weighted BW = 20 Hz...22 kHz, no digital input signal, analog gain = mute Micronas June 30, 2004; 6251-505-1DS 83 MAS 35x9F DATA SHEET Symbol Parameter Pin Name Min. Limit Values Typ. 80 Max. Unit Test Conditions XTALKAO Crosstalk attenuation left/right channel (headphone) OUTLR dB f = 1 kHz, sine wave, OUTL/R: RL16 (see Fig. 5-1 on page 89) analog gain = 0 dB input = -3 dBFS PSRRAO Power supply rejection ratio for analog audio outputs AVDD0/1 OUTL/R 70 35 dB dB 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms 4.6.4. DC/DC Converter Characteristics at T = TA, Vin = 1.2 V, Voutn = 3.0 V, fclk = 18.432 MHz, fsw = 384 kHz, PWM mode, L = 22 H, in P(L/M)QFP package (unless otherwise noted) Typ. values for TA = 25 C Symbol Parameter Pin Name Min. VIN VIN Minimum start-up input voltage Minimum operating input voltage DC1 DC2 DC1 DC2 VOUT Programmable output voltage range Output voltage tolerance Output current 1 battery cell Output current 2 battery cells Line regulation Load regulation Maximum efficiency Switching frequency Switching frequency during start-up DCSOn DCSOn 297 384 250 VSENSn VSENSn 0.7 -1.8 95 576 VSENSn 2.0 0.7 0.8 1.1 1.2 3.5 V V V Limit Values Typ. 0.9 Max. V ILOAD 1 mA, DCCF = 5050hex (reset) 1) Unit Test Conditions ILOAD = 50 mA, DCCF = 5050hex (reset) ILOAD = 200 mA, DCCF = 5050hex (reset) Voltage settings in DCCF register (I2C subaddress 76hex) ILOAD = 20 mA TA = 25 C2) VIN = 0.9...1.5 V, 330 F VIN = 1.8...3.0 V, 330 F ILOAD = 20 mA ILOAD = 20...200 mA, VIN = 2.4 V, VOUT = 3.5 V (see Section 2.6.2. on page 12), (see Table 3-3) VSENSn < 1.9 V VOTOL ILOAD1 ILOAD2 dVOUT/ dVIN/VOUT dVOUT/ VOUT hmax fswitch fstartup VSENSn VSENSn -4 4 200 600 % mA mA %/V % % kHz kHz 1) Since the regulators are bootstrapped, once 2) PFM mode regulates approx. 1% higher started they will operate down to 0.7 V input voltage 84 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Symbol Parameter Pin Name Min. Limit Values Typ. 75 135 265 325 1 0.4 Max. Unit Test Conditions IsupPFM1 IsupPFM2 IsupPWM1 IsupPWM2 Ilnmax Supply current in PFM mode VSENS1 VSENS2 A 3) Supply current in PWM mode VSENS1 VSENS2 A 3) 4) VSENSn NMOS switch current limit (low side switch) PMOS switch turnoff current (rectifier switch) NMOS switch on Resistance (low side switch) DCSOn, DCSGn DCSOn VSENSn DCSO1, DCSG1 DCSO2, DCSG2 A A mA m m A PWM-Mode PFM-Mode IIptoff Ron 70 170 280 0.1 ILEAK 3) 4) Leakage current DCSOn, DCSGn Converter off, no load Current into VSENSn Pin. VIN > VOUT + 0.4V; no DC/DC-Converter switching action present Add. current of oscillator at PIN AVDD0/1, (see Section 4.6.3. on page 81) Micronas June 30, 2004; 6251-505-1DS 85 MAS 35x9F 4.6.5. Typical Performance Characteristics DATA SHEET Efficiency vs. Load Current DCDC1 (VOUT = 3.5 V) 100 3.0 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.5 V) 3.0 V 80 Efficiency (%) 1.8 V Efficiency (%) 80 1.8 V 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 40 40 20 20 0 10-4 10 -3 10 -2 10 -1 1 0 10-4 10-3 10-2 10-1 1 Load Current (A) Load Current (A) Efficiency vs. Load Current DCDC1 (VOUT = 3.0 V) 100 2.4 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.0 V) 2.4 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 10-3 10-2 10-1 0 10-4 10 -3 10 -2 10 -1 1 0 10-4 1 Load Current (A) Fig. 4-31: Efficiency vs. Load Current Load Current (A) 86 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Efficiency vs. Load Current DCDC1 (VOUT = 2.2 V) 100 1.5 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 2.2 V) 1.5 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 0 10-4 10 -3 10 -2 10 -1 1 0 10-4 10-3 10-2 10-1 1 Load Current (A) Load Current (A) Maximum Load Current vs. Input Voltage 0.8 DCDC1 Vout: 2.2 V 3.0 V 3.5 V PFM PWM 0.8 Maximum Load Current vs. Input Voltage DCDC2 Maximum Load Current (A) Vout: 2.2 V 3.0 V 3.5 V PFM 0.4 PWM Maximum Load Current (A) 0.6 0.6 0.4 0.2 0.2 0 0.0 1.0 2.0 3.0 Input Voltage (V) Fig. 4-32: Maximum Load Current vs. Input Voltag Note: Efficiency is measured as VSENSn x ILOAD / (Vin x Iin). IAVDD is not included (Oscillator current) 0 0.0 1.0 2.0 3.0 Input Voltage (V) Micronas June 30, 2004; 6251-505-1DS 87 MAS 35x9F DATA SHEET Loadregulation at VOUT = 2.7 V, 2.5 V 2.75 2.7 Output Voltage (V) 2.65 2.6 2.55 2.5 2.45 DCDC1 2.4 0 50 100 150 200 Load Current (mA) 2.9 0 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 3.55 3.5 Output Voltage (V) 3.45 3.4 3.05 3.0 2.95 Loadregulation at VOUT = 3.0 V, 3.5 V 1.5 V 1.5 V VIN: 1.5 V 1.2 V 0.9 V 0.9 V DCDC1 50 100 150 200 Load Current (mA) No-Load Battery Current VOUT = 3.0 V 10 Both DCDC running in PWM One DCDC running in PFM Battery Current (mA) 8 6 4 2 0 0.5 1.0 1.5 2.0 2.5 3.0 Input Voltage (V) 88 June 30, 2004; 6251-505-1DS Micronas VDC2 VDC2 Micronas Serial memory device Parallel memory device e.g. SmartMediaCard 3 MPEG, CELP, SC4 8 Reference clock VDC2 D e.g. SDI-Card Portable radio telephone MPEG, SC4 2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D SII SOD SIC SID SOI PI12 PI13 PI14 PI15 PI16 PI17 PI18 PI19 SOC SPDO PCSQ 10k SIBC PIO-control 100n SPDI2 100n SPDIR FILTL AVDD0 OUTL OUTR AVSS0 470p FILTR AVSS1 VREF 3n XTI VSS POR TE DVS XTO INL VDD XVDD XVSS INR MICBI AVDD1 1 3u3 220p 1n 18p 18p 390 n A 18.432 MHz 3.6...5.6 k 3.3 n 390p MIC 390p separate trace Tape recorder FM radio D A 1u Place VDD / XVDD -filter capacitors above ground plane 390n VDC1 VDC2 390n D 4u7 D 1.5u 1.5u Option for I2C-address connect to VSS or I2CVDD A D Star point ground connection very close to pins DCSG1 and DCSG2 1n A 10n 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 See figure caption 64 17 PVDD 63 18 DCSG1 DCSO1 62 19 DCSG2 61 20 DCSO2 60 21 VSENS2 59 22 DCEN 58 23 CLKO 4k7 VDC2 4k7 57 56 25 I2CD I2CC 55 26 SYNC 54 27 VBAT 100n 470p SPDI1 53 28 PUP 52 29 EODQ SIBI 51 30 PRTRQ 50 31 PRTWQ SIBD 5 49 32 PR D DATA SHEET 5. Application DigiAmp MD-recorder IEC 60958 100 k 3 DAB-receiver DVD-player 75 MPEG (IEC 61937) ADR-receiver 75 220u 22 MAS 35x9F 24 5.1. Typical Application in a Portable Player 220u L R 22 100 Headphone > 16 1.5k 100 1.5k C - MMC/SDI-Card or SMC/CF2+ used as storage media - Dashed lines show optional (external) devices 6.8n 6.8n 22u I2CVDD VSENS1 MICIN AGNDC A 10n Fig. 5-1: Application circuit of the MAS 35x9F. For connections of the DC/DC converters, please refer to Fig. 5-2. June 30, 2004; 6251-505-1DS Place all ceramic capacitors as close as possible to IC pins VDC1 470p capacitorss should be high-Q (NP0 or C0G) <3.3 kOhm see note on page 69 MAS 35x9F 89 MAS 35x9F 5.2. Recommended DC/DC Converter Application Circuit (Power optimized scenario, (see Fig. 2-7 on page 13)). DATA SHEET VBAT DCSO1 L1 = 22 H D1, Schottky AVDD0/1 VSENS1 VDC1 e.g. 2.2 V C3 = 330 F + Vin (Input Voltage) (0.9..1.5 V) C1 = 330 F (low ESR) DCSG1 + MAS 35x9F VSS, XVSS DCEN DCSO2 D Power-On Push Button L2 = 22 H D2, Schottky VSENS2 VDC2 e.g. 3.0 V for C, Storage Media C2 = 330 F (low ESR) DCSG2 VREF AVSS0/1 + Star Point Ground Connection very close to Pins DCSG1 and DCSG2 A D A Fig. 5-2: External circuitry for the DC/DC converters For turn-on voltage of DSP and codec, please refer to Section 2.11.2.1. 90 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Micronas June 30, 2004; 6251-505-1DS 91 MAS 35x9F 6. Data Sheet History 1. Preliminary data sheet: "MAS 35x9F, MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec", Aug. 01, 2001, 6251-505-1PD. First release of the preliminary data sheet. 2. Data Sheet: "MAS 35X9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec", June 30, 2004, 6251-505-1DS. First release of the data sheet. Major changes: - New package diagrams were included for PLQFP64-1, PMQFP64-2, PQFN64-1 - Functional description of the MP3 Block Input Mode now available for improved input timing behavior of the MPEG 1/2/2.5 Layer3 decoder - Important advice for turn-on and operating voltage - Changes in configuration registers - Tables were added: PIO input DMA mode timing; Sample rate in MP3; Sample rate in AAC - Handshake protocol for writing MPEG data to the PIO-DMA was added. DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-505-1DS All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 92 June 30, 2004; 6251-505-1DS Micronas |
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