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Integrated Circuit Systems, Inc.
ICS1524
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
General Description
The ICS1524 is a low-cost, very high-performance frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock synthesis and distribution as well as line-locked and genlocked applications. The ICS1524 offers two channels of clock phase controlled outputs; CLK and DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended output pins. The CLK output channel has a fixed phase relationship to the PLL's input and the DPACLK uses the Dynamic Phase Adjust circuitry to allow control of the clock phase relative to input signal. Optionally, the CLK outputs can operate at half the clock rate and phase aligned with the DPACLK channel, enabling deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL uses either its internal programmable feedback divider or an external divider and is programmed by a standard I2C-busTM serial interface.
Features
* * * * Wide input frequency range * 8 kHz to 100 MHz 250 MHz balanced PECL differential outputs 150 MHz single-ended SSTL_3 clock outputs Dynamic Phase Adjust (DPA) for DPACLK outputs * Software controlled phase adjustment * 360o Adjustment down to 1/64 clock increments * * * * External or internal loop filter selection Uses 3.3 VDC Inputs are 5 volt tolerant. I2C-bus serial interface runs at either low speed (100 kHz) or high speed (400 kHz). Hardware and Software PLL Lock detection
Applications
* * * Generic Frequency Synthesis LCD Monitors and Projectors Genlocking Multiple Video Systems
Block Diagram
Loop Filter
Pin Configuration
VDDD VSSD SDA SCL PDEN EXTFB HSYNC EXTFIL XFILRET VDDA VSSA OSC
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
OSC
I2C
DPACLK DPACLK+/FUNC
24 Pin 300-mil SOIC
I C-bus is a trademark of Philips Corporation.
ICS1524 Rev C 01/31/2003 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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ICS1524
HSYNC
CLK CLK+/-
IREF CLK+ (PECL) CLK- (PECL) DP ACLK+ (PECL) DP ACLK- (PECL) VSSQ VDDQ DP CLK (SSTL) A CLK (SSTL) FUNC (SSTL) LOCK/REF (SSTL) I2CADR
ICS1524
Document Revision History
Rev A ICS1523 Rev T Datasheet used as a starting template New Block Diagram substituted for old 1523 one Removed reference to CLK / 2 Functionality Created a set of clock outputs that bypass the DPA External PDEN is now the IN-SEL MUX control bit Text descriptions changed to support new 1524 block diagram Rev B Replaced page 15 "Layout Guidelines" Replaced SIOC Package diagram on page 22 "Advanced Status" removed Redrew front page graphics for clairity Rev C Corrected Chip Revision and Chip Version values on page 5 Changed Title on Page 1 Minor format changes to pages 8 and 21 Corrected pin names on page 10
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Block Diagram
Osc_Div Reg 7:0-6
PDEN (5)
PD_Pol Reg 0:1 PDen Reg 0:0
LOCK/REF (14)
En_DLS Reg 0:7 En_PLS Reg 0:6
OSC (12)
Ref_Pol Reg 0:2
Osc Divider
1 0
Lock Logic
EXTFIL (8) XFILRET (9)
HSYNC (7)
MUX
Phase/ Freq Detector
PLL_Lock PFD Reg 12:1 Reg 1:0-2
Charge Pump
Filter Select
Fil_Sel Reg 4:7
VCO PostScaler Divider
PECL Bias
PSD Reg 1:4-5 Out_Scl Reg 6:6-7
IREF (24)
Fbk_Sel Reg 0:4
Fbk_Pol Reg 0:3
EXTFB (6)
1 0
Int Filter
MUX
DPA_Lock Reg 12:0
Output Scaler
DPACLK (17)
OE_Tck Reg 6:1
3
SDA (3) SCL (4) I2CADR (13)
Feedback Divider I2C Interface
FDB1 FDB0 Reg: 3:0-3 2:0-7 Reg
DPA_OS Reg 4:0-5 DPA_Res Reg 5:0-1
+
Dynamic Phase Adjust
DPACLK+ (21) DPACLK- (20)
OE-Pck Reg 6:0
CLK (16)
1 0
MUX
OE_T2 Reg 6:3
Func_Sel Reg 0:5
+
CLK+ (23)
OE_P2 Reg 6:2
CLK- (22)
PowerOn Reset
1 0
Ck2_Inv Reg 6:5
MUX
FUNC (15)
OE_F Reg 6:4
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ICS1524 Block Diagram
June 25, 2001
ICS1524
Pin Descriptions
PI N NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P I N NAME VDDD VS S D SDA SCL P DEN EXTF B HS YNC EXTF I L XF I LRET VDDA VS S A OS C I 2C ADR LOCK/ REF F UNC CLK DPACLK VDDQ VS S Q DPACLK- DPACLK+ CLK- CLK+ I REF TYPE P WR P WR I N/ OUT IN IN IN IN IN IN P WR P WR IN IN SSTL SSTL SSTL SSTL P WR P WR PECL PECL PECL PECL IN DESCRI PTI ON Digital supply Digital ground Se r i a l d a t a Se r i a l c l o c k PFD e n a b l e Ex t e r n a l f e e d b a c k Horizontal sync External filter External filter return Analog supply Analog ground Oscillator I 2C a d d r e s s Lo c k i n d i c a t o r / r e f e r e n c e Fu n c t i o n o u t p ut Pixel clockt DPA Delayed Clock Output driver supply Output driver ground DPA Delayed PECL clock DPA Delayed PECL clock + PECL clock PECL clock + Reference current C OMME NT S 3. 3V t o di gi t a l s e c t i ons Ground for digital sections I2C-bus1 I2C-bus1 Suspends charge pump1 External divider input to PFD1 Clock input to PLL1 External PLL loop filter External PLL loop filter return 3. 3V f or a na l og c i r c ui t r y Ground for analog circuitry I n p u t f r o m c r y s t a l o s c i l l a t o r p a c k a g e 1, 2 Chip I2C address select Low = 4Dh read, 4Ch write High = 4Fh read, 4Eh write Displays PLL or DPA lock or REF input SSTL_3 selectable HSYNC output Non-Delayed SSTL_3 Clock DPA Delayed SSTL_3 Clock 3.3V VDD for output drivers Ground for output drivers DPA Delayed Inverted PECL Clock Open drain. DPA Delayed PECL Clock Non-Delayed Inverted PECL Clock Non-Delayed PECL Clock Reference current for PECL outputs Open drain. Open drain. Open drain.
Notes:
1. These LVTTL inputs are 5 V-tolerant. 2. Connect to ground if unused.
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ICS1524
I2C Register Map Summary
Register Index 0h Name Input Control Access R/W Bit Name PDen PD_Pol Ref_Pol Fbk_Pol Fbk_Sel Func_Sel EnPLS EnDLS 1h Loop Control R/W* PFD0-2 Reserved PSD0-1 Reserved 2h 3h FdBk Div 0 FdBk Div 1 R/W* R/W* FBD0-7 FBD8-11 Reserved 4h DPA Offset R/W DPA_OS0-5 Reserved Fil_Sel 5h DPA Control R / W ** DPA_Res0-1 Metal_Rev 6h Output Enables R/W OE_Pck OE_Tck OE_P2 OE_T2 OE_F Ck2_Inv Out_Scl 7h Osc_Div R/W Osc_Div 0-6 In-Sel 8h Reset Write DPA PLL 10h 11h 12h Chip Ver Chip Rev Rd_Reg Read Read Read Chip Ver Chip Rev DPA_Lock PLL_Lock Reserved Bit # 0 1 2 3 4 5 6 7 0-2 3 4-5 6-7 0-7 0-3 4-7 0-5 6 7 0-1 2-7 0 1 2 3 4 5 6-7 0-6 7 0-3 4-7 0-7 0-7 0 1 2-7 Reset Value 1 Phase Detector Enable 0 0 0 0 0 1 0 0 0 0 0 FF F 0 0 0 1 3 0 1 1 1 1 1 0 0 0 1 x x 18 01 N/A N/A 0 External Reference Polarity External Feedback Polarity External Feedback Select Function Out Select Description (0=Disable 1=Enable) (0=Positive Edge, 1=Negative Edge) (0=Positive Edge, 1=Negative Edge) (0=Internal Feedback, 1=External) (0=Recovered HSYNC, 1=Input HSYNC) (0=Disable 1=Enable) (0=Disable 1=Enable)
Phase Detector Input Select
Enable PLL Lock/Ref Status Output Enable DPA Lock/Ref Status Output Phase Detector Gain Reserved Post-Scaler Divider Reserved PLL FeedBack Divider LSBs (bits 0-7) * PLL Feedback Divider MSBs (bits 8-11) * Reserved Dynamic Phase Aligner Offset Reserved Loop Filter Select DPA Resolution
(0 = /2, 1 = /4, 2 = /8, 3 = /16)
(0=External, 1=Internal) (0=16 delay elements, 1=32, 2=Reserved, 3=64)
Metal Mask Revision Number Output Enable for PECL DPACLK Output Enable for STTL_3 DPACLK Output Enable for PECL CLK Output Enable for STTL_3 CLK Output Enable for STTL_3 FUNC ( 0=High Z, 1=Enabled) ( 0=High Z, 1=Enabled) ( 0=High Z, 1=Enabled) ( 0=High Z, 1=Enabled) ( 0=High Z, 1=Enabled)
Select non-delayed CLK (1) or DPA delayed CLK/2 (0) on CLKx pins SSTL DPACLK (Pin 17) Scaler (0 = /1, 1 = /2, 2 = /4, 3 = /8) Osc Divider modulus RESERVED Writing xA hex resets DPA and loads working register 5 Writing 5x hex resets PLL and loads working registers 1-3 Chip Version 17 hex Chip Revision C2 hex DPA Lock Status PLL Lock Status Reserved (0=Unlocked, 1=Locked) (0=Unlocked, 1=Locked)
* Identifies double-buffered registers. Working registers are loaded during software PLL reset. ** Identifies double-buffered register. Working registers are loaded during software DPA reset.
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Detailed Register Description
Name: Register: Index:
PDen PD_Pol Ref_Pol Fbk_Pol Fbk_Sel Func_Sel EnPLS EnDLS
Input Control 0h Read / Write
0 1 2 3 4 5 6 7 1 0 0 0 0 0 1 0 Phase detector Enable Phase/Frequency Detector Input MUX Control Phase/Frequency Detector External Reference Polarity External Reference Feedback Polarity External Feedback Select Function Output Select Enable PLL Lock Status Output on LOCK/REF pin Enable DPA Lock Status Output on LOCK/REF pin
Bit Name Bit # Reset Value Description
Bit
0 1
Name
PDen PD_Pol
Description
RESERVED Input MUX Control
PD_POL Bit 1 0 0 1 1 PDen Pi n 5 0 1 0 1 P h a s e / F r e q u e n cy De t e c t o r I nput Suppl i e d wi t h. . . OSC In HSYNC In HSYNC In OSC In
2
Ref_Pol
Phase/Frequency Detector External Reference Polarity -- Edge of input signal on which Phase Detector triggers. 0 = Rising Edge (default) 1 = Falling Edge External Reference Feedback Polarity -- Edge of EXTFB (pin 6) signal on which Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1). 0 = Positive Edge (default) 1 = Negative Edge External Feedback Select 0 = Internal Feedback (default) 1 = External Feedback Function Output Select -- Selects re-clocked output to FUNC (pin 15). 0 = Recovered HSYNC (default). Regenerated HSYNC output. 1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7). Enable LOCK/REF (pin14) Output
EnPLS EnDLS IN_SEL LOCK/REF(14) 0 0 N/A 0 0 1 N/A 1 if DPA locked, 0 otherwise 1 0 N / A 1 i f P L L l o c ke d , 0 o t h e r w i s e Post Schmitt trigger 1 1 0 HSYNC(7) XOR Ref_Pol 1 1 1 Fosc / Osc_Div
3
Fbk_Pol
4
Fbk_Sel
5
Func_Sel
6 7
EnPLS EnDLS
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Name: Register: Index: Loop Control Register 1h Read / Write*
Bit Name Bit # Reset Value Description
PFD0-2 Reserved PSD 0-1 Reserved 0-2 3 4-5 6 -7 0 0 0 0 Phase Frequency Detector Gain Reserved Post-Scaler Divider Reserved
Bit
0-2
Name
PFD0-2
Description
Phase/Frequency Detector Gain
Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 PFD Ga i n ( A/ 2 r a d) 1 2 4 8 16 32 64 128
3 4-5
Reserved PSD 0-1 Post-Scaler Divider -- Divides the output of the VCO to the DPA and Feedback Divider.
Bit 5 0 0 1 1 Bit 4 0 1 0 1 PSD Divider 2 (default) 4 8 16
6-7
Reserved
* Double-buffered register. Actual working registers are loaded during software PLL reset.
See register 8h for details.
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Name: Register: Index: Feedback Divider 0 Register / Feedback Divider 1 Register 2h, 3h Read / Write*
Bit Name
FBD 0-7 FBD 8 -11 Reserved
Index
2 3 3
Bit #
0 -7 0 -3 4 -7
Reset Value
FF
Description
PLL Feedback Divider LSBs (0 -7).* When Bit 0 = 0, then the total number of clocks per line is even. When Bit 0 = 1, then the total number of clocks is odd. PLL Feedback Divider MSBs (8 -11)*
F
Reserved
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS 1524 generates between HSYNCs. Program these registers with the total number of horizontal clocks per line minus 8.
Reg 3 21 Reg 2 43
3
0
7
6
5
2
1
0
Feedback Divider Modulus
=
12 Feedback Divider Modulus 4103
+8
* Double-buffered registers. Actual working registers are loaded during software PLL reset.
See Register 8h for details.
Name: Register: Index:
DPA Offset Register 4h Read / Write
Bit Name
DPA_OS0-5 Reserved Fil_Sel
Bit # Reset Value
0-5 6 7 0 0 0
Description
Dynamic Phase Adjust Offset Reserved Loop Filter Select
Bit
0-5
Name
DPA_OS0-5
Description
Dynamic Phase Adjust Offset. Selects clock edge offset in discrete steps from zero to one clock period minus one step. Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1). Note: Offsets equal to or greater than one clock period are neither recommended nor supported. Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps. Selects external loop filter (0) or internal loop filter (1). The use of an external loop filter is strongly recommended for all designs. Typical loop filter values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor.
7
Fil_Sel
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ICS1524
Name: Register: Index: DPA Control Register 5h Read / Write*
Bit Name
DPA_Res 0-1 Metal_Rev
Bit #
0-1 2- 7
Reset Value
3 0
Description
Dynamic Phase Adjust Resolution Select. Metal Mask Revision Number.
Bit
0-1
Name
DPA_Res 0 -1
Description
Dynamic Phase Adjust (DPA) Resolution Select. It is not recommended to use the DPA above 160 MHz.
Bit 1 0 0 1 1
Bit 0 0 1 0 1
Delay Elements 16 32 Reserved 64 12
CLK Range, MHz 48 24 80 40
160
2-7
Metal_Rev
Metal Mask Revision Number. After power-up, register bits 7:2 must be written with 111111. After this write, a read indicates the metal mask revision, as below.
Revision A B C1 C2 D E F G Bit 7 1 0 1 0 1 1 1 1 Bit 6 1 1 0 0 1 1 1 1 Bit 5 1 1 1 1 0 1 1 1 Bit 4 1 1 1 1 1 0 1 1 Bit 3 1 1 1 1 1 1 0 1 Bit 2 1 1 1 1 1 1 1 0
* Double-buffered register. Actual working registers are loaded during software DPA reset.
See register 8h for details.
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Name: Register: Index: Output Enable Register 6h Read / Write
Bit Name Bit # Reset Value Description
OE_Pck OE_Tck OE_P2 OE_T2 OE_F Sel_1X Out_Scl 0 1 2 3 4 5 6-7 0 0 0 0 0 0 0 Output Enable for DPACLK Outputs (PECL, Pins 21, 20 ) Output Enable for DPACLK Output (SSTL_3 Pin 17) Output Enable for CLK Outputs (PECL, Pins 23, 22) Output Enable for CLK Output (SSTL_3, Pin 16) Output Enable for FUNC Output (SSTL_3, Pin 15) Select CLK Output Source (Pins 23, 22, 16) CLK Output Scaler (SSTL_3, Pin 16)
Bit
0
Name
OE_Pck
Description
Output Enable for DPACLK Outputs (PECL) 0 = High Z 1 = Enabled Output Enable for DPACLK Output (SSTL_3) 0 = High Z 1 = Enabled Output Enable for CLK Outputs (PECL) 0 = High Z 1 = Enabled Output Enable for CLK Output (SSTL_3) 0 = High Z 1 = Enabled Output Enable for FUNC Output (SSTL_3) 0 = High Z 1 = Enabled Select CLK Output Source (Pins 23, 22, 16) 0 = Half Speed DPA Delayed clock to CLK outputs 1 = Full Speed non-DPA Delayed clock to CLK outputs Clock (CLK, pin 16) Scaler
Bit 7 0 0 1 1 Bit 6 0 1 0 1 CLK Divider 1 2 4 8
1
OE_Tck
2
OE_P2
3
OE_T2
4
OE_F
5
Ck2_Inv
6 -7
Out_Scl
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ICS1524
Name: Register: Index: Oscillator Divider Register 7h Read / Write
Bit Name
Osc_Div 0-6 In_Sel
Bit #
0-6 7
Reset Value
0 1
Description
Osc Divider Modulus Input Select
Bit
0-6
Name
Osc_Div 0-6
Description
Oscillator Divider Modulus. Divides the input from OSC (pin 12) by the set modulus. The modulus equals the programmed value, plus 2. Therefore, the modulus range is from 3 to 129. Input Select -- Selects the input to the Phase/Frequency Detector 0 = HSYNC 1 = Osc Divider
7
In_Sel
Name: Register: Index:
RESET Register 8h Write
Bit Name
DPA Reset PLL Reset
Bit #
0 -3 4 -7
Reset Value
x x
Description
Writing xAh to this register resets DPA working register 5 Writing 5xh to this register resets PLL working registers 1-3
Bit
0 -3 4 -7
Name
DPA PLL
Description
Writing xAh to this register resets DPA working register 5 Writing 5xh to this register resets PLL working registers 1-3
Value xA 5x 5A Resets DPA PLL DPA and PLL
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Name: Register: Index: Chip Version Register 10 h Read
Bit Name
Chip Ver
Bit #
0-7
Reset Value
17
Description
Chip Version 24 (18h )
Name: Register: Index:
Chip Revision Register 11h Read
Bit Name
Chip Rev
Bit #
0 -7
Reset Value
01+
Description
Initial value 01h. +Value increments with each all-layer change.
Name: Register: Index:
Status Register 12 h Read
Bit Name
DPA_Lock PLL_Lock Reserved
Bit # Reset Value
0 1 2 -7 N/A N/A 0
Description
DPA Lock Status PLL Lock Status Reserved
Bit
0
Name
DPA_Lock
Description
DPA Lock Status. (Refer to Register 0h, bits 6 and 7.) 0 = Unlocked 1 = Locked PLL Lock Status. (Refer to Register 0h, bits 6 and 7.) 0 = Unlocked 1 = Locked
1
PLL_Lock
2 -7
Reserved
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ICS1524
I2C Data Characteristics
Bit transfer on the I2C-bus
START and STOP conditions
Acknowledge on the I2C-bus
These waveforms are from "The I2 C-bus and how to use it," published by Philips Semiconductor. The document can be obtained from http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf
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I2C Data Format
RANDOM REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 xWA 7 bit address START condition A data Acknowledge AP STOP condition Acknowledge register address Acknowledge WRITE command
RANDOM REGISTER READ PROCEDURE S 0 1 0 0 1 1 XWA 7 bit address START condition register address Acknowledge WRITE command AS 0 1 0 0 1 1XRA 7 bit address data Repeat START Acknowledge Acknowledge READ command AP STOP condition NO Acknowledge
SEQUENTIAL REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 XWA 7 bit address START condition A data Acknowledge A data Acknowledge A AP Acknowledge Acknowledge STOP condition register address Acknowledge WRITE command
SEQUENTIAL REGISTER READ PROCEDURE S 0 1 0 0 1 1 XWA 7 bit address START condition Direction: register address Acknowledge WRITE command AS 0 1 0 0 1 1XRA 7 bit address data Repeat START Acknowledge Acknowledge READ command A AP data NO Acknowledge Acknowledge STOP condition
From bus host to device
From device to bus host
Note: 1. 2. 3. All values are transmitted with the most-significant bit first and the least-significant bit last. The value of the X bit equals the logic state of pin 13 (I2CADR). R = READ = 1 and W = WRITE = 0
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General Layout Guidelines
* * * * * Use a PC board with at least four layers: one power, one ground, and two signal. Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling. All supply voltages must be supplied from a common source and must ramp together. Any flux or other board surface debris can degrade the performance of the external loop filter. Ensure that the 1524 area of the board is free of contaminants.
Specific Layout Guidelines
1. Digital Supply (VDD) - Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-F capacitor, located as close as possible to the pins. A 0.01-F capacitor may be added for additional high frequency rejection. 2. External Loop Filter - Strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9 (EXTFIL and EXTFILRET) as possible with minimum length traces. Typical loop filter values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see the Frequently Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.) A ground isolated, surface trace can be useful to isolate this section from the rest of the board. 3. Analog PLL Supply (VDDA) - Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of the bead with 4.7-F. Bypass pin 10 to pin 11 (VSSA) with a 0.1-F capacitor. A 0.01-F capacitor may be added for additional high frequency rejection. Locate these components as close as possible to the pins. 4. PECL Current Set Resistor - Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to ground with a 0.1 -F capacitor. 5. .PECL Outputs - Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Ohm characteristic impedance. Locate any optional series "snubbing" resistors as close as possible to the source pins. If the termination resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground planes. [These termination resistors are omitted if the load device implements them internally. For details, see the ICS application note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on Designing a Custom Interface for the ICS1523 (1523AN4.)] 6. Output Driver Supply - Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-F capacitor, located as close as possible to the pins. A 0.01-F capacitor may be added for additional high frequency rejection. 7. SSTL_3 Outputs - SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmission line system at higher-output frequencies. With terminated outputs, the considerations of item 5, "PECL Outputs" apply. See JEDEC documents JESD8-A and JESD8-8.
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PECL Outputs
For information on using the ICS1524's PECL output pins, please refer to Application Note 4: Designing a Custom PECL Interface for the ICS1523
SSTL_3 Outputs
Unterminated Outputs
In the ICS1524, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically 700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor determining high-frequency performance of these single-ended outputs. Typically, no termination is required either for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz.
Terminated Outputs
SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmission line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet LVTTL VIH and VOL requirements, the intrinsic rise and fall times of ICS1524 SSTL outputs are only slightly improved by termination in a low impedance. The ICS1524 SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 Ohms reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.
VDD 330 150 Single L VTTL Load
ICS1524
SSTL-3 Output
For more information on using the ICS1524's SSTL output pins, please refer to Application Note 3: Using SSTL_3 Outputs with CMOS or LVTTL Inputs
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Power Supply Considerations
The ICS1524 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The supply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1524, the supply voltage at the part must be reduced below the threshold voltage (Vth) of the power-on reset circuit. The supply voltage must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state is latched. The amount of time (td) to hold the voltage in a reset state varies with the design. However, a typical value of 10 ms should be sufficient.
Supply V oltage
Vmin
td
Vth = 1.8V
Absolute Maximum Ratings
VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3V VSS - 0.3V to 5.5V VSSA - 0.3V to VDDA +0.3V VSSQ - 0.3V to VDDQ +0.3V - 65C to +150C 175C 260C
ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV (*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
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Recommended Operating Conditions
VDD, VDDQ, VDDA (measured to VSS) . 3.0 to 3.6 V Operating Temperature (Ambient) . . . . . . 0 to +70C
DC Supply Current
PA R A ME T E R Supply Current, Digital Supply Current, Output Drivers Supply Current, Analog S YMB OL I DDD I DDQ I DDA CONDI TI ONS VDDD = 3.6V VDDQ = 3.6V, no output drivers enabled. VDDA = 3.6V MI N -- -- -- MAX 25 6 5 UNI TS mA mA mA
Digital Inputs (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I 2C ADR)
PA R A ME T E R Input High Voltage Input Low Voltage Input Hysteresis Input High Current Input Low Current Input Capacitance IIH IIL Ci n VIH = VDD VIL = 0 S YMB OL VI H VI L CONDI TI ONS MI N 2 VS S - 0 . 3 0. 2 -- -- -- MA X 5. 5 0. 8 0. 6 10 200 10 UNI T S V V V A A pF
SDA (In Output Mode: SDA is Bidirectional)
PA R A ME T E R Output Low Voltage S YMB OL VOL CONDI TI ONS IOUT = 3 mA. VOH = 6.0V maximum as determined by the external pull-up resistor. MI N MA X 0. 4 UNI T S V
PECL Outputs (DPACLK+, DPACLK-, CLK+, CLK -)
PA R A ME T E R Output High Voltage Maximum Output Frequency Output Low Voltage (Note: VOL must not fall below the level given so that the correct value for IOUT can be maintained.) S YMB OL VOH Fp MAX VOL IOUT = 0 VDDD = 3.3V IOUT = programmed value CONDI TI ONS MI N -- -- 1. 0 MA X VDD 250 -- UNI T S V MH z V
SSTL-3 Outputs (DPACLK, CLK, FUNC, LOCK/REF)
PA R A ME T E R Output Resistance Maximum Output Frequency S YMB OL RO Fs MAX 1 AC Input Characteristics
PA R A ME T E R HSYNC Input Frequency OSC Input Frequency S YMB OL fHSYNC fOSC CONDI TI ONS MI N . 008 . 02 MA X 10 100 UNI T S MH z MH z
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ICS1524
VCO Output Frequency and Intrinsic Jitter
700 700
600
Frequency (Slow: 3.0V @ 70C) Frequency (Nominal: 3.3V @ 30C) Frequency (Fast: 3.6V @ 0C) Jitter (3.0V @ 70C) Jitter (3.3V @ 30C) Jitter (3.6V @ 0C)
600
500 VCO Frequency (MHz)
500
400
400
Frequency 300 300
200 Jitter 100
200 Jitter (ps)
100
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2
0
VCO Voltage
Note: Measured with an Externally Forced Filter Voltage
19
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DPA Delay-16 Element Resolution
20 18 16 14 12 10 8 6 4 2 0 0
50 MHz - SVGA @ 72 Hz 157.5 MHz - SXGA @ 85 Hz
ns Delay
4
8
12
16
DPA Setting
DPA Delay - 32 Element Resolution
45 40 35
25.175 MHz - VGA @ 60 Hz 78.75 MHz - XGA @ 75 Hz
ns Delay
30 25 20 15 10 5 0 0
4
8
12
16
20
24
28
32
DPA Setting DPA Delay - 64 Element Resolution
90 80 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
12.27 MHz - NTSC 39.8 MHz - SVGA @ 60
ns Delay
64
Note: Maximum number of data points used for this graph.
DPA Setting
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ICS1524
HSYNC REF PECL CLKPECL CLK+ SSTL-CLK
tF tR t1 t2 t3 tp t0
Output Timing Diagram
tS
t4
t8
t9
FUNC_OUT
t5
tDPA PECL DPACLKPECL DPACLK+
tS t1 t2 t3 tp
t4 tF
t8
t9
SSTL-DPACLK FUNC
Typical Transition Times*
Symbol tR tP tS tF REF PECL CLK SSTL-CLK FUNC_OUT Timing Description Rise 2.8 1.0 1.6 1.2 Fall 1.8 1.2 0.7 1.0 Units ns ns ns ns
Output Timing*
Symbol t0 t1 t2, t3 t4 t5 t6 t7 t8, t9 Timing Description HSYNC to REF delay REF to PECL clock delay PECL clock duty cycle PECL clock to SSTL_3 clock delay PECL clock to FUNC_OUT delay PECL clock to PECL/2 clock PECL clock to SSTL_3-CLK/2 delay SSTL clock duty cycle Min 11.3 -1.0 45 0.2 1.5 1.0 1.1 45 Typ 11.5 0.8 50 0.75 1.9 1.3 1.4 50 Max 12 2.2 55 1.2 2.3 1.5 1.8 55 Units ns ns % ns ns ns ns %
*Note: Measured at 3.6V 0C, 135-MHz output frequency, PECL clock lines to 75 termination, SSTL_3 clock lines unterminated, 20-pF load. Transition times vary based on termination.
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ICS1524
24-Pin SOIC (wide body)
Orde ring Information Part/Orde r N umbe r IC S1524M IC S1524MT M arking Package Shipping
IC S1524M IC S1524M
SIO C - 24 SIO C - 24
Tubes Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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ICS1524
NOTES
23
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Integrated Circuit Systems, Inc.
Corporate Headquarters: 2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone: 610-630-5300 Fax: 610-630-5399 525 Race Street San Jose, CA 95126-3448 Telephone: 408-297-1201 Fax: 408-925-9460
San Jose Operations:
Web Site:
http://www.icst.com
ICS1524 Rev C 01/31/2003
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