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ICs for Carradio Applications
PLL Frequency Synthesizer, IF Counter, 7 bit ADC, 7 & 4 bit DAC with two channel digital alignment
SDA 4336 Version V1
Target Specification 03.05.99 (35 pages incl. this page)
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Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG i.Gr. 21.5.99. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
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7DEOH RI &RQWHQWV 1.1 2.1 2.2 2.3 4.1 4.2 4.3 4.4 4.5 4.6 4.7 6.1 6.1.1 6.1.2 7.1 7.2 7.3
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2YHUYLHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 &LUFXLW 'HVFULSWLRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal input/output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8
%ORFN GLDJUDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 &LUFXLW 'HVFULSWLRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 bit A/D converter for ADC_IN1 and ADC_IN2 detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IF counter for STS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output / input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two channel digital alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOCCAR Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 15 16 16 17
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Semiconductor Group
4
21.5.99
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The SDA 4336 is a Car-Radio PLL frequency synthesizer implemented in Infineon BiCMOS technology B6CA. The device contains the PLL, 2 pin 61.5MHz Oscillator internally coupled to PLL, an IF Counter for AM & FM an 7 bit ADC, an 7 & 4 bit DAC and additonal 2 ports for input- or output-functions. Primary applications are in Car-Radio systems. 376623 * * * * * * * * * * * * * * * * * * * )HDWXUHV
Operation range 8 to 11 V I2C Bus and 3Wire Bus operation selectable Bus interface with low threshold voltage Schmitt-Trigger inputs for interfacing 3V or 5V microprocessors 16 bit fully programmable R- and N-Counter Resolution e.g.100kHz, 50kHz, 25kHz, 12.5kHz, 10kHz, 6.25kHz, 6kHz, 5kHz, 3kHz, 1kHz. 4 programmable phase detector currents : 0.5mA, 1mA, 2mA, 4mA. Rail to rail Loop-amplifier 2 Chargepump-outputs for different timeconstants High running 2 pin crystal oscillator fQ= 61.5MHz , adjustable via Bus Switchable output for 10.25MHz (500mVss @ load-capacitance 10pF) Multiplexed 7 bit ADC for ADC_IN1 and ADC_IN2. Result read out via bus (2 bytes). 7 bit DAC-output, range 0...VREFD5V 4 bit DAC-output, range 0...VREFD5V 3 free programmable output PORTS PORT 1: free programmable output PORT 2: for AM seek mode or input port for stereo-indicator PORT 3: IFC_SD for IF counter resolution or input port for station-detect Search tuning stop with IF counter measurement, result read out via bus or port. two channel digital alignment is available FM-mode AM-mode 1ms...64ms 440kHz...471kHz 250Hz...4kHz
gatetime center-frequency (standard) (double) window-resolution (standard) (double)
320us...40.96ms 10.40MHz...11.19375MHz or 20.80MHz ..22.3875MHz 6.25kHz ...100kHz or 12.5 kHz ... 200 kHz
7\SH SDA 4336
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3DFNDJH P-TSSOP-28
Semiconductor Group
5
21.5.99
Specification
SDA 4336
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IFC_SD IF_AM IF_FM ADC_IN1 ADC_IN2 VCC BUS_MODE SCL SDA BUS_ENA VREFD5V VREFD3V GNDD QUARTZ1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
PORT_4BIT PORT_7BIT VCO VCC1 GNDA PD_1 PD_0 PDA DAL_2 DAL_1 PORT1 XTAL_DIV6 PORT2_STEREO QUARTZ2
SDA 4336
22 21 20 19 18 17 16 15
Semiconductor Group
6
21.5.99
Specification
SDA 4336
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PORT IF_Counter result output or Station-Detect input set by bus IF_AM frequency input with counter request IF_FM frequency input with counter request PORT ADC1 Input PORT ADC2 Input Positive supply voltage (8...11V) Data bus input: Bus-mode select Must be Low for I2C-Bus-mode, must be High for 3 Wire -Bus-mode Data bus input: Clock Clock input of the serial control interface with Schmitt-Trigger input stage Data bus input / output: Bidirectional Data-input/output Data input of the serial control interface with Schmitt-Trigger input stage in write-mode. Data output in readmode. Bus input: Enable Enable input of the serial control interface with Schmitt-Trigger input stage. When EN=H the input signals CLK and DA are disabled. When EN=L the serial control interface is enabled. The received data are transferred to the registers with the positive edge of the EN_Q-signal. Reference voltage for analogue BiCMOS circuity Reference voltage for digital CMOS circuity Digital ground for CMOS circuitry Reference oscillator input1 / Crystal Reference oscillator input2 / Crystal
1R 6\PERO
1 2 3 4 5 6 7 8 9 IFC_SD IF_AM IF_FM ADC_IN1 ADC_IN2 VCC BUS_MODE SCL SDA
10
BUS_ENA
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VREFD5V VREFD3V GNDD QUARTZ1 QUARTZ2
PORT2_STEREO Port2 open-drain output or Stereo detection input set by bus XTAL_DIV6 PORT1 DAL_1 DAL_2 PDA PD_0 PD_1 GNDA VCC1 VCO PORT_7BIT PORT_4BIT Output crystal frequency divided by 6 Port1 free programmable open-drain output Output digtal alignment cannel 1 Output digtal alignment cannel 2 Phase detector output analogue (Tuningvoltage) Charge pump output Phase detector tristate charge pump output for PD_Select = Low Charge pump output Phase detector tristate charge pump output for PD_Select = High Analogue Ground for bipolar circuitry Positive supply voltage for loop-amplifier of PLL (8...11V) VCO frequency input. VCO input with sensitive preampifier for PLL Output port 7 bit DAC (Range: 0...VREFD5V) Output port 4 bit DAC (Range: 0...VREFD5V)
Semiconductor Group
7
21.5.99
Specification
SDA 4336
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Pin No.
Symbol
Function
+5V
1
1
IFC_SD
1: IF_Counter output IF center or Station-Detect input
GNDD
+ 5V
135k
2: IF_AM input
2
330
2
IF_AM
GNDD
+ 5V
50k
3: IF_FM input
3
330
3
IF_FM
GNDD
+5V
4
4
ADC_IN1
4: ADC Input_IN1
+5V 5 pF
5
GNDD
5
ADC_IN2
5: ADC Input_IN2
Semiconductor Group
8
21.5.99
Specification
SDA 4336
Pin No. 6
Symbol VCC
Function
6: Positive poewr supply voltage for serial bus and synthesizer
+ 5V
7
7
BUS_MODE
330
+5V GNDD
7: Bus mode input
+ 5V
8
8
SCL
330
+5V GNDD
8: Bus clock input
+ 5V
9
330
9: Data bus input / output
9
SDA
GNDD
+ 5V
10
10
BUS_ENA
330
+5V GNDD
10: Bus enable input
11
VREFD5V
11: Reference voltage digital section 5V 12: Reference voltage for digital section 3V 13: Ground for serial bus and synthesizer
12
VREFD3V
13
GNDD
Semiconductor Group
9
21.5.99
Specification
SDA 4336
Pin No.
Symbol
Function
+V 14
14
QUARTZ1
2,5 k
14: Reference oscillator input / Crystal
15
5k
5k
15
QUARTZ2
15: Reference oscillator input / Crystal
16
PORT2_STER EO
16: Port2 open-drain output or Stereo detection input set by bus
V+ 3V
17
XTAL_DI V6
2k
17
17: Crystal oscillator auxiliary output (10.25 MHz)
200fF
GNDD
+5V
330
18
18
PORT1
18: Switch port output 2 (open drain)
GNDD
Semiconductor Group
10
21.5.99
Specification
SDA 4336
Pin No.
Symbol
Function
VCC
19
DAL_1
10p 30k
19
19: DAL_1 Output
30k
GNDD
30k
VCC
20
DAL_2
10p 30k
20
20: DAL_2 Output
30k
GNDD
30k
VCCD
+5 V
IPDA
21
21: PLL phase detector output analog (Tuning voltage)
21
PDA
3k
PD
GNDD
Semiconductor Group
12
11
21.5.99
Specification
SDA 4336
Pin No.
Symbol
Function
+5 V
PD
+5 V
22
22
PD_0
22: PLL Charge pump output (Phase detector tristate charge pump output) 23: PLL Charge pump output (Phase detector tristate charge pump output)
23
PD_1
+5 V
23
24 25
GNDA VCC1
24: Ground for loop amplifier 25: Positive power supply for loop-amplifier
+ 5V
10k 26 330 15p 10k
26: VCO input
26
VCO
GNDD
VCC
27
27: Output port 7 bit
27
PORT_7BIT
10k
2.5k
GNDD
Semiconductor Group
12
21.5.99
Specification
SDA 4336
Pin No.
Symbol
Function
VCC
28
28: Output port 4 bit
28
PORT_4BIT
10k
2.5k
GNDD
Semiconductor Group
13
21.5.99
Specification
SDA 4336
%ORFN GLDJUDP
IFC_SD
1
IFCounter
DAC 4, DAC 7
28
PORT_4BIT
IF_AM
2
27
PORT_7BIT
IF_FM
3
26
VCO
ADC_IN1
ADC_IN2
4 2 Channel ADC 5
25
VCC1
24
GNDA
PLL
VCC 6 23 PD_1
BUS_MODE
7
22
PD_0
SCL
I2C8 3W BUS PORTS
9
21
PDA
SDA
20
DAL_2
BUS_ENA
10
19
DAL_1
VREFD5V
11
18
PORT1
VREFD3V
12
Vref
17
XTAL_DIV6
GNDD
13
16
PORT2_STEREO
QUARTZ1
14
Crystal Oscillator
15
QUARTZ2
Semiconductor Group
14
21.5.99
Specification
SDA 4336
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The SDA 4336 is a FM car radio PLL synthesizer system with IF counter for STS, a 2 channel multiplexed 7 bit ADC, a 7 bit DAC- and a 4 bit DAC multifunctional output. The serial bus is switchable between I2C and 3 Wire bus mode.
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The 7 bit A/D converter has two input channels and works as successive approximation converter. The conversion time for both input signals is t = 32 s. The 7-bit digital-words from both channels (14 bit) are read out together via bus into two bytes with the read subadress 82H. The input voltage range for both channels is 0...VREFD5V.
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For FM-mode the center frequency is adjustable in 128 steps (6.25kHz for standard IF-frequency/ 12.5kHz for double IF-frequency) from 10.40MHz...11.19375MHz (standard) / 20.80MHz .. 22.3875MHz (double). The gate-time is adjustable in 8 steps from 320us...40.96ms and the tolerance of the accepted count value, the window is adjustable in 5 steps from +/- 6,25 kHz .. 100 kHz (standard))/ 12.5 kHz .. 200 kHz (double). For AM-mode the center frequency is adjustable in 128 steps (1kHz) from 384kHz .. 511kHz. The gate-time is adjustable in 7 steps from 1ms...64ms and the tolerance of the accepted count value, the window is adjustable in 5 steps from +/- (250Hz...4kHz). Mode is selectable by bus. In FM-mode the input IF_AM is going low with a internally NMOS Open drain transistor. In AM-mode the input IF_FM is going low with a internally NMOS Opendrain transistor. The results IF_CENT and IF_WINDOW are read out via bus (read-subadress 82H & 83H). The result IF_CENT is optional avialable on pin IFC_SD set by bus. If the IF frequency into the preselected window, IF_CENT goes from high to lo level. The IF frequency is outside the preselected window, IF_CENT is high. The bit IF_WINDOW is a hint IF-frequency is to low (IF_WINDOW=high) or is to high (IF_WINDOW=low). In addition to the frequency measurement, thresholds for ADC_IN1 and ADC_IN2 voltages can be programmed via bus (subaddress 0BH). IF_CENT will only go to low level in case fo ADC_IN1 and ADC_IN2 voltages are beyond the thresholds and the frequency is inside the window. When setting the thresholds to zero ADC_IN1 and ADC_IN2 evaluation is disabled.
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A master crystal oscillator provides all necessary clock frequencies for the whole IC. A 61.5 MHz crystal is used in 3rd harmonic mode. The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A converter. The crystal frequency is used as reference frequency for the PLL oscillator and IF counter. It is also used as clock for the DAC's and ADC's. Finally the crystal frequency divided by 6 (10.25 MHz) is available at a pin as low pass filtered voltage. It can be disabled with the serial bus.
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PORT1 is a NMOS Open drain output, PORT2_STEREO and IFC_SD are NMOS Open drain outputs in port mode or inputs set by bus. PORT_7BIT / PORT_4BIT are multifunctionaly DAC outputs with a output voltage range from Vout= 0...VREFD5V, with a resolution from 7 bit and 4 bit.
Semiconductor Group
15
21.5.99
Specification
SDA 4336
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A two channel digital alignment is avialable. Each channel is separatly set by a sloperange from 0.66...2.0 with 7bit resolution additional a offsetvoltage from +/- 0,5V or +/- 1V with 7bit resolution. The offsetvoltage range is: UOFFSET= +/-1V*(n/127), n=0...127, for bit D15=high in subaddresses 09H or 0AH UOFFSET= +/-0,5V*(n/127), n=0...127, for bit D15=low in subaddresses 09H or 0AH direction is set by bit 7in subaddress 09H or 0AH The slope range is: Slope= 128/(64+n) , n=0...127
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The SDA 4336 supports the I2C bus protocol (2 wire) or 3 Wire bus protocol operation selectable by pin 7: BUS_MODE (I2C=low, 3W=high). All bus pins ( BUS_MODE, SCL, SDA, BUS_ENA) are Schmitt-triggered input buffer for 3V or 5V C. The bit stream begins with the most significant bit (MSB), is shifted in (write mode) on the low to high transition of CLK and is shifted out (read mode) on the high to low transition of CLK. I2C bus mode In this mode pin7 (BUS_MODE) = low and pin10 (BUS_ENA)=low. In this mode SDA is a bidirectional input / output pin. Data Transition: Data transition on the pin SDA must only occur when the clock SCL is low. SDA transitions while SCL is high will be interpreted as start or stop condition. Start Condition (STA): A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high level.This start condition must precede any command and initiate a data transfer onto the bus. Stop Condition (STO): A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable high level. This condition terminate the communication between the devices and forces the bus interface into the initial conditions. Acknowlage (ACK): Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has receive the 8 bits of data correctly. Data Transfer Write Mode: To start the communication, the bus master must initiate a start condition, followed by the 8bit chip address (write). The chip address for the SDA 4336 is fixed as "1100110" (MSB at first). The last bit (LSB=A0) of the chip address byte defines the typ of operation to be performed: A0=1, a read operation is selected and A0=0, a write operation is selected. After this comparision the SDA 4336 will generate an ACK. After this device addressing the desired sub address byte and data bytes must be followed. The subaddresses determines which one of the 11 data bytes (00H...07H,09H .. 0BH) is transmitted first. At the end of data transition the master must be generate the stop condition. Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition, fol lowed by the 8bit chip address (write: A0=0), followed by the sub address read (82H or 83H), followed by the chip address (read: A0=1). After that procedure the 16bit data register 82H or the 8bit data register 83H is read out. After the first 8 bit read out, the uP mandatory send LOW during the ACK-clock. After the second 8 bit read out the uP mandatory send HIGH during the ACK-clock. At the end of data transition the master must be generate the stop condition. 3W bus mode In this mode pin7 (BUS_MODE) =high. Pin9 (SDA) is a bidirectional input / output pin in this mode. Pin10 (BUS_ENA) is used to activate the bus interface to allow the transfer of data to / from the device. When BUS_ENA is in an inactive high state, shifting is inhibited.
Semiconductor Group
16
21.5.99
Specification
SDA 4336
Data Transition: Data transition on the pin SDA must only occur when the clock SCL is low. To transfer data to / from the device, BUS_ENA (which must start inactive high) is taken low, a serial transfer is made via SDA, CLK and BUS_ENA is taken back high. The bit stream needs neither the chip address. Data Transfer Write Mode: To start the communication, the BUS_ENA is taken low. The desired sub address byte and data bytes must be followed. The subaddresses determines which one of the 11 data bytes (00H...07H, 09H .. 0BH) is transmitted first. At the end of data transition the BUS_ENA must be high. Data Transfer Read Mode: To start the communication in the read mode, the BUS_ENA is taken low, followed by the sub address read (82H or 83H). After that the device is ready to read out the 16bit data register 82H or the 8bit data register 83H. At the end of data transition the BUS_ENA must be high.
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R / N Counter The SDA 4336 has 2 identical 16bit counter for R and N path. Input frequency for the R-counter is the buffered XTAL-frequency (61.5MHz). Tuning steps can be selected by the 16bit R-counter from fR= 6.25kHz...100kHz. Input frequency for the N-counter is the buffered LO-frequency (in FM mode 98.2MHz...118.7MHz). Three State Phase Comparator The phase comparator generates a phase error signal according to phase difference between f R (R counter output) and fN (N counter output).This phase error signal drives the charge pump current generator. Polarity is fixed positiv for this application note. Charge Pump The charge pump generates signed pulses of current. 4 current values and 2 outputs are available. Loop Amp The integrated rail to rail loop amplifier allows an active loop filter design with external components. Two modes are avialiable with status bit D11: high speed and normal mode.
Semiconductor Group
17
21.5.99
SWITCH LP1/LP2 PD_0
PD_1
Semiconductor Group
16 BIT NCOUNTER PHASE COMP PDA CHARGE PUMP VCC1
VCO
-
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XTAL_IN 16 BIT RCOUNTER DIV BY 6
XTAL_IN_Q
REF OSC
XTAL_DIV6
GND_A
IF_FM MUX IF-COUNT 22 BIT-REFCOUNTER
IF_AM
DAL
DAL_2
VCC 19 BIT-GATECOUNTER
Specification
18
BUS
4 BIT DAC
GND
SUPPLY VOLTAGE
RESULT CONTROL
DAL
DAL_1
VREF_5
VREF_3
BUS_MOVE
PORT_4BIT
SCL
I2C-Bus
or PORT_7BIT PORT1 PORT2_STEREO DIV BY 123 IFC_SD
SDA
3 Wire-Bus
EN_Q
BUS
7 BIT DAC
ADC_IN2 SAMPLE AND HOLD 7 BIT ADC
MUX
ADC_IN1
PORT EXTENSION OUTPUT OR INPUT
SDA 4336
21.5.99
Specification
SDA 4336
3KDVH GHWHFWRU RXWSXWV
fR fn
PD_0/1
Polarity pos.
P-Channel Tri-State. N-Channel
Frequency fV < fR or fV lagging
Frequency fV > fR or fV leading
Frequency fV = fR
Semiconductor Group
19
21.5.99
Specification
SDA 4336
Bus Interface
Pin Function
Pin name Function I2C-mode 3Wire mode BUS_MODE Bus mode select Low High BUS_ENA Enable High=Inactiv, Low=Activ SCL Serial clock Clock input SDA Serial data Data in / out
%XV 'DWD )RUPDW
I2C
Bus Write Mode
MSB
CHIP ADDRESS (WRITE) 1 0 0 1 1 0
LSB
MSB
SUB ADDRESS (WRITE) 00H...07H, 09H .. 0BH S6 S5 S4 S3 S2 S1
LSB
MSB
DATA IN X...0 (X=7 or 15) ... D5 D4 D3 D2 D1
LSB
STA
1
0
ACK
S7
S0
ACK
DX
D0
ACK
STO
I2C Bus Read Mode
MSB
CHIP ADDRESS (WRITE) 1 0 0 1 1 0
LSB R8 LSB
LSB
MSB
SUB ADDRESS (READ) 82H / 83H LSB 0 0 0 0 0 1
LSB
MSB
CHIP ADDRESS (READ) 1 0 0 1 1 0
LSB
STA
1
0
ACK
1
0
ACK
STA
1
1
ACK
MSB
DATA OUT FROM SUB ADD 82H
R14 R13 R12 R11 R10 R9
MSB
DATA OUT FROM SUB ADD 82H R6 R5 R4 R3 R2 R1
R15
MSB
ACK1)
R7
R0
ACK2)
STO
DATA OUT FROM SUB ADD 83H R6 R5 R4 R3 R2 R1
R7
R0
ACK2)
STO
1): mandatory LOW send by uP, 2): mandatory HiGH send by uP
3W Bus Write Mode
MSB
SUB ADDRESS (WRITE) 00H...07H, 09H .. 0BH S6 S5 S4 S3 S2 S1
LSB
MSB
DATA IN X...0 (X=7 or 15) ... D5 D4 D3 D2 D1
LSB
S7
S0
DX
D0
3W Bus Read Mode
MSB
SUB ADDRESS (READ) 82H 0 0 0 0 0 1
LSB
MSB
DATA OUT FROM SUB ADD 82H (MSB)
R14 R13 R12 R11 R10 R9
LSB
MSB
DATA OUT FROM SUB ADD 82H (LSB) R6 R5 R4 R3 R2 R1
LSB
1
MSB
0
LSB
R15
R8
R7
R0
SUB ADDRESS (READ) 83H 0 0 0 0 0 1
MSB
DATA OUT FROM SUB ADD 83H (MSB) R6 R5 R4 R3 R2 R1
LSB
1
1
R7
R0
Chipaddress Organisation
Chip Address (only I2C mode) MSB 1 1 1 1 0 0 0 0 1 1 1 1 0 0 LSB 0 1 Function Chip Address Write Chip Address Read
Subaddress
Sub Addresses of Data Registers Write MSB Bin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 Hex 00H 01H 02H 03H 04H 05H 06H 07H Function Status R_Counter N_Counter DAC7 IF_COUNT_P1 IF_COUNT_P2 Specials DAC4
Semiconductor Group
20
21.5.99
Specification
SDA 4336
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
0 0 0
0 1 1
1 0 1
09H 0AH 0BH
DAL_1 DAL_2
COMP_PRESET
Sub Address of Data Register Read MSB Bin LSB Hex Function Result ADC_IN2, ADC_IN1, IF_Window and IF_Center Result_Misc
1
0
0
0
0
0
1
0
82H
1
0
0
0
0
0
1
1
83H
Data Byte Specification
Status Subaddress 00H Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function not used (must be=0) PORT2_STEREO PORT1 Stereo-Flag Loopamp current not used (must be=0) not used (must be=0) AM / FM ADC_Single ADC_Mode ADC_ON DAC4 PD_Select CP_Current 2 CP_Current 1 CP_Mode R_Counter Subaddress 01H Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function 2
15
N_Counter Subaddress 02H Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function 2
15
COMP_PRESET Subaddress 0BH Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function
not used
V_IN1_26 V_IN1_25 V_IN1_24 V_IN1_23 V_IN1_22 V_IN1_21 V_IN1_20
214 213 2 2
12 11
214 213 2 2
12 11
210 2 2
9 8
210 2 2
9 8
27 26 2
5
27 26 2
5
DAL_Mode
V_IN2_26 V_IN2_25 V_IN2_24 V_IN2_23 V_IN2_22 V_IN2_21 V_IN2_20
24 23 2
2
24 23 2
2
21 20
21 20
DAC7 Subaddress 03H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function
IF_Count_P1 Subaddress 04H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function
IF_Count_P2 Subaddress 05H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function
CF_Mode
Specials Subaddress 06H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function XTAL_DIV6 not used not used not used XTAL_3 XTAL_2 XTAL_1 XTAL_0
IF_DAC4 Subaddress 07H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function not used not used not used not used DAC4_3 DAC4_2 DAC4_1 DAC4_0
Enable
DAC7_6 DAC7_5 DAC7_4 DAC7_3 DAC7_2 DAC7_1 DAC7_0
Enable
Station_ Detect Win_2 Win_1 Win_0 Gate_2 Gate_1 Gate_0
CF_6 CF_5 CF_4 CF_3 CF_2 CF_1 CF_0
Semiconductor Group
21
21.5.99
Specification
SDA 4336
DAL_1 Subaddress 09H Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function Offset O1_R (Range) Slope S1_26 Slope S1_2 Slope S1_2 Slope S1_2 Slope S1_2
5 4 3 2 1
DAL_2 Subaddress 0AH Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function Offset O2_R (Range) Slope S2_26 Slope S2_2 Slope S2_2 Slope S2_2 Slope S2_2
5 4 3 2 1
Results ADC_IN1, ADC_IN2 and IF counter Subaddress 82H (read address) Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function IF_window ADC_IN2_26 ADC_IN2_2 ADC_IN2_2 ADC_IN2_2
5 4 3 2 1
Result Misc Subaddress 83H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function
IF_Window
IF_Center ADC_IN1_Comp ADC_IN2_Comp Res Res Station_Detect Stereo_Flag
ADC_IN2_2
Slope S1_2
Slope S2_2
ADC_IN2_2
Slope S1_20 Offset O1_P (Polarity) Offset O1_2
6
Slope S2_20 Offset O2_P (Polarity) Offset O2_26
ADC_IN2_20 IF_center ADC_IN1_26 ADC_IN1_25 ADC_IN1_24 ADC_IN1_23 ADC_IN1_22 ADC_IN1_21 ADC_IN1_20
Offset O1_25 Offset O1_24 Offset O1_23 Offset O1_22 Offset O1_21 Offset O1_20
Offset O2_25 Offset O2_24 Offset O2_23 Offset O2_22 Offset O2_21 Offset O2_20
Semiconductor Group
22
21.5.99
Specification
SDA 4336
Status, Subaddress 00H MSB D15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 1 0 1 0 1 0 0 1 0 x x 0 0 1 x x 1 1 1 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0 1 D14 D13 D12 D11 D10 0 D9 0 LSB MSB D8 D7 D6 D5 D4 D3 D2 D1 LSB Function D0 these bits must be = 0 opendrain Port2_Stereo output = high level (port-mode) opendrain Port2_Stereo output = low level (port-mode) opendrain Port2_Stereo is input for Stereoflag opendrain Port1 output = high level opendrain Port1 output = low level Loopamp currentsource high (ILOOPAMP=2.4mA) for high speed tuning Loopamp currentsource low (ILOOPAMP=1.2mA) AM-Mode FM-Mode 7 bit AD Converter enabled for single mode, stop 7 bit AD Converter enabled for single mode start. To restart single mode write the same bits once more. 7 bit AD Converter enabled for continuos mode run. 7 bit AD Converter enabled for single or continous mode 7 bit AD Converter disabled for single and continous mode DAC4 enabled (see subaddress 07H) DAC4 disabled (see subaddress 07H) Phase detector select; PD_1 = ON, PD_0 = OFF Phase detector select; PD_1 = OFF, PD_0 = ON Chargepump current Icp3 = 4mA Chargepump current Icp2 = 2mA Chargepump current Icp1 = 1mA Chargepump current Icp0 = 500uA Chargepump enabled Chargepump disabled
Subaddress 01H, R_Counter and Subaddress 02H, N_Counter MSB D15 1 D14 1 D13 1 D12 D11 1 1 D10 1 D9 1 LSB MSB D8 1 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 LSB Function D0 1 Divider by 65535
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 0 0
1 0 1 1
1 0 1 0
1 1 1 0
1 1 1 1
0 0 1 1
1 0 0 0
0 1 1 0
0 1 0 1
0 1 0 1
0 0 0 1
Divider by 2000 Divider by 1230 Divider by 1000 Divider by 615
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 0 0
1 0 0
0 0 0
0 1 0
1 0 0
0 1 1
0 0 0
Divider by 100 Divider by 10 Divider by 2
Semiconductor Group
23
21.5.99
Specification
SDA 4336
Subaddress 03H, DAC7 MSB D7 1 0 x x x x x x x D6 D5 D4 D3 D2 D1 LSB Function D0 DAC7 enabled DAC7 disabled
Subaddress 04H, IF_Count_P1 MSB D7 1 0 D6 D5 D4 D3 D2 D1 LSB Function D0 IF_Count enabled IF_Count disabled Port IFC_SD is input for station_detect to start IF_COUNT externally, if the station detetect goes to high Port IFC_SD is output for result IF_CENTER FM_MODE / AM_MODE
1
1
1
1
1
1
1
1
DAC7_127 (full scale)
1
0
1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
DAC7_66 (MSB+3*LSB) DAC7_65 (MSB+2*LSB) DAC7_64 (MSB+LSB) DAC7_63 (MSB) DAC7_62 (MSB-LSB) DAC7_61 (MSB2*LSB) DAC7_60 (MSB3*LSB) DAC7_59 (MSB4*LSB)
1 0 0 0 0
0 1 1 0 0
0 1 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0
Window= 100kHz* / 4kHz Window= 50kHz* / 2kHz Window= 25kHz* / 1kHz Window= 12.5kHz* / 500Hz Window= 6.25kHz* / 250Hz Gatetime= 40.96ms/not used Gatetime= 20.48ms / 64ms Gatetime= 10.24ms / 32ms Gatetime= 5.12ms / 16ms Gatetime= 2.56ms / 8ms Gatetime= 1.28ms / 4ms
1
0
0
0
0
0
1
0
DAC7_2 (zero+2*LSB) DAC7_1 (zero+LSB; LSB=39mV) DAC7_0 zero *
0
1 1
0 0
0 0
0 0
0 0
0 0
0 0
1 0
0 0
0 0
1 0
Gatetime= 640us / 2ms Gatetime= 320us / 1ms
Valid for D7=0 in subaddress 05H in FM_Mode Multiply window value with 2 for D7=1 in subaddress 05H (e. g. D7=0 Window= 6.25 kHz D7=1 Window= 12.5 kHz)
Semiconductor Group
24
21.5.99
Specification
SDA 4336
Subaddress 05H, IF_Count_P2, FM_Mode Centerfrequency = CF, CF_FMstep= 6.25kHz / 12.5kHz MSB D7 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 D5 D4 D3 D2 D1 LSB Function D0 Centerfrequency CF1 Centerfrequency CF0 CF1= 22.3875 MHz CF0= 11.1937 MHz
Subaddress 05H, IF_Count_P2, AM_MODE Centerfrequency = CF, CF_AMstep= 1kHz MSB D7 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D6 D5 D4 D3 D2 D1 LSB Function D0 Center frequency CFO CF_AM= 471kHz CF_AM= 470kHz CF_AM= 469kHz CF_AM= 468kHz CF_AM= 467kHz CF_AM= 466kHz CF_AM= 465kHz CF_AM= 464kHz CF_AM= 463kHz CF_AM= 462kHz CF_AM= 461kHz CF_AM= 460kHz CF_AM= 459kHz CF_AM= 458kHz CF_AM= 457kHz CF_AM= 456kHz CF_AM= 455kHz CF_AM= 454kHz CF_AM= 453kHz CF_AM= 452kHz CF_AM= 451kHz CF_AM= 450kHz CF_AM= 449kHz CF_AM= 448kHz CF_AM= 447kHz CF_AM= 446kHz CF_AM= 445kHz CF_AM= 444kHz CF_AM= 443kHz CF_AM= 442kHz CF_AM= 441kHz CF_AM= 440kHz
1 0
1 1
0 0
0 0
0 0
0 0
0 0
0 0
CF1= 22.600 MHz CF0= 10.800 MHz
0 0 0
1 0 1 0 1 0
0 0 0 0 0 0
1 1 1 1 1 1
1 1 1 1 0 0
0 0 0 0 1 1
0 0 0 0 1 1
0 0 0 0 1 1
1 1 0 0 1 1
CF1= 21.4125 MHz CF0= 10.70625 MHz CF1= 21.400 MHz CF0= 10.700 MHz CF1= 21.3875 MHz CF0= 10.69375 MHz
0 0 0 0 0 0 0
1 0
0 0
1 1
0 0
0 0
0 0
0 0
0 0
CF1= 21.200 MHz CF0= 10.600 MHz
0 0 0
1 0
0 0
0 0
1 1
0 0
0 0
0 0
0 0
CF1= 21.000 MHz CF0= 10.500 MHz
0 0 0
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
CF1= 20.800 MHz CF0= 10.400 MHz
0 0 0
Centerfrequencies FM for D7=1 D7=0 CF1= 20.800 MHz +n*12.5 kHz, CFStep=12.5 kHz CF0= 10.400 MHz +n*6.25 kHz, CFStep=6.25 kHz n=0...127
0 0 0 0 0 0 0 0 0
Centerfrequencies AM for D7=0 CF_AM=384kHz+n*1kHz, CFStep=1kHz n=0...127
Semiconductor Group
25
21.5.99
Specification
SDA 4336
Subaddress 06H, Specials MSB D7 D6 D5 x 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D4 x D3 D2 D1 LSB Function D0 not used XTAL_DIV6 enabled XTAL_DIV6 disabled DAL_1 / 2 enabled DAL_1 / 2 disabled XTAL_adjust CL = 15 pF XTAL_adjust CL = 14pF XTAL_adjust CL = 13 pF XTAL_adjust CL = 12 pF XTAL_adjust CL = 11 pF XTAL_adjust CL = 10 pF XTAL_adjust CL = 9 pF XTAL_adjust CL = 8 pF XTAL_adjust CL = 7 pF XTAL_adjust CL = 6 pF XTAL_adjust CL = 5 pF XTAL_adjust CL = 4 pF XTAL_adjust CL = 3 pF XTAL_adjust CL = 2 pF XTAL_adjust CL = 1pF XTAL_adjust CL = 0pF
Subaddress 07H, IF_DAC4 MSB D7 x D6 x D5 x D4 x 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D3 D2 D1 LSB Function D0 not used DAC4_15 (full scale) DAC4_14 DAC4_13 DAC4_12 DAC4_11 DAC4_10 (MSB+2*LSB) DAC4_9 (MSB+LSB) DAC4_8 (MSB) DAC4_7 DAC4_6 DAC4_5 DAC4_4 DAC4_3 (zero+3*LSB) DAC4_2 (zero+2*LSB) DAC4_1 (zero+LSB; LSB=333mV) DAC4_0 zero
Subaddress 0BH, Comp preset MSB D15 X
IN1P26 IN1P25 IN1P24 IN1P23 IN1P22 IN1P21 IN1P20 IN2P26 IN2P25 IN2P24 IN2P23 IN2P22 IN2P21 IN2P20
LSB D14 D13 D12 D11 D10 D9 D8
MSB D7 D6 D5 D4 D3 D2 D1
LSB D0 Function not used Preset value IN1 Preset value IN2 Digital Alignment ON Digital Alignment OFF
1 0
Semiconductor Group
26
21.5.99
Specification
SDA 4336
Subaddress 09H, DAL_1 Subaddress 10H, DAL_2 MSB D15 1 0 1 1 1 1 1 1 1 D14 D13 D12 D11 D10 D9 LSB MSB D8 D7 D6 D5 D4 D3 D2 D1 LSB Function D0 Offset O1_H / O2_H: range high: full scale =1V Offset O1_L / O2_L: range low: full scale =0,5V Slope S1_127 / S2_127 (full scale: slope=0.66)
1
0
0
0
0
0
0
Slope S1_63 / S2_63 (MSB: slope=1.0)
0 0
0 0
0 0
0 0
0 0
0 0
1 0
Slope S1_1 / S2_1 (LSB: slope=1.969) Slope S1_0 /S 2_0 (zero: slope=2)
1 0 1 1 1 1 1 1 1
Offset_1 / _2: polarity positiv Offset_1 / _2: polarity negativ Offset O1 / O2_127 (full scale: 1V or 0,5V, direction depend from D7, value range depend from D15)
1
0
0
0
0
0
0
Offset O1 / O2_63 (MSB: 0,5V or 0.25V, direction depend from D7, value range depend from D15))
0 0
0 0
0 0
0 0
0 0
0 0
1 0
Offset O1 / O2_1 (LSB: 7,87mV or 3,9mV, direction depend from D7, value range depend from D15) Offset O1/ O2_0 (zero: 0)
n-------- , D15=1 127 n Offset O1/2_L= ---------------, D15=0 127x2
Offset O1/2_H=
n= 0 .. 127
Slope =
128 ------------------( 64 + n )
n=0 .. 127
Subaddress 82H, Read Results from ADC_IN1, ADC_IN2 and IF counter MSB D15 1 D14 D13 D12 D11 D10 D9 LSB MSB D8 D7 1 D6 D5 D4 D3 D2 D1 LSB Function D0 IF_counter result: IF frequency is outside the desired window. IF frequency is lower as the desired IF frequency. IF_counter result: IF frequency is outside the desired window.IF frequency is higher as the desired IF frequency. IF_counter result: IF frequency is inside the desired window Result ADC_IN2 byte IN2_6...IN2_0 IN1 _26 IN1 _25 IN1 _24 IN1 _23 IN1 _22 IN1 _21 IN1 _20 Result ADC_IN1 byte IN1_6...IN1_0
0
1
x IN2 _26 IN2 _25 IN2 _24 IN2 _23 IN2 _22 IN2 _21 IN2 _20
0
Semiconductor Group
27
21.5.99
Specification
SDA 4336
Subaddress 83H, Read Results from MISC MSB D7 1 D6 1 D5 D4 D3 D2 D1 LSB D0 Function IF_counter result: IF frequency is outside the desired window. IF frequency is lower as the desired IF frequency. IF_counter result: IF frequency is outside the desired window. IF frequency is higher as the desired IF frequency. IF_counter result: IF frequency is inside the desired window. 1 0 1 0 1 1 1 0 X IN1_Voltage is higher than the preseted value (D8 .. D14) in 0BH IN1_Voltage is lower than the preseted value (D8 .. D14) in 0BH IN2_Voltage is higher than the preseted value in (D0 .. D6) 0BH IN2_Voltage is lower than the preseted value in (D0 .. D6) 0BH not used Start IF_counter on the rising edge from low to high Standby IF_counter Input signal Stereo_Flag from PORT2_STEREO (x=0 or 1) see also D7 & D6 in Subadress 04H, IF_Count_P1
0
1
X
0
Semiconductor Group
28
21.5.99
Specification
SDA 4336
,& %XV 7LPLQJ
BUS_MODE = LOW
tBUF
SDA
tHD.STA tR tLOW tF tSP
SCL
P
tHD.STA
S
tHIGH
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
S
P
BUS_ENA pulsed or mandatory low
tSU.ENASDA tSU.ENASDA
tSU.ENASDA
3W-Bus Timing
BUS_MODE = HIGH
SDA
tSP tF
S
tLOW t R
P
SCL
tHD.STA
tHD.DAT
tHIGH
tSU.DAT
tSU.STO
BUS_ENA
tSU.STAENA tWHEN
tSU.STOENA
Semiconductor Group
29
21.5.99
Specification
SDA 4336
Parameter LOW level input voltage (SDA, SCL, BUS_ENA, BUS_MODE) HIGH level input voltage (SDA, SCL, BUS_ENA, BUS_MODE)
Symbol VIL VIH
Limit Values min. -0.5 2.10 0 0 max. 0.90 5.50 50 0.40
Unit V V ns V ns kHz us us us us us ns ns
Pulse widh of spikes which must be suppressed by the tSP input filter LOW level output voltage 3mA sink current (SDA) VOL Output fall time from VIHmin to VILmax with a bus capacitOF tance from 10pF to 400pFwith up to 3mA SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated. 1) LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set -up time Rise, fall time of both SDA and SCL signals Set-up time for STOP condition Setup time SCL to BUS_ENA H-pulsewidth (BUS_ENA)
1) 2) 2) 1) 1) 1)
20+0.1Cb3) 250 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 0.6 400 0.6 0.6
3)
fSCL tBUF tHO.STA tLOW tHIGH tSU.STA tHD.DAT tSU.DAT tR, tF tSU.STO Cb tSU.SCLEN tWHEN
400
300
ns us pF us us
Capacitive load for each bus line
only in I2C bus mode only in 3W bus mode 3)C = capacitance of one bus line in pF. b Note that the maximum tF for the SDA and SCL bus lines quoted at 300ns is longer than the specified maximum tOF for the output stages (250ns).This allows series protection resistors to be connected between the SDA / SCL pins and the SDA /SCL bus lines without exceeding the maximum specified tF.
Semiconductor Group
30
21.5.99
Specification
SDA 4336
(OHFWULFDO &KDUDFWHULVWLFV
$EVROXWH 0D[LPXP 5DWLQJV
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result.
Parameter ESD-Protection all bipolar pins HBM ( R=1.5k , C=100pF ) ESD-Protection all CMOS pins HBM ( R=1.5k , C=100pF ) Total power dissipation Ambient temperature Junction temperature Storage temperature Thermal resistance T-SSOP-28 (sys-air) Symbol VESD VESD Ptot TA Tj Tstg TthSA - 40 - 40 Limit Values min. -2 t.b.d. max. 2 t.b.d. 150 85 125 125 114 Units kV kV mW C C C K/W
All values are referred to ground (pin), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from Vs across the designated pin), it has a positive sign.
Semiconductor Group
31
21.5.99
Specification
SDA 4336
2SHUDWLQJ 5DQJH
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Parameter Supply voltage Current consumption Ambient temperature
$&'& &KDUDFWHULVWLFV
Symbol VVCC Ivcc TA
Limit Values min 8 - 40 max 11 35 85
Unit V mA C
Test Conditions
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Parameter TA = 25 C,VVCC = 8.5V Power supply Total current consumption Voltage reference Crystal oscillator Operating frequency Negative input impedance Negative input impedance Input impedance crystal Spurious harmonics crystal Bus controlled adjust range f16-17 Z16-17 Z16-17 Rcr asp fadj vXTAL_DIV6
_ON
Symbol
Limit Values min typ 20 4.7 5 61.5 - 250 1.4 tbd - 20 40 500 1.5 60 50 5.3 max
Unit
Test conditions
IVCC VREFD5V
mA V MHz k dB ppm mVpp VDC dB 3rd harmonic f = 61.5 MHz f = 20.5 MHz 3rd harmonic f < 200 MHz see diagram SUB06h f = 10.25 MHz, Cload = 10pF f = 10.25 MHz, Cload = 10pF Signal supression f = 10.25 MHz
VXTAL_DIV6 Bus controlled output XTAL_DIV6
_ON
VXTAL_DIV6
_OFF
VXTAL_DIV6
_OFF
mVDC Cload = 10pF
Chargepump output PD_1, PD_0 (Loopfilter input) DC voltage DC current DC current DC current DC current Tristate output current VPD_1 VPD_0 IPD_1_3 IPD_0_3 IPD_1_2 IPD_0_2 IPD_1_1 IPD_0_1 IPD_1_0 IPD_0_0 IPD_1_OFF IPD_0_OFF 32 3.2 1.6 0.8 400 2.5 4 2 1 500 0.1 4.8 2.4 1.2 600 10 V mA mA mA uA nA VPD_1/0 = 2.5V , guaranteed by design 21.5.99 see Status, Subaddress 00H, bit D1, D2 VPD_1/0 = 2.5V locked
Semiconductor Group
Specification
SDA 4336
Parameter TA = 25 C,VVCC = 8.5V
Symbol
Limit Values min typ max
Unit
Test conditions
Loop amplifier tuningvoltage output (Loopfilter output) LOW output voltage HIGH output voltage VPDA_L VPDA_H 0 VVCC0.5V tbd. tbd. 400 VCC mV mV ITUNE = 100 uA ITUNE = -100 uA VTUNE = 4V, VPD_1 = 0V, VPD_0 = 0V (see Status, Subaddress 00H, bit D11) fIF_1 = 440...471kHz fIF_1 = 455kHz fIF_0 = 10.60...10.80MHz / 20.800 .. 22.3875 MHz fIF_0 = 10.70MHz
HIGH output current source LOW output current source IF_Counter input sensitivity AM input impedance AM input sensitivity FM input impedance FM PLL for synthesizer (see PLL Synthesizer on page 17) PLL / VCO step size (programmable via R-counter) N-counter divide ratio R-counter divide ratio input sensitivity input impedance ADC converter ADC_IN1 / IN2 input voltage range Sampling capacitance least significant bit zero offsetfailure full scale nonlinearity coverting time for both channels DAC_7 converter PORT_7BIT output voltage range least significant bit zero offsetfailure full scale nonlinearity output current output capacitance
IPDA_H IPDA_L
-2.4 mA -1.2
vIF_1 ZIF_1 vIF_0 ZIF_0
50
tbd. 180
mV k mV k
50
tbd. 10
fref N R vVCO ZVCO vADC_IN1/2 CS VLSB VZERO VFS V fCONV
6.25 2 2 50 tbd. 2.5 0 5 39, 37 tbd. tbd.
VREFD5V
100 65535 65535
kHz
f crystal = 61.5 MHz 16-Bit 16-Bit
mV k V pF mV mV tbd. +/-1.5 V LSB us 5.40 V mV mV tbd. +/-1.5 50 10 V LSB uA pF
fVCO = 70...120MHz fVCO = 120MHz
VREFD5V
tbd.
32
VPORT_7BIT 0 VLSB VZERO VFS V IPORT_7BIT CPORT_7BIT tbd. 39, 37 tbd.
VREFD5V
tbd.
Semiconductor Group
33
21.5.99
Specification
SDA 4336
Parameter TA = 25 C,VVCC = 8.5V DAC_4 converter PORT_4BIT output voltage range least significant bit zero offsetfailure full scale nonlinearity output current output capacitance DAL_1 / 2 output voltage range slope_range_1/2 slope_min_1/2 slope_max_1/2 offset_low range offset_high range offset_zero offset_low_LSB offset_high_LSB offset_low_fullscale offset_high_fullscale output current output capacitance
Symbol
Limit Values min typ max 5.40 333.33 tbd. tbd.
VREFD5V
Unit
Test conditions
VPORT_4BIT 0 VLSB VZERO VFS V IPORT_4BIT CPORT_4BIT
V mV mV
tbd. +/-1.5 50 10 VVCC0.2V 2.00
V LSB uA pF
tbd.
VDAL_1 / 2 SL_R1/2 SL_L1/2 SL_H1/2 OL_R1/2 OH_R1/2
O_ZERO1/2 OL_LSB1/2 OH_LSB1/2
0.2 0.6702 tbd. tbd. -0.5 -1.0 0 3.9 7.87 tbd. 0.5 1 0.6702 2.00
V 1 1 1 V V V mV mV Serial-resistor: Rext=10k Cext=1nF
tbd. tbd. 0.5 1.0 tbd.
OL_FS1/2 IDAL_1 / 2 CDAL_1 / 2
tbd. tbd. tbd. tbd.
V V uA pF
OH_FS1/2 tbd.
Port outputs, PORT1, PORT2_STEREO, IFC_SD (see Output / input Ports on page 15) LOW output voltage HIGH Leackage current
2
VP IP_LEACK
0 0
100
400 100
mV nA
IP = 1 mA VP = 5 V
I C / 3-Wire-bus (BUS_MODE, SCL, SDA, BUS_ENA) (see I2C Bus Timing on page 29 and Bus Data Format on page 20) H-input voltage L-input voltage Hysteresis of Schmitt trigger inputs (BUS_MODE, SCL, SDA, BUS_ENA) Input capacity VIH VIL Vhys CI 2.10 -0.5 0.30 5 5.50 0.90 V V V pF
Semiconductor Group
34
21.5.99
Specification
SDA 4336
3DFNDJH 2XWOLQHV 376623 (Plastic Package)
Semiconductor Group
35
21.5.99

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