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K7N163631B K7N161831B
Document Title
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
Revision History
Rev. No. 0.0 0.1 0.2 History 1. Initial document. 1. Update the current spec(Icc, ISB) 1. Change the ISB,ISB1,ISB2 - ISB ; from 120mA to 170mA - ISB1 ; from 80mA to 150mA - ISB2 ; from 80mA to 130mA 1. Remove the 1.8V Vdd voltage level 1. Remove the -20 and -13 speed bin Draft Date Mar. 23, 2004 May. 13, 2004 Sep. 21. 2004 Remark Advance Preliminary Preliminary
0.3 0.4
Oct. 18, 2004 Jan. 04, 2005
Preliminary Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
16Mb NtRAM(Flow Through / Pipelined) Ordering Information
Org. Part Number Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) 6.5ns 250/167MHz 6.5ns 250/167MHz PKG Temp
K7M161835B-QC(I)65 1Mx18 K7N161831B-Q(F)C(I)25/16 K7M163635B-QC(I)65 512Kx36 K7N163631B-Q(F)C(I)25/16
FlowThrough Pipelined FlowThrough Pipelined
3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5
C ; Commercial Q : 100TQFP Temp.Range F : 165FBGA I ; Industrial Temp.Range
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
FEATURES
* VDD= 2.5 or 3.3V +/- 5% Power Supply. * Byte Writable Function. * Enable clock and suspend operation. * Single READ/WRITE control pin. * Self-Timed Write Cycle. * Three Chip Enable for simple depth expansion with no datacontention . * A interleaved burst or a linear burst mode. * Asynchronous output enable control. * Power Down mode. * 100-TQFP-1420A * 165FBGA(11x15 ball aray) with body size of 13mmx15mm. * Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7N163631B and K7N161831B are 18,874,368-bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N163631B and K7N161803B are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP and 165FBGA packages. Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -25 4.0 2.6 2.6 -16 6.0 3.5 3.5 Unit ns ns ns
LOGIC BLOCK DIAGRAM
LBO A [0:18]or A [0:19] ADDRESS REGISTER A2~A18 or A2~A19 A0~A1 BURST ADDRESS COUNTER
A0~A1 512Kx36, 1Mx18 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd 36 or 18
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
PIN CONFIGURATION(TOP VIEW)
BWd BWb BWa BWc
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
CKE
CS2
ADV
CLK
CS1
CS2
VDD
VSS
WE
A18
A6
A17 83
OE
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VDD
A5
A4
A3
A2
A1
A0
A10
A12
A13
A14
A15
LBO
N.C.
N.C.
VSS
N.C.
N.C.
PIN NAME
SYMBOL A0 - A18 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,44 45,46,47,48,49,50,81 82,83,84,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd or NC VDDQ VSSQ PIN NAME TQFP PIN NO. Power Supply(+3.3V) 14,15,16,41,65,66,91 17,40,67,90 Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs 38,39,42,43 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30
ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
A11
Output Power Supply 4,11,20,27,54,61,70,77 (3.3V or 2.5V) Output Ground 5,10,21,26,55,60,71,76
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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A16
50
NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd
84
81
A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7N163631B(512Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VDD VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC
Jan. 2005 Rev 0.4
K7N163631B K7N161831B
PIN CONFIGURATION(TOP VIEW)
BWb BWa
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
CKE
CS2 N.C.
N.C.
CS2
ADV
CLK
CS1
VDD
VSS
WE
A19
A6
A18 83
OE
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VDD
A5
A4
A3
A2
A1
A0
A12
A13
A14
A15
A16
LBO
N.C.
N.C.
VSS
N.C.
N.C.
PIN NAME
SYMBOL A0 - A19 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,44 45,46,47,48,49,50,80 81,82,83,84,99,100 85 88 89 87 98 97 92 93,94 86 64 31 SYMBOL VDD VSS N.C. PIN NAME TQFP PIN NO. Power Supply(+3.3V) 14,15,16,41,65,66,91 Ground 17,40,67,90 No Connect 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,95,96 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24
ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
A11
DQa0~a8 DQb0~b8
Data Inputs/Outputs Data Inputs/Outputs
VDDQ VSSQ
Output Power Supply 4,11,20,27,54,61,70,77 (3.3V or 2.5V) Output Ground 5,10,21,26,55,60,71,76
NOTE : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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A17
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VDD VDD VDD VSS DQb4 DQb3 VDDQ VSSQ DQb2 DQb1 DQb0 N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7N161831B(1Mx18)
A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VDD VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
Jan. 2005 Rev 0.4
K7N163631B K7N161831B
K7N163631B(512Kx36) 1 A B C D E F G H J K L M N P R
NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC LBO
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)
2
A A NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC NC NC
3
CS1 CS2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
5
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS
6
CS2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0*
7
CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
8
ADV OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL A A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b,c,d) OE ZZ LBO TCK TMS TDI TDO Address Inputs Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs PIN NAME VDD VSS N.C. DQa DQb DQc DQd DQPa~Pd VDDQ Output Enable Power Sleep Mode Burst Mode Control JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output SYMBOL Power Supply Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Output Power Supply PIN NAME
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
K7N161831B(1Mx18) 1 A B C D E F G H J K L M N P R
NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC LBO
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)
2
A A NC DQb DQb DQb DQb VDD NC NC NC NC NC NC NC
3
CS1 CS2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
5
NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS
6
CS2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0*
7
CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
8
ADV OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL A A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b) OE ZZ LBO TCK TMS TDI TDO Address Inputs Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs PIN NAME VDD VSS N.C. SYMBOL Power Supply Ground No Connect PIN NAME
DQa DQb DQPa, Pb VDDQ
Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Output Power Supply
Output Enable Power Sleep Mode Burst Mode Control JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
FUNCTION DESCRIPTION
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
The K7N163631B and K7N161831B are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2) are active . Output Enable(OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time.
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3
(Interleaved Burst, LBO=High)
Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0
Fourth Address
BQ TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3
(Linear Burst, LBO=Low)
Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE READ
READ
BEGIN READ
RE AD DS
ST BUR
BEGIN WRITE
IT WR E DS
WRITE
D REA
DESELECT
DS BURST
BUR ST
WRI TE
DS
DS
BURST
BURST READ
W R IT E
D EA R
BURST WRITE
BURST
COMMAND DS READ WRITE BURST DESELECT BEGIN READ BEGIN WRITE BEGIN READ BEGIN WRITE CONTINUE DESELECT
ACTION
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK)
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H X X X L X L X L X L X X CS2 X L X X H X H X H X H X X CS2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
CLK
ADDRESS ACCESSED N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address
Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock
Notes : 1. X means "Dont Care".
2. The rising edge of clock is symbolized by ().
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H OPERATION READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
WRITE TRUTH TABLE(x18)
WE H L L L L
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
BWa X L H L H
BWb X H L L H
OPERATION READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
ASYNCHRONOUS TRUTH TABLE
OPERATION Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
Notes 1. X means "Dont Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on Any Other Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias Commercial Industrial SYMBOL VDD VIN PD TSTG TOPR TOPR TBIAS RATING -0.3 to 4.6 -0.3 to VDD+0.3 1.6 -65 to 150 0 to 70 -40 to 85 -10 to 85 UNIT V V W C C C C
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS (0C TA 70C)
PARAMETER SYMBOL VDD1 Supply Voltage VDDQ1 VDD2 VDDQ2 Ground VSS MIN 2.375 2.375 3.135 3.135 0 Typ. 2.5 2.5 3.3 3.3 0 MAX 2.625 2.625 3.465 3.465 0 UNIT V V V V V
Notes: 1. The above parameters are also guaranteed at industrial temperature range. 2. It should be VDDQ VDD
CAPACITANCE*(TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested. VIH
SYMBOL CIN COUT
TEST CONDITION VIN=0V VOUT=0V
MIN -
MAX TBD TBD
UNIT pF pF
VSS
VSS-1.0V 20% tCYC(MIN)
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current(except ZZ) Output Leakage Current Operating Current SYMBOL IIL IOL ICC ISB Standby Current ISB1 ISB2 Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) VOL VOH VOL VOH VIL VIH VIL VIH
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
TEST CONDITIONS VDD=Max ; VIN=VSS to VDD Output Disabled, Vout=VSS to VDDQ Device Selected, IOUT=0mA, ZZVIL , Cycle Time tCYC Min Device deselected, IOUT=0mA, ZZVIL, f=Max, All Inputs0.2V or VDD-0.2V Device deselected, IOUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f=Max, All InputsVIL or VIH IOL=8.0mA IOH=-4.0mA IOL=1.0mA IOH=-1.0mA -25 -16
MIN -2 -2 2.4 2.0 -0.3* 2.0 -0.3* 1.7
MAX +2 +2 360 300 170 150 130 0.4 0.4 0.8 VDD+0.3** 0.7 VDD+0.3**
UNIT A A mA mA mA mA V V V V V V V V
NOTES
1,2
3
3
Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. Data states are all zero. 4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
TEST CONDITIONS
PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3/2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load
* The above parameters are also guaranteed at industrial temperature range.
VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.5V VDDQ/2 See Fig. 1
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
Output Load(A)
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Dout 319 / 1667 5pF*
Dout Zo=50
RL=50
353 / 1538
* Including Scope and Jig Capacitance Fig. 1
AC TIMING CHARACTERISTICS
PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE Setup to Clock High Data Setup to Clock High Write Setup to Clock High (WE, BWX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High CKE Hold from Clock High Data Hold from Clock High Write Hold from Clock High (WE, BWX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up SYMBOL tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tCES tDS tWS tADVS tCSS tAH tCEH tDH tWH tADVH tCSH tPDS tPUS -25 MIN 4.0 1.5 1.5 0 1.7 1.7 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 2 2 MAX 2.6 2.6 2.6 2.6 MIN 6.0 1.5 1.5 0 2.2 2.2 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -16 MAX 3.5 3.5 3.0 3.0 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC. The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0C,3.465V) than tHZC, which is a Max. parameter(worst case at 70C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
SLEEP MODE
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SLEEP MODE ZZ active to input ignored CONDITIONS ZZ VIH SYMBOL ISB2 tPDS tPUS tZZI tRZZI 0 2 2 2 MIN MAX TBD UNITS mA cycle cycle cycle
ZZ inactive to input sampled
ZZ active to SLEEP current ZZ inactive to exit SLEEP current
SLEEP MODE WAVEFORM
K
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z
DONT CARE
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z BYPASS SAMPLE RESERVED BYPASS BYPASS TDO Output Boundary Scan Register Identification Register Boundary Scan Register Bypass Register Boundary Scan Register Do Not Use Bypass Register Bypass Register Notes 1 3 2 4 5 6 4 4
SRAM CORE
1 1 1
TDI
BYPASS Reg. Identification Reg. Instruction Reg. Control Signals
TDO
TMS TCK
TAP Controller
NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use.
TAP Controller State Diagram
1 0 Test Logic Reset 0 Run Test Idle
1 1
Select DR 0 Capture DR 0 Shift DR 1
1 1
Select IR 0 Capture IR
1
0
0 1 Shift IR 1 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 0
1
Exit1 DR 0 Pause DR 1 Exit2 DR 1 0 0
1
Update DR 0
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
SCAN REGISTER DEFINITION
Part 512Kx36 1Mx18 Instruction Register 3 bits 3 bits
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
Bypass Register 1 bits 1 bits
ID Register 32 bits 32 bits
Boundary Scan 75 bits 75 bits
ID REGISTER DEFINITION
Part 512Kx36 1Mx18 Revision Number (31:28) 0000 0000 Part Configuration (27:18) 00111 00100 01000 00011 Vendor Definition (17:12) XXXXXX XXXXXX Samsung JEDEC Code (11: 1) 00001001110 00001001110 Start Bit(0) 1 1
165FBGA BOUNDARY SCAN EXIT ORDER(x36)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
NOTE,
165FBGA BOUNDARY SCAN EXIT ORDER(x18)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J 11G 11F 11E 11D 11C 10F 10E 10D 10G 11A 10A 10B 9A 9B 8A 8B 7A 7B LBO NC NC A A A A A A A ZZ NC NC NC NC NC DQa DQa DQa DQa DQa DQa DQa DQa DQa NC NC NC NC A A A A A ADV OE CKE WE CLK NC NC CS2 BWa NC BWb NC CS2 CS1 A A NC NC NC NC NC NC DQb DQb DQb DQb DQb DQb DQb DQb DQb NC NC NC NC A A A A A1 A0 6B 11B 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G 1J 1K 1L 1M 1N 2K 2L 2M 2J 3P 3R 4R 4P 6P 6R 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J 11G 11F 11E 11D 10G 10F 10E 10D 11C 11A 10A 10B 9A 9B 8A 8B 7A 7B
LBO NC NC A A A A A A A ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa DQb DQb DQb DQb DQb DQb DQb DQb DQb NC A A A A ADV OE CKE WE
CLK NC NC CS2 BWa BWb BWc BWd CS2 CS1 A A NC DQc DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd DQd A A A A A1 A0
6B 11B 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G 1J 1K 1L 1M 2J 2K 2L 2M 1N 3P 3R 4R 4P 6P 6R
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
NC ; Dont Care
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
JTAG DC OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage Output Low Voltage Symbol VDD VIH VIL VOH VOL Min 3.135/2.375 2.0/1.7 -0.3 2.4/2.0 -
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
Typ 3.3/2.5 -
Max 3.465/2.625 VDD+0.3 0.8/0.7 0.4/0.4
Unit V V V V V
Note
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Symbol VIH/VIL TR/TF Min 3.0/0 , 2.5/0 1.0/1.0 , 1.0/1.0 VDDQ/2 Unit V ns V Note
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns Note
JTAG TIMING DIAGRAM
TCK
tCHCH tMVCH tCHMX tCHCL tCLCH
TMS
tDVCH tCHDX
TDI
tSVCH tCHSX
PI (SRAM)
tCLQV
TDO
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
TIMING WAVEFORM OF READ CYCLE
tCH tCL
Clock
tCYC tCES tCEH
CKE
tAS
tAH A1 A2 A3
Address
tWS
tWH
WRITE
512Kx36 & 1Mx18 Pipelined NtRAMTM
- 18 -
tCSS
tCSH
CS
tADVS
tADVH
ADV
OE
tOE tLZOE tHZOE Q1-1 tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tHZC Q3-4
Preliminary
Data Out
Jan. 2005 Rev 0.4
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
K7N163631B K7N161831B
TIMING WAVEFORM OF WRTE CYCLE
tCH tCL
Clock
tCES tCEH tCYC
CKE
Address
A1
A2
A3
WRITE
512Kx36 & 1Mx18 Pipelined NtRAMTM
- 19 Jan. 2005 Rev 0.4
CS
ADV
OE
tDS tDH D3-2 D3-3 D3-4
Data In
tHZOE
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
Preliminary
Data Out
Q0-3
Q0-4
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
K7N163631B K7N161831B
TIMING WAVEFORM OF SINGLE READ/WRITE
tCH tCL
Clock
tCES tCEH tCYC
CKE
Address
A1
A2
A3
A4
A5
A6
A7
A8
A9
WRITE
512Kx36 & 1Mx18 Pipelined NtRAMTM
- 20 Jan. 2005 Rev 0.4
CS
ADV
OE
tOE tLZOE
Data Out
Q1 tDS tDH D2
Q3
Q4
Q6
Q7
Preliminary
Data In
D5
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
K7N163631B K7N161831B
TIMING WAVEFORM OF CKE OPERATION
tCH tCL
Clock
tCES tCEH tCYC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
512Kx36 & 1Mx18 Pipelined NtRAMTM
- 21 Jan. 2005 Rev 0.4
CS
ADV
OE
tCD tLZC tHZC Q1 tDS tDH D2 Q3 Q4
Data Out
Preliminary
Data In
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
K7N163631B K7N161831B
TIMING WAVEFORM OF CS OPERATION
tCH tCL
Clock
tCES tCEH tCYC
CKE
Address
A1
A2
A3
A4
A5
WRITE
512Kx36 & 1Mx18 Pipelined NtRAMTM
- 22 Jan. 2005 Rev 0.4
CS
ADV
OE
tOE tLZOE tHZC Q1 Q2 tDS tDH tCD tLZC Q4
Data Out
Preliminary
Data In
D3
D5
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
K7N163631B K7N161831B
PACKAGE DIMENSIONS
100-TQFP-1420A
22.00 0.30 20.00 0.20
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
Units ; millimeters/Inches
0~8 0.127 + 0.10 - 0.05
16.00 0.30 14.00 0.20 0.10 MAX
(0.83) 0.50 0.10 #1 0.65 0.30 0.10 0.10 MAX (0.58)
1.40 0.10 1.60 MAX 0.50 0.10 0.05 MIN
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Jan. 2005 Rev 0.4
K7N163631B K7N161831B
165 FBGA PACKAGE DIMENSIONS
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
A
B
Top View
C D
A F
Side View
E
G
B
Bottom View
H
E
Symbol A B C D
Value 15 0.1 13 0.1 1.3 0.1 0.35 0.05
Units mm mm mm mm
Note
Symbol E F G H
Value 1.0 14.0 10.0 0.5 0.05
Units mm mm mm mm
Note
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Jan. 2005 Rev 0.4

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