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SM5879AV
NIPPON PRECISION CIRCUITS INC.
3rd-order , 2-channel D/A Converter
OVERVIEW
The SM5879AV is a 3rd-order , two-channel D/A convertor LSI for digital audio reproduction equipment. This device incorporate NPC's molybdenumgate CMOS technology and incorporates an 8-times oversampling digital filter and analog 3rd-order post-converter low-pass filters. The SM5879AV also incorporates built-in digital bass boost and deemphasis filters, an attenuator, and soft mute function. Low-voltage operation is also supported. This device features a compact 24-pin VSOP package and a D/A converter that provides both compact size and low power consumption.
PINOUT (TOP VIEW)
DVDD TEST P/M AVDDR RO AVSSR TO1 AVSSL LO AVDDL MUTEO DVSS
1
24
LRCI BCKI DI BB2 / BBON BB1 / MDT DEEM / MCK MUTE / MLEN XVDD XTO XTI XVSS CKO
S M 5 8 7 9 AV
12 13
FEATURES
s s s s s
s
s
s
s
0.65
0.22 +0.1 -0.05
s s
ORDERING INFOMATION
Device SM5879AV Package 24pin VSOP
s s s
NIPPON PRECISION CIRCUITS--1
0.1 0.1
s
2.7 to 3.3 V operating supply voltage 44.1 kHz sampling frequency 16.9344 MHz (384fs) system clock Built-in crystal oscillator circuit 16-bit, MSB first, rear-packed serial data input format ( 64 fs bit clock) 8-times oversampling digital filter * 32 dB stopband attenuation * +0.05 to -0.05 dB passband ripple Deemphasis filter operation * 36 dB stopband attenuation * -0.09 to +0.23 dB deviation from ideal deemphasis filter characteristics Attenuator * 7-bit attenuator (128 steps) set by microcontroller Soft mute function set by parallel setting * (approximately 1024/fs total muting time) Mono setting * Left or right channel mono selectable by microcontroller Built-in infinity-zero detection circuit , two-channel D/A converter * 3rd-order noise shaper * 32fs oversampling Built-in 3rd-order post-converter low-pass filters 24-pin VSOP package Molybdenum-gate CMOS process
PACKAGE DIMENSIONS
Unit: mm
24-pin VSOP
+ 0.05 0.15 - 0.02
7.8 0.1
5.6 0.1 7.6 0.2
1.25 +0.2 -0.1
0 to 10
0.5 0.2
SM5879AV
Theoretical Filter Characteristics
Deemphasis OFF overall characteristics
Frequency band Parameter f Passband ripple Stopband attenuation Built-in analog LPF compensation 0 to 0.4535fs 0.5465fs to 7.4535fs 0.4535fs @ fs = 44.1 kHz 0 to 20.0 kHz 24.1 to 328.7 kHz 20.0 kHz min -0.05 32 - typ - - -0.34 max +0.05 - - Attenuation (dB)
Overall frequency characteristic (deemphasis OFF)
0 10 20
Gain(dB)
30 40 50 60 0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (Fs)
Passband characteristic (deemphasis OFF)
0.0 0.2
Gain(dB)
0.4 0.6 0.8 0.000
0.125
0.250
0.375
0.4535
0.500
Frequency (Fs)
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SM5879AV Deemphasis ON overall characteristics
Frequency band Parameter f Deviation from ideal deemphasis filter characteristics Stopband attenuation Built-in analog LPF compensation 0 to 0.4535fs 0.5465fs to 7.4535fs 0.4535fs @ fs = 44.1 kHz 0 to 20.0 kHz 24.1 to 328.7 kHz 20.0 kHz min -0.09 36 - typ - - -0.34 max +0.23 - - Attenuation (dB)
Overall frequency characteristic (deemphasis ON)
0 10 20
Gain(dB)
30 40 50 60 0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequncy (Fs)
Passband characteristic (deemphasis ON)
0 2 4 6
Gain(dB)
8 10 12 0.000
0.125
0.250
0.375
0.4535
0.500
Frequncy (Fs)
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SM5879AV
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name DVDD TEST P/M AVDDR RO AVSSR TO1 AVSSL LO AVDDL MUTEO DVSS CKO XVSS XTI XTO XVDD MUTE/ MLEN DEEM/ MCK BB1/ MDT BB2/ BBON DI BCKI LRCI I/O II I O O O O O O I O I I I IO I I I Digital supply pin. Input for testing LSI. Test mode when HIGH. Parallel/microcontroller setting selection pin. Parallel setting when HIGH. Right-channel analog supply pin. Right channel analog output pin. Right-channel analog ground pin. Test mode output. Normally LOW. Left-channel analog ground pin. Left-channel analog output pin. Left-channel analog supply pin. Infinity-zero detection output Digital ground pin Oscillator clock output. 16.9344 MHz. Crystal oscillator ground pin Crystal oscillator or 16.9344-MHz external clock input pin Crystal oscillator output pin Crystal oscillator supply pin P/M=H; soft mute control pin. Mute is active when HIGH. P/M=L; microcontroller interface clock P/M=H; deemphasis control pin. Deemphasis is ON when HIGH. P/M=L; microcontroller interface clock P/M=H; bass boost setting switch pin 1 P/M=L; microcontroller interface serial data P/M=H; bass boost setting switch pin 2 P/M=L; bass boost detection output Serial data input pin Bit clock input pin Sample rate clock (fs) input pin. Left channel when HIGH, and right channel when LOW. Description
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SM5879AV
BLOCK DIAGRAM
LRCI BCKI DI
Input interface
P /M MUTE / MLEN DEEM / MCK BB1 / MDT BB2 / BBON
MUTEO
Microcontroller interface
L
R
Filter & attenuation operation block
L R CKO XVSS XTO XTI XVDD
Timing control
DVSS DVDD TEST TO1
PWM data generation block
L
Noise shaper operation block
R
AVDDL
AVDDR
+
-
-
+
LO
AVSSL AVSSR
RO
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SM5879AV
SPECIFICATIONS
Absolute Maximum Ratings
DVSS = AVSSL = AVSSR= XVSS = 0 V, AVDD = AVDDL = AVDDR
Parameter Supply voltage range Input voltage range1 XTI input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol DVDD, AVDD, XVDD VIN1 VIN Tstg PD Tsld tsld Rating -0.3 to 7.0 DVSS - 0.3 to DVDD + 0.3 XVSS - 0.3 to XVDD + 0.3 -55 to 125 250 255 10 Unit V V V C mW C s
1. Pins TEST, P/ M, MUTE/ MLEN, DEEM/ MCK, BB1/ MDT, BB2/ BBON, DI, BCKI, LRCI Also applicable during supply switching.
Recommended Operating Conditions
DVSS = AVSSL = AVSSR = XVSS = 0 V, AVDD = AVDDL = AVDDR
Parameter Supply voltage range Symbol DVDD, AVDD, XVDD DVDD - XVDD, DVDD - AVDD, XVDD - AVDD, DVSS - XVSS, DVSS - AVSS, XVSS - AVSS Topr Rating 2.7 to 3.3 Unit V
Supply voltage variation
0.1
V
Operating temperature range
-20 to 70
C
note) Since DVDD, XVDD, AVDDL, and AVDDR are connected via the LSI base board, current may flow if potential difference occurs among them.
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SM5879AV
DC Electrical Characteristics
Rating Parameter DVDD digital supply current1 XVDD system clock supply current1 AVDD analog supply current1 XTI HIGH-level input voltage XTI LOW-level input voltage XTI AC-coupled input voltage HIGH-level input voltage3 LOW-level input voltage3 HIGH-level output voltage4 LOW-level output voltage4 XTI HIGH-level input current XTI LOW-level input current Input leakage current3 Symbol IDDD IDDX IDDA
2
Condition min - - - Clock input Clock input 0.7XVDD - 0.3XVDD 0.7DVDD - IOH = -0.5mA IOL = 0.5mA VIN = XVDD VIN = 0 V VIN = DVDD VIN = 0V DVDD - 0.4 - - - -1.0 -1.0 typ 3.70 0.55 0.68 - - - - - - - 4 4 - - max 7.40 1.10 1.36 - 0.3XVDD - - 0.3DVDD - 0.4 10 10 1.0 1.0
Unit mA mA mA V V Vp-p V V V V A A A A
VIH1 VIL1 VINAC VIH2 VIL2 VOH VOL IIH1 IIL1 IILH ILL
1. DVDD = AVDD = XVDD = 2.7V, XTI clock input frequency fXTI = 16.9344 MHz, no output load. 2. IDDA is the total current. 3. Pins TEST, P/ M, MUTE/ MLEN, DEEM/ MCK, BB1/ MDT, BB2/ BBON, DI, BCKI, LRCI 4. Pins MUTEO, CKO, BB2/ BBON, TO1
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SM5879AV
AC Electrical Characteristics
System clock (XTI)
Crystal Oscillator
Rating Parameter Oscillator frequency Symbol min fOSC 10.0 typ 16.9344 max 18.5 MHz Unit
External clock input
Rating Parameter HIGH-level clock pulsewidth LOW-level clock pulsewidth Clock pulse cycle Symbol min tCWH tCWL tXI 20.0 20.0 54.0 typ 29.5 29.5 59.0 max 50 50 100 ns ns ns Unit
XTI input clock
t XI VIH1 0.5VDD VIL1
t CWL
t CWH
Serial input (BCKI, DI, LRCI)
Rating Parameter BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth BCKI pulse cycle DI setup time DI hold time Last BCKI rising edge to LRCI edge LRCI edge to first BCKI rising edge Symbol min tBCWH tBCWL tBCY tDS tDH tBL tLB 50 50 6tXI 50 50 50 50 typ - - - - - - - max - - - - - - - ns ns ns ns ns ns ns Unit
Serial input timing
BCKI t BCWH DI t DS LRCI t LB t BL t DH t BCY t BCWL
0.5VDD
0.5VDD
0.5VDD
NIPPON PRECISION CIRCUITS--8
SM5879AV Control input
P/M=H
Rating Parameter Rise time Fall time Symbol min tr tf - - typ - - max 50 50 ns ns Unit
tr
MUTE DEEN BB1 BB2
tr
90% 10% 0.5VDD
90% 10%
Figure 1.
P/M=L
Rating Parameter MCK LOW-level pulsewidth MCK HIGH-level pulsewidth MCK pulse width MDT setup time MDT hold time MLEN setup time MLEN hold time Rise time Fall time Symbol min tMCWL tMCWH tMcy tMDS tMDH tMLH tMLW tr tf 200 200 400 100 100 100 200 - - typ - - - - - - - - - max - - - - - - - 50 50 ns ns ns ns ns ns ns ns ns Unit
MCK
t MCWH t MCY MDT t MDS t MDH t MCWL
0.5VDD
0.5VDD
MLEN t MLS t MLW t MLH
0.5VDD
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SM5879AV
AC Analog Characteristics
DVSS = AVSSL= AVSSR = XVSS = 0 V, DVDD = AVDDL = AVDDR = XVDD = 2.7V, P/M=2.7V, MUTE=0V, DEEM=0V, BB1=2.7V, BB2=2.7V, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 C
Rating Parameter Total harmonic distortion LSI output level Evaluation board output level Dynamic range Signal-to-noise ratio1 Channel separation Symbol THD + N Vout1 Vout2 D.R S/N Ch. Sep Condition min 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, -60 dB 1 kHz, 0/- dB 1 kHz, -/0 dB - 0.65 - 86.0 86.0 80.0 typ 0.0075 0.70 0.70 91.0 91.5 87.0 max 0.015 0.75 - - - - % Vrms Vrms dB dB dB Unit
1. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise.
AC Measurement Circuit and Conditions
Measurement circuit block diagram
CKO(384fs)
Signal Generator
BCK LRCK(fs) DATA
Left Channel
Evaluation L/R Channel Board Selector Right Channel
Distortion Analyzer
fs= 44.1kHz DATA= 16bit
10k Input Impedance NF Corporation 3346A
RMS Measurement Shibasoku AD725C
Measurement conditions
Parameter1 Total harmonic distortion Output level Dynamic range Signal-to-noise ratio Symbol THD + N Vout DR S/N D-RANGE THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF JIS A filter ON 20 kHz lowpass filter ON 400 Hz highpass filter OFF 3346A left/right-channel selector switch THRU AD725C distortion analyzer with built-in filter 20 kHz lowpass filter ON 400 Hz highpass filter OFF
Channel separation
Ch. Sep
THRU
1. Pins LO and RO should have an output load of 10 k (min).
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100p 220p 33k 22k 33u 33u 33k -+ 10p 10p 0.01u 33u + 1500p 33u + + 0.1u -+ 16.9344MHz 1 +100k 100p 5.6k 6.8k 2.2u 2 NJM 2100D +4 3 22k 8 6 NJM 2100D + 5 22k 33u 22k
5.6k
Measurement circuit
BBON
100
L OUT
MUTEO
CKO
VCC
100p 5.6k 220p 33k 22k 33u 33u 33k -+ 6 NJM
2100D
LRCI
MDT
SM5879AV
MCK
470u
+
LRCI
DVSS CKO XVSS MUTEO XTI AVDDL XTO LO AVSSL XVDD MUTE/MLEN TO1 DEEM/MCK AVSSR BB1/MDT RO BB2/BBON AVDDR DI P/M BCKI TEST
SM5879
DVDD
BCKI
VEE
DI
MLEN
22k
0.01u
5.6k 4 1500p
6.8k + 33u
8 2 NJM
2.2u
2100D
100 + 3 22k 33u + 0.1u +100p 100k
0.01u 0.01u 33u 100u -+ + 5 22k
100u
-+ AVDD AVSS TO1
NIPPON PRECISION CIRCUITS--11
+
DVSS DVDD
-+
R OUT
SM5879AV
FUNCTIONAL DESCRIPTION
System Clock
Note that the input clock accuracy and jitter greatly influence the AC analog characteristics. The system clock can be controlled by a crystal oscillator consisting of a crystal connected between XTI and XTO and a built-in CMOS invertor or, alternatively, an external system clock. Since the built-in CMOS invertor has a feedback resistor, the external system clock can be AC coupled to XTI. The system clock is output from CKO.
System Reset (RSTN)
System reset for SM5879AV is performed by a builtin power ON reset circuit. At system reset, the internal arithmetic operation and output timing counter are synchronized with the next LCRI rising edge and thereby reset again for synchronization with external elements. Analog output is muted by this resetting, and muting is cleared by the ninth LCRI rise (See Figure 1). However, noise is generated due to the change in PWM output during a timing reset. An external mute circuit is necessary to prevent this noise.
Power on Switch
1 2 3 9 10
LRCI
Internal Reset
LO RO
Output Muted
Figure 2. System reset timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2scomplement, 16-bit serial format. Serial data bits are read into the SIPO register (serialto-parallel converter register) on the rising edge of the bit clock BCKI. The bit clock frequency on BCKI should be between 32fs and 64fs.
1 / fs LRCI BCKI (MAX64fs) DI Lch MSB 16bit LSB Rch MSB 16bit LSB
Figure 3.
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SM5879AV
Selection and Setting of Functions
SM5879AV offers a variety of functions. Fundamentally, there are two methods available for selecting and setting these functions. One method is using an external input pin; this is called parallel setting. The other method is by using the microcontroller interface, which is called microcontroller setting.
Table 1. Selection and Setting of Functions
Function Setting Methods Function Parallel setting Related external pin name (When P/M is HIGH) BB1, BB2 None DEEM MUTE None None Microcontroller setting Related flag (When P/M is LOW) FBB1, FBB2 Output to BBON FDEM None (Enabled by attenuator) 7 bits (A6 - A0) MONO, CSEL Notes
Microcontroller interface refers here to serial data transfer from the microcontroller using the three pins MDT, MCK, and MLEN. These two methods of setting and selection are set by the P/M pin. When P/M is HIGH, parallel setting is used. When P/M is LOW, microcontroller setting is used.
Bass boost Bass boost detection output Deemphasis filter Soft mute Attenuator setting Monaural setting
Bass boost Bass boost detection output Deemphasis filter Soft mute Attenuation Stereo/mono output setting
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SM5879AV
Microcontroller Interface
For microcontroller setting (when P/M is HIGH), the microcontroller interface consisting of MDT (data), MCK (clock) and MLEN (latch enable) can be used. Data from the microcontroller is input to the inputstage shift registers at the rise of MCK. Changes in MDT should be performed at the rise of MCK. Serial data in the shift registers is latched in parallel to the flag registers at the rise of MLEN. Two flag registers are available, divided into the attenuation factor and mode flag by the D7 data.
MLEN MCK MDT D0 D1 D2 D3 D4 D5 D6 D7
Figure 4. Format of microcontroller interface input
Table 2. microcontroller setting flags
Microcontroller serial data D7 D6 D5 D4 D3 D2 D1 D0 0 A6 A5 A4 A3 A2 A1 A0 Flag 1 FDEM FBB1 FBB2 MONO CSEL -
A0 to A6: Attenuation factor (A6: MSB) FDEM: Deemphasis ON/OFF (ON when 1) FBB1: Bass boost setting switch flag 1 FBB2: Bass boost setting switch flag 2 MONO: Stereo/mono setting (Mono when 1) CSEL: Mono output channel selection (Right channel when 1)
NIPPON PRECISION CIRCUITS--14
SM5879AV
Bass Boost
Two types of bass boost and gain modification can be set by either parallel or microcontroller.
Table 3.
Parallel setting pin name Microcontroller setting flag BB1 BB2 Mode FBB1 H H L L FBB2 H L H L Flat 1 Bass boost MIN Bass boost MAX Flat2
3 2 1 0 Boost (dB) -1 -2 -3 -4 -5 -6 -7 -8 Flat2 (-8dB)
4 5
Max. Chrasteristic
Flat1 (0dB)
Min. Charasteristic
-9 10
100
1000 Frequency (Fs)
10
10
Figure 5. Bass boost mode frequency response
Bass boost detection output
With microcontroller setting (when P/M is LOW), the 21st pin is the BBON output pin and functions as output that detects the bass boost mode.
Table 4.
Microcontroller setting flag BB1 H H L L BB2 H L H L Mode Flat 1 Bass boost MIN Bass boost MAX Flat 2 BBON pin L H H H
BBON output is LOW when the bass boost mode is set to Flat 1 and HIGH in all other cases.
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SM5879AV
Deemphasis filter
The built-in deemphasis filter in the SM5879AV operates at fs = 44.1 kHz.
Table 5.
Parallel setting pin name Microcontroller setting flag DEEM Deemphasis mode FDEM H L ON OFF
Soft Mute
With parallel setting (when P/M is HIGH), soft mute can be activated by the MUTE pin level setting using the built-in attenuation counter. When muting is activated, MUTE is HIGH. When soft mute is activated, the attenuation counter operates and lowers gain in 128 steps. The time until mute is activated is approximately 1024/fs 23.2 msec. The time required to release muting is the same.
MUTE
0dB (Gain) - 1024/fs 1024/fs
Figure 6. Example of soft mute operation
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SM5879AV
Attenuation
The SM5879AV loads the attenuation factor with serial data by means of the microcontroller interface, thus enabling attenuation operation.
MLEN MCK MDT A0 A1 (LSB) D0 D1 A2 D2 A3 D3 A4 D4 A5 D5 A6 (MSB) D6 0 D7
Figure 7. Method of setting the attenuation factor The attenuation computation is performed by multiplying the output of the internal 7-bit UP/DOWN counter output data by the signal data. When the conL channel DATTGain = 20 x log --------------- [dB] 127 R channel DATTGain = 20 x log --------------- [dB] 127 When DATT = 0, this becomes -. When the attenuation factor is changed, it is smoothly changed from the previous setting until it reaches the value of the new setting as expressed by the above equations. The time required to change gain is approximately 1024 fs 23.2 msec when the time required to change one step of the attenuation factor is approximately 8 / fs 181.4 sec over the range 0 dB to -. tents of the counter are DATT, gain can be expressed by the following equations.
Setting1 Setting5 Setting3
(Gain)
Setting2 Setting4 Time
Figure 8. Example of attenuation gain
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SM5879AV
Stereo/Mono Output Setting
Mono output can be set via the microcontroller (when P/M is HIGH).
Table 6.
Microcontroller setting flag MONO H H L L CSEL H L H Stereo L Output R channel L channel
Infinity-Zero Detection Output
HIGH level is output from the infinity-zero detection output pin in the following cases with the SM5879AV. (1) From the time that power ON is reset until the first data comes in. (2) When the LOW level space of the DI pin has continued for 214x (1/fs) 0.37 [sec] or more.
214/fs
1 2 3 9
LRCI DI RSTN MUTEO Internal Status
Initialize Signal No Signal Signal
Figure 9.
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SM5879AV
TIMING DIAGRAMS
Input Timing (DI, BCKI, LRCI)
1 / fs LRCI BCKI (MAX64fs) DI Lch MSB 16bit LSB Rch MSB 16bit LSB
TYPICAL APPLICATIONS
Input Interface Circuits
Normal Speed
X'tal (16.9344MHz)
XTAI
16.9344MHz 44.1kHz 2.1168MHz
XTI CKO LRCI DI BCKI
XTO
SONY CXD2500
PSSL
LRCK DA16 DA15
SM5879
NIPPON PRECISION CIRCUITS--19
SM5879AV
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9702BE 1997.11
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS--20

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