View AS998_386877.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AS998/A PWM Controller
SEMICONDUCTOR
Preliminary Specification
Description
The AS998/AS998A is an IC intended for use as a PWM controller for switch mode power supplies. The device is particularly suited as a primary side controller for adapter, printer, peripheral, mobile chargers and desktop auxiliary power supplies. The AS998/AS998A is manufactured in BICMOS technology and exhibits very low start-up and operating power. This allows the device to be suitable in applications where stringent standby or Blue Angel criteria are required. Many of the external functions associated with PWM controllers have been integrated into the AS998/AS998A allowing the external component count to be significantly reduced. Features such as fixed internal oscillator, internal ramp compensation and current filters all reduce the external support components.
Features
* * * * * * * * * * * Low start-up current 64 A (Typ) Low running current 2 mA (Typ) Low power light load mode Low power standby when OV is activated Extended commercial operating temperature range: 0 to 105C On-board fixed frequency oscillator 100 kHz (Typ) Frequency randomizer to reduce EMC emissions Dedicated OV shutdown pin On-board voltage ramp compensation On-board current sensing filtering Optional primary side regulation
Pin Configuration -
Top View
OV Comp VFB
LI
VREG
8L PDIP (8N)
1 2 3 4
M
8L SOIC (8D)
OV Comp VFB ISENSE
1 2 3 4 8 7 6 5 8 7 6 5
IN
VREG VCC OUT GND VCC OUT GND
ISENSE
P
Ordering Information
AS998/A B 8D N
Packaging Option: T = Tubes N = Tape and Reel (13" Reel Dia.) Package Type: 8D = 8 Pin, Plastic SOIC 8N = 8 Pin, Plastic DIP
Circuit Type: PWM Controller (Models AS998 & AS998A) Temperature Range: B = 0C to 105C
www.ptcc.com.tw
R
E
233
A
The AS998/AS998A has a typical output rise and fall time of 250/210 ns.
R
Y
P
Vcc on chip power Bias P Bias N I-bias
AS998/AS998A
www.ptcc.com.tw
Vdd
Power Management
R
Internal Power & Reference PTAT Generator Bandgap Reg > 14 (OverVolt) > 10 (Turn On) > 6.5 (Turn Off) Vcc OSC Dither Fout
Functional Block Diagram
Gnd
E
Ref 1 2 3 OSC Vramp 75% Duty Cycle Vcc Attenuator + + LPF RC=3E-7
Comp 1
Vcc
OV
Temp Comp Current Source Ref 1 Current Conveyor Vcc Vcc S
LI
Output Driver SET Q
234
Vcc Ref 3
Comp 2
Vdd
M IN
R
Out
FB
CLR Q
Comp
A
CSNS
R
Y
PWM Controller
PWM Controller
Pin Function Description
Pin Number Function 1 OV Description
AS998/AS998A
Overvoltage pin. The OV input/output function is implemented by an on-chip latch. This pin is driven to the Reg voltage if the on-chip circuitry senses a VDD level greater than the OV threshold (VDDov). This error condition stops the part from generating any more output pulses until VDD has been reduced to the VDDul level and then raised as in a normal power-on sequence. Alternatively, the OV error condition can be cleared by forcing the OV pin to near ground. The output is immediately enabled following an OV clear function. The OV error condition can also be generated externally by temporarily forcing the OV pin to a voltage greater than the VOV threshold. This will force the part to latch an tion and not generate any more output pulses unless cleared as
2
COMP
4
CSNS
Current sense input. The signal on this pin is fed via a low pass filter to the PWM com-parator. Superimposed on the input to the PWM is a slope compensation ramp derived from the main oscillator. In addition to the above, the current sense signal is connected directly to an overcurrent comparator that detects an overload condition and immediately terminates the gate drive pulse with a minimum propagation delay.
5 6
GND OUT
7
VDD
P
8
R
REG
www.ptcc.com.tw
E
LI
Circuit common ground.
Gate drive output. The current source and sink capability of the output buffer is tailored to minimize EMI. When the IC is not running, this pin is held low so a pull down resistor on the FET gate is not required.
Positive supply voltage. An on-board shunt regulator allows this IC to be powered via a simple resistor from a widely varying bias supply. The ICs power management block keeps the part in startup current mode while VDD is ramping up until the part turns on at the UVLhigh threshold. The IC then draws the specified supply current while operating unless VDD drops below the UVLlow threshold. If VDD drops below UVLlow, then the part will return to startup current mode. Voltage regulator. Decoupling pin as required for internal low voltage supply. This pin may be used to source 1mA for the control optocoupler.
M
IN
235
3
FB
Feedback pin. Inverting input to the error amplifier. This pin is tied to an internal default divider which will tend to regulate VDD at a nominal 11V.
A
Compensation pin. This pin is the output of the error amplifier and can also be used as an input for an optocoupled control signal to the PWM comparator. Generally this pin is connected to a feedback network to FB. If an optocoupler feedback is used, COMP connects to the collector of the common emitter optocoupler, generally with a pull-up resistor to VDD or Reg.
R
OV condidescribed.
Y
AS998/AS998A
IC Block Diagram Description
Power Management
PWM Controller
This block contains reference generators and comparators to determine the under-voltage shutdown point, the power-on point, the primary regulation operating point, and the overvoltage shutdown point. Internal Power / Reference This block includes a course regulator for on-chip power and cascade voltages for HV circuitry, a bandgap for comparator references, a bias current generator, PTAT, BiasP and BiasN. Temperature Compensated Current Source This block generates a constant current as a function of voltage and temperature with no off-chip components. Oscillator
Feedback Control
This block senses one of the various feedback methods to control the output duty cycle. It includes a current sense, a low pass filter, current amplifier, summing amp, and comparators. This block sums the analog ramp from the OSC, sense, and compensation node voltages into a comparator which triggers the falling edge of the PWM clock signal. This provides supply voltage compensation and load regulation to the power converter system. Out_Drv
Absolute Maximum Ratings
Supply Voltage (Low Impedance Source)
E
Rating
LI
A high speed, high current bipolar output stage capable of providing approximately 500 mA sink and 250 mA source current to charge and discharge the gate of a large power FET. It is understood that the total delay from the comp pin to the output pin should be about 100 ns.
M
IN
VDD IDD IOUT IREG PD TJ TL
Symbol
A
TSTG
Mirrored currents from the reference block are used to charge a capacitor to the threshold voltage at which point the direction is switched to an opposing 3X mirror to drive the capacitor to a lower threshold value. This generates a 75% duty cycle digital clock to the output latch, and a 100kHz ramp voltage to be used in the feedback control.
R
Rating 13 15 600 10 750 1000 150 300
Y
Unit V mA mA mA mW mW C C C
Output Peak Current Regulator Current
P
Continuous Power at 25C
R
Supply Current (High Impedance Source)
8L SOIC 8L PDIP
Junction Temperature Storage Temperature Lead Temperature, Soldering 10 Seconds
- 65 to 150
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
www.ptcc.com.tw
236
PWM Controller
Electrical Characteristics
AS998/AS998A
Electrical Characteristics are guaranteed over full junction temperature range (0 to 105C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are VDD = 12 V; OV = 0V, CSNS = 0V. Cload = 1800pf, Creg = 100 nf (AVVD to GND). To start chip, Vdd must be raised above UVLhigh. Parameter Startup Current Supply Current Startup Threshold UVL off Threshold Bias Current at POS Int Regulator Voltage Oscillator Parameter Mean Period Symbol TOSC TREP TDEV DMAX Symbol RFB VDDREG VREF GBP AVOL Test Condition Symbol IDDO IDD UVLHIGH UVLLOW VCLAMP VREG IDD = 10mA No Load IREG = 1mA Test Condition UVLHIGH Threshold No Load AS998 AS998A 1 9 9.5 7.6 13 5.5 Min. Typ. 64 2 10 10 8 14 Max. 100 4 11 10.5 8.4 7.0 14.7 Unit A mA V V V V V
R
Min. 7.3
Y
6.25 Typ. 9.3 9.3 15 16.5 75 Typ. 100 12 2.5 85 10 100 50 300 Typ. 0.4 100 320 700
Max. 11.7 10.7
Unit s s cycles
8.4V < VDD < 13.3V; 15 cycle avg. - AS998
8.4V < VDD < 13.3V; 15 cycle avg. - AS998A Peak-to-Peak Modulation Max. Duty Cycle Error Amplifier Parameter FB Divider R VDD Regulation Point FB Threshold Gain (DC) Gain-Bandwidth Product COMP Output High COMP Output Low Peak-to-Peak change in period
IN
237
Modulation Repetition Rate
A
8.1
13.7 70
23 78
% %
M
Test Condition
Min.
Max.
Unit k
11.4 2.37
12.6 2.62
V V dB MHz V
LI
VCOMPH VCOMPL ICOMPH
COMP = FB, VDD = 12V No load on COMP No load on COMP
E
FB = 2V FB = 3V COMP = 3V, FB = 2V COMP = 1V, FB = 3V
4.5 250 100 500
mV A A
COMP Source Current COMP Sink Current
25 25
R
ICOMPL Symbol
Current Sense Comparator Parameter Test Condition to CSNS input RCSAC FCS tpd1 Fin FCO Time Constant Min. Max. Unit
P
Scaling of COMP AC Input Impedance Input Filter Prop. Delay to Output
k ns ns
www.ptcc.com.tw
AS998/AS998A
Electrical Characteristics
Over Current Comparator Parameter Comparator Threshold Propagation Delay to Output Symbol VCSTH tpd2 Test Condition COMP = 1V, FB = 3V FB = 2, Vcs step to 1.65V, from 50% point on CSNS input to 90% point on output H to L transistion Min. (cont.)
PWM Controller
Typ. 1.25 100
Max. 150
Unit V ns
Over Voltage Input
OV VDD Threshold OV Threshold OV Latch State Low OV Latch State High OV Hi Impedance Pull-up OV Unlatch Threshold Output Parameter Max. "Off State" Voltage Output Rise Time Output Fall Time
VDDOV VOV OVRN OVRP OVHI VDDUL Symbol VOFF tr tf
Forcing VDD pin Forcing OV pin OV = Reg - 1V, Equiv. R to Reg OV = 1V, Equiv. R to Gnd OV = 1V, IDD = 10mA VDD dropped until latch fails
13
Y
14 14.7 3.5 8 16 16 1 5.25 8 0.3 5 Typ. 1.7 250 210 290 240
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit V V k k A V
Test Condition IOUT = 100A
IN
238
A
4.75 Min. 170 140
R
4 4
Max.
Unit V ns ns
T = 25C, 10% - 90%
www.ptcc.com.tw
P
R
E
LI
M
T = 25C, 10% - 90%

▲Up To Search▲

Price & Availability of AS998

	To Download AS998 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .