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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT20 Dual 4-input NAND gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual 4-input NAND gate FEATURES * Output capability: standard * ICC category: SSI GENERAL DESCRIPTION 74HC/HCT20 The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi fo = input frequency in MHz = output frequency in MHz PARAMETER propagation delay nA, nB, nC, nD to nY input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 8 3.5 22 HCT 13 3.5 17 ns pF pF UNIT CL = output load capacitance in pF VCC = supply voltage in V (CL x VCC2 x fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". December 1990 2 Philips Semiconductors Product specification Dual 4-input NAND gate PIN DESCRIPTION PIN NO. 1, 9 2, 10 3, 11 4, 12 5, 13 6, 8 7 14 SYMBOL 1A, 2A 1B, 2B n.c. 1C, 2C 1D, 2D 1Y, 2Y GND VCC NAME AND FUNCTION data inputs data inputs not connected data inputs data inputs data outputs ground (0 V) positive supply voltage 74HC/HCT20 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Dual 4-input NAND gate 74HC/HCT20 Fig.4 Functional diagram. Fig.5 HC logic diagram (one gate). FUNCTION TABLE INPUTS nA L X X X H Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care Fig.6 HCT logic diagram (one gate). nB X L X X H nC X X L X H nD X X X L H OUTPUT nY H H H H L December 1990 4 Philips Semiconductors Product specification Dual 4-input NAND gate DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay nA, nB, nC, nD to nY output transition time typ. 28 10 8 19 7 6 max. 90 18 15 75 15 13 -40 to +85 min. max. 115 23 20 95 19 16 -40 to +125 min. max. 135 27 23 110 22 19 ns UNIT 74HC/HCT20 TEST CONDITIONS VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS Fig.7 tTHL/ tTLH ns Fig.7 December 1990 5 Philips Semiconductors Product specification Dual 4-input NAND gate DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI Note to HCT types 74HC/HCT20 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT nA, nB, nC, nD UNIT LOAD COEFFICIENT 0.3 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. tPHL/ tPLH tTHL/ tTLH propagation delay nA, nB, nC, nD to nY output transition time typ. 16 7 max. 28 15 -40 to +85 min. max. 35 19 -40 to +125 min. max. 42 22 ns ns 4.5 4.5 Fig.7 Fig.7 UNIT VCC (V) WAVEFORMS TEST CONDITIONS AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the enable input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 6 |
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