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| (R) USBLC6-4SC6 VERY LOW CAPACITANCE ESD PROTECTION ASD (Application Specific Devices) MAIN APPLICATIONS USB2.0 ports up to 480Mb/s (high speed) Backwards compatible with USB1.1 low and full speed Ethernet port: 10/100Mb/s SIM card protection Video line protection Portable electronics DESCRIPTION The USBLC6-4SC6 is a monolithic Application Specific Discrete dedicated to ESD protection of high speed interfaces, such as USB2.0, Ethernet links and Video lines. Its very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized ESD strikes. FEATURES 4 data lines protection Protects VBUS Very low capacitance: 3pF typ. SOT23-6L package RoHS compliant BENEFITS Very low capacitance between lines to GND for optimized data integrity and speed Low PCB space consuming, 9mm maximum foot print Enhanced ESD protection IEC61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS. Allows ESD current flowing to Ground when ESD event occurs on data line High reliability offered by monolithic integration Low leakage current for longer operation of battery powered devices Fast response time Consistent D+ / D- signal balance: - Best capacitance matching tolerance I/O to GND = 0.015pF - Compliant with USB 2.0 requirements < 1pF SOT23-6L Figure 1: Functional Diagram I/O1 1 6 I/O4 GND 2 5 VBUS I/O2 3 4 I/O3 Table 1: Order Code Part Number USBLC6-4SC6 Marking UL46 COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 level4: 15kV (air discharge) 8kV (contact discharge) February 2005 REV. 2 1/10 USBLC6-4SC6 Table 2: Absolute Ratings Symbol VPP Tstg Tj TL Parameter At device level: IEC61000-4-2 air discharge IEC61000-4-2 contact discharge MIL STD883C-Method 3015-6 Value 15 15 25 -55 to +150 125 260 Unit Peak pulse voltage kV Storage temperature range Maximum junction temperature Lead solder temperature (10 seconds duration) C C C Table 3: Electrical Characteristics (Tamb = 25C) Symbol VRM IRM VBR VF Parameter Reverse stand-off voltage Leakage current Breakdown voltage between VBUS and GND Forward voltage VRM = 5V IR = 1mA IR = 10mA IPP = 1A, tp = 8/20s Any I/O pin to GND IPP = 5A, tp = 8/20s Any I/O pin to GND 3 0.015 Capacitance between I/O VR = 1.65V 1.85 0.04 2.7 pF 6 0.86 12 17 4 pF Test Conditions Value Min. Typ. Max. 5 2 Unit V A V V V V VCL Clamping voltage Ci/o-GND Ci/o-GND Ci/o-i/o Ci/o-i/o Capacitance between I/O and GND VR = 1.65V 2/10 USBLC6-4SC6 Figure 2: Capacitance versus voltage (typical values) C(pF) 5.0 4.5 4.0 3.5 CO=I/O-GND F=1MHz VOSC=30mVRMS Tj=25C Figure 3: Line capacitance versus frequency (typical values) C(pF) 5.0 4.5 VCC=0V VOSC=30mVRMS Tj=25C 4.0 3.5 VCC=1.65V 3.0 2.5 Cj=I/O-I/O 3.0 2.5 2.0 1.5 1.0 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Data line voltage (V) 0.5 0.0 1 10 F(MHz) 100 1000 Figure 4: Relative variation of leakage current versus junction temperature (typical values) IRM[Tj] / IRM[Tj=25C] 100 VBUS=5V Figure 5: Frequency response 0.00 USBLC6-4SC6 (50) S21(dB) -5.00 10 -10.00 -15.00 Tj(C) 1 25 50 75 100 125 -20.00 100.0k 1.0M 10.0M F(Hz) 100.0M 1.0G 3/10 USBLC6-4SC6 TECHNICAL INFORMATION 1. SURGE PROTECTION The USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VBUS + VF for positive surges VCL- = - VF for negative surges with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 1.4 and VT = 1.2V. For an IEC61000-4-2 surge Level 4 (Contact Discharge: Vg=8kV, Rg=330), VBUS = +5V, and if in first approximation, we assume that : Ip = Vg / Rg = 24A. So, we find: VCL+ = +39V VCL- = -34V Note: the calculations do not take into account phenomena due to parasitic inductances. 2. SURGE PROTECTION APPLICATION EXAMPLE If we consider that the connections from the pin VBUS to VCC and from GND to PCB GND are done by two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the voltage VCL has an extra value equal to Lw.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : VCL+ = +39 + 144 = 183V VCL- = -34 - 144 = -178V We can reduce as much as possible these phenomena with simple layout optimization. It's the reason why some recommendations have to be followed (see paragraph "How to ensure a good ESD protection"). Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout VCL+ 183V ESD SURGE VBUS Lw +VCC VF Lw di dt Lw di dt POSITIVE SURGE VCC+VF I/O tr=1ns t VI/O Lw di dt di VCL+ = VBUS+VF+Lw dt surge >0 di surge <0 VCL- = -VF-Lw dt tr=1ns t -VF -Lw di dt NEGATIVE SURGE GND -178V VCL- 4/10 USBLC6-4SC6 3. HOW TO ENSURE A GOOD ESD PROTECTION While the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the power supply +VCC and from the VBUS pin to GND must be as short as possible to avoid overvoltages due to parasitic phenomena (see figure 6). It's often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the ground plane that allows a short connection. To ensure the same efficiency for positive surges when the connections can't be short enough, we recommend to put close to the USBLC6-4SC6, between VBUS and ground, a capacitance of 100nF to prevent from these kinds of overvoltage disturbances (see figure 7). The add of this capacitance will allow a better protection by providing during surge a constant voltage. The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations described above. Figure 7: ESD behavior: optimized layout and add of a capacitance of 100nF Figure 8: ESD behavior: measurements conditions (with coupling capacitance) ESD SURGE VCL+ ESD SURGE Lw REF2=+VCC C=100nF t TEST BOARD USBLC6-4SC6 POSITIVE SURGE I/O VCL+ = VCC+VF surge >0 VI/O t +5V VCL- = -VF surge <0 NEGATIVE SURGE REF1=GND VCL- C=100nF Figure 9: Remaining voltage after the USBLC6-4SC6 during positive ESD surge Figure 10: Remaining voltage after the USBLC6-4SC6 during negative ESD surge IMPORTANT: A main precaution to take is to put the protection device closer to the disturbance source (generally the connector). Note: The measurements have been done with the USBLC6-4SC6 in open circuit. 5/10 USBLC6-4SC6 4. CROSSTALK BEHAVIOR 4.1. Crosstalk phenomena Figure 11: Crosstalk phenomena RG1 Line 1 1 VG1 + 12VG2 VG1 RG2 Line 2 RL1 VG2 RL2 2VG2 + 21VG1 DRIVERS RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k). Figure 12: Analog crosstalk measurements TRACKING GENERATOR TEST BOARD USBLC6-4SC6 SPECTRUM ANALYSER 50 +5V Vg 50 Vin C=100nF Vout Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13). Figure 13: Analog crosstalk results USBLC6-4SC6 Aplac 7.70 User: ST Microelectronics Oct 29 2004 0.00 dB -30.00 -60.00 As the USBLC6-4SC6 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (figure 5) gives attenuation information and shows that the USBLC6-4SC6 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900MHz) frequencies, for instance. -90.00 -120.00 100.0k 1.0M 10.0M f/Hz 100.0M 1.0G 6/10 USBLC6-4SC6 5. APPLICATION EXAMPLES Figure 14: USB2.0 port application diagram using USBLC6-4SC6 + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS - + 5V USB connector Protecting Bus Switch HUBDOWNSTREAM TRANSCEIVER SW1 VBUS D+ DRS RS RPD USBLC6-2SC6 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - GND RS RS RPD GND TX LS/FS + TX LS/FS - + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS - SW1 USB connector VBUS D+ DRS RS USBLC6-2P6 RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - GND RS GND TX LS/FS + USBLC6-4SC6 RPD RS RPD TX LS/FS - Mode Low Speed LS Full Speed FS High Speed HS SW1 Open Closed SW2 Closed Open Closed then open Open Figure 15: T1/E1/Ethernet protection Tx SMP75-8 USBLC6-4SC6 +VCC 100nF DATA TRANSCEIVER Rx SMP75-8 7/10 USBLC6-4SC6 6. PSPICE MODEL Figure 16 shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined by the PSPICE parameters given in figure 17. Figure 16: PSPICE model Lbo ndso t 23 100 m Lpinsot 23 Lvc c Rvc c Vcc MODEL = Dhigh io1 io2 io3 io4 Lpinsot 23 Lpinsot 23 Lpinsot 23 Lpinsot 23 Lbo ndso t 23 100 m Lbo ndso t 23 100 m Lbo ndso t 23 100 m Lbo ndso t 23 100 m MODEL = Dhigh MODEL = Dhigh MODEL = Dhigh MODEL = Dzener MODEL = Dlow MODEL = Dlow MODEL = Dlow MODEL = Dlow Lbo ndso t 23 100 m Lpi nsot 23 Lgn d Rgn d Lbo ndso t 23 100 m Note: This simulation model is available only for an ambient temperature of 27C. Figure 17: PSPICE parameters Figure 18: USBLC6-4SC6 considerations PCB layout Dlow BV CJ0 IBV IKF IS ISR N M RS VJ TT 50 2.4p 1m 0.038 55.2p 100p 1.62 0.3333 0.38 0.6 0.1u Dhigh 50 2.4p 1m 0.018 2.27f 100p 1.13 0.3333 0.63 0.6 0.1u Dzener 7.3 20p 1m Lbondsot23 Lpinsot23 Rgnd 0.564n 0.15n D+1 350m 100p 350m 100p 1 2.42 3.21p 100p 1.24 0.3333 0.42 0.6 0.1u Rvcc Lvcc Lgnd D-1 GND D+2 D-2 VBUS CBUS = 100nF USBLC6-4SC6 8/10 USBLC6-4SC6 Figure 19: SOT23-6L Package Mechanical Data A E DIMENSIONS REF. A Millimeters Min. 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 0 3.00 0.102 0.60 0.004 10 0 Typ. Max. 0.10 Min. 0 1.45 0.035 1.30 0.035 0.50 0.014 0.20 0.004 3.05 0.110 1.75 0.059 0.037 0.118 0.024 10 Inches Typ. Max. 0.057 0.004 0.051 0.02 0.008 0.120 0.069 e B e D A1 A2 b C A2 D E e c A1 H L L H Figure 20: Foot Print Dimensions (in millimeters) 0.60 1.20 0.95 3.50 2.30 1.10 Table 4: Ordering Information Ordering code USBLC6-4SC6 Marking UL46 Package SOT23-6L Weight 16.7 mg Base qty 3000 Delivery mode Tape & reel Table 5: Revision History Date 10-Dec-2004 28-Feb-2005 Revision 1 2 First issue. Minor layout update. No content change. Description of Changes 9/10 USBLC6-4SC6 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10 |
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