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19-2597; Rev 0; 8/03
16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range
General Description
The MAX1177 is a 16-bit, low-power, successiveapproximation analog-to-digital converter (ADC) featuring automatic power-down, a factory-trimmed internal clock, and a byte-wide parallel interface. The device operates from a single +4.75V to +5.25V analog supply and features a separate digital supply input for direct interface with +2.7V to +5.25V digital logic. The MAX1177 accepts an analog input voltage range from 0 to +10V. It consumes no more than 26.5mW at a sampling rate of 135ksps when using an external reference, and 31mW when using the internal +4.096V reference. AutoShutdownTM reduces supply current to 0.4mA at 10ksps. The MAX1177 is ideal for high-performance, batterypowered, data-acquisition applications. Excellent AC performance (THD = -100dB) and DC accuracy (3 LSB INL) make this device ideal for industrial process control, instrumentation, and medical applications. The MAX1177 is available in a 20-pin TSSOP package and is fully specified over the -40C to +85C extended temperature range and the 0C to +70C commercial temperature range. o Byte-Wide Parallel Interface o Analog Input Voltage Range: 0 to +10V o Single +4.75V to +5.25V Analog Supply Voltage o Interfaces with +2.7V to +5.25V Digital Logic o 3 LSB INL o 1 LSB DNL o Low Supply Current (max) 2.9mA (External Reference) 3.8mA (Internal Reference) 5A AutoShutdown Mode o Small Footprint o 20-Pin TSSOP Package
Features
MAX1177
Ordering Information
PART MAX1177ACUP MAX1177BCUP MAX1177CCUP MAX1177AEUP MAX1177BEUP MAX1177CEUP TEMP RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP
Applications
Temperature Sensing and Monitoring Industrial Process Control I/O Modules Data-Acquisition Systems Precision Instrumentation
ANALOG INPUT AIN 0.1F +5V ANALOG +5V DIGITAL 0.1F
Typical Operating Circuit
AVDD
DVDD
P DATA D0-D7 BUS OR D8-D15 EOC REF REFADJ
MAX1177
R/C CS HBEN
Pin Configuration and Functional Diagram appear at end of data sheet. AutoShutdown is a trademark of Maxim Integrated Products, Inc.
HIGH BYTE LOW BYTE
AGND DGND
0.1F
10F
________________________________________________________________ Maxim Integrated Products
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16-Bit, 135ksps, Single-Supply ADC with to 10V Input Range MAX1177
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AIN to AGND .....................................................-16.5V to +16.5V REF, REFADJ to AGND............................-0.3V to (AVDD + 0.3V) CS, R/C, HBEN to DGND .........................................-0.3V to +6V D_, EOC to DGND ...................................-0.3V to (DVDD + 0.3V) Maximum Continuous Current into Any Pin ........................50mA Continuous Power Dissipation (TA = +70C) TSSOP (derate 10.9mW/C above +70C) ..................879mW Operating Temperature Ranges MAX1177_CUP ...................................................0C to +70C MAX1177_EUP ................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V 5%, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Differential Nonlinearity RES MAX1177A DNL No missing codes over temperature MAX1177A Integral Nonlinearity INL MAX1177B MAX1177C Transition Noise Offset Error Gain Error Offset Drift Gain Drift AC ACCURACY (fIN = 1kHz, VAIN = full range, 135ksps) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range ANALOG INPUT Input Range Input Resistance Input Current Input Capacitance VAIN RAIN IAIN CIN Normal operation Shutdown mode 0 VAIN +10V 0 5.3 5.3 -0.1 10 +2.0 6.9 10 9.2 V k mA pF SINAD SNR THD SFDR 92 85 86 90 91 -100 103 -92 dB dB dB dB RMS noise, external reference Internal reference -10 MAX1177B MAX1177C 16 -1 -1.0 -1 -3 -3 -4 0.6 0.75 0 0 16 1 +10 0.2 +1 +1.5 +2 +3 +3 +4 LSBRMS mV %FSR V/C ppm/C LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
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16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V 5%, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INTERNAL REFERENCE REF Output Voltage REF Output Tempco REF Short-Circuit Current EXTERNAL REFERENCE REF and REFADJ Input-Voltage Range REFADJ Buffer-Disable Threshold REF Input Current REFADJ Input Current DIGITAL INPUTS/OUTPUTS Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance Tri-State Output Leakage Tri-State Output Capacitance POWER SUPPLIES Analog Supply Voltage Digital Supply Voltage Analog Supply Current AVDD DVDD IAVDD External reference, 135ksps Internal reference, 135ksps Shutdown mode (Note 1), digital input = DVDD or 0V Standby mode Digital Supply Current Power-Supply Rejection IDVDD AVDD = DVDD = 4.75V to 5.25V 3.5 0.5 3.7 0.75 4.75 2.70 5.25 5.25 2.9 3.8 5 V V mA A mA mA LSB VHYST CIN IOZ COZ 15 VOH VOL VIH VIL Digital input = DVDD or 0V -1 0.2 15 10 ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V ISINK = 1.6mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V 0.7 x DVDD 0.3 x DVDD +1 DVDD 0.4 0.4 V V V V A V pF A pF IREF IREFADJ Normal mode, fSAMPLE = 135ksps Shutdown mode (Note 1) REFADJ = AVDD 3.8 AVDD 0.4 60 0.1 16 4.2 AVDD 0.1 100 10 V V A A IREF-SC VREF 4.056 4.096 35 10 4.136 V ppm/C mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1177
Shutdown Supply Current
ISHDN
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16-Bit, 135ksps, Single-Supply ADC with to 10V Input Range MAX1177
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to TMAX.)
PARAMETER Maximum Sampling Rate Acquisition Time Conversion Time CS Pulse-Width High CS Pulse-Width Low (Note 2) R/C to CS Fall Setup Time R/C to CS Fall Hold Time CS to Output Data Valid EOC Fall to CS Fall CS Rise to EOC Rise Bus Relinquish Time HBEN Transition to Output Data Valid SYMBOL fSAMPLE-MAX tACQ tCONV tCSH tCSL tDS tDH tDO tDV tEOC tBR tDO1 DVDD = 4.75V to 5.25V DVDD = 2.7V to 5.25V DVDD = 4.75V to 5.25V DVDD = 2.7V to 5.25V DVDD = 4.75V to 5.25V DVDD = 2.7V to 5.25V DVDD = 4.75V to 5.25V DVDD = 2.7V to 5.25V DVDD = 4.75V to 5.25V DVDD = 2.7V to 5.25V 0 40 80 40 80 40 80 (Note 2) DVDD = 4.75V to 5.25V DVDD = 2.7V to 5.25V 40 40 60 0 40 60 40 80 2 4.7 CONDITIONS MIN TYP MAX 135 UNITS ksps s s ns ns ns ns ns ns ns ns ns
Note 1: Maximum specification is limited by automated test equipment. Note 2: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
Typical Operating Characteristics
(Typical Operating Circuit, AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, CLOAD = 20pF. Typical values are at TA = +25C, unless otherwise noted.)
INL vs. CODE
MAX1177 toc01
DNL vs. CODE
2.5 2.0 1.5 1.0 DNL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 SUPPLY CURRENT (mA) 2.20 2.15
MAX1177 toc02
SUPPLY CURRENT (AVDD + DVDD) vs. TEMPERATURE
5.25V
MAX1177 toc03
3 2 1 INL (LSB) 0 -1 -2 -3 8192 24,576 40,960 57,344 CODE
2.25
5.0V 2.10 2.05 2.00 4.75V 1.95 -40 -20 0 20 40 60 80 TEMPERATURE (C) fSAMPLE = 135ksps SHUTDOWN MODE BETWEEN CONVERSIONS
-2.5 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE
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16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range
Typical Operating Characteristics (continued)
(Typical Operating Circuit, AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, CLOAD = 20pF. Typical values are at TA = +25C, unless otherwise noted.)
SUPPLY CURRENT (AVDD + DVDD) vs. SAMPLE RATE
MAX1177 toc04
MAX1177
SHUTDOWN CURRENT (AVDD + DVDD) vs. TEMPERATURE
NO CONVERSIONS
MAX1177 toc05
OFFSET ERROR vs. TEMPERATURE
8 6 OFFSET ERROR (mV) 4 2 0 -2 -4 -6 -8 -10
MAX1177 toc06
10
5.0 SHUTDOWN SUPPLY CURRENT (A) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
10
1 SUPPLY CURRENT (mA) STANDBY MODE
0.1
0.01
SHUTDOWN MODE
0.001
0.0001 0.01 0.1 1 10 100 1000 SAMPLE RATE (ksps)
0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-40
-20
0
20
40
60
80
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE
MAX1177 toc07
INTERNAL REFERENCE vs. TEMPERATURE
MAX1177 toc08
FFT AT 1kHz
-20 -40 MAGNITUDE (dB) -60 -80 -100 -120 -140 -160 -180 fSAMPLE = 131ksps
MAX1177 toc09
0.20 0.15 GAIN ERROR (%FSR) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -40 -20 0 20 40 60 80 TEMPERATURE (C)
4.136 4.126 INTERNAL REFERENCE (V) 4.116 4.106 4.096 4.086 4.076 4.066 4.056 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0
0
10
20
30
40
50
60
FREQUENCY (kHz)
SINAD vs. FREQUENCY
MAX1177 toc10
SFDR vs. FREQUENCY
MAX1177 toc11
THD vs. FREQUENCY
-10 -20 -30 -40 -50 -60 -70 -80 -90
MAX1177 toc12
100 90 80 70 SINAD (dB)
120 100 80 SFDR (dB) 60 40 20
0
50 40 30 20 10 0 1 10 FREQUENCY (kHz) 100 fSAMPLE = 131ksps
fSAMPLE = 131ksps 0 1 10 FREQUENCY (kHz) 100
THD (dB)
60
-100 -110 1 10
fSAMPLE = 131ksps 100
FREQUENCY (kHz)
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16-Bit, 135ksps, Single-Supply ADC with to 10V Input Range MAX1177
Pin Description
PIN 1 2 3 4 NAME D4/D12 D5/D13 D6/D14 D7/D15 Tri-State Digital-Data Output Tri-State Digital-Data Output Tri-State Digital-Data Output Tri-State Digital-Data Output. D15 is the MSB. Read/Convert Input. Power up and put the device in acquisition mode by holding R/C low during the first falling edge of CS. During the second falling edge of CS, the level on R/C determines whether the reference and reference buffer power down or remain on after conversion. Set R/C high during the second falling edge of CS to power down the reference and buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third falling edge of CS to put valid data on the bus. End of Conversion. EOC drives low when conversion is complete. Analog Supply Input. Bypass with a 0.1F capacitor to AGND. Analog Ground. Primary analog ground (star ground). Analog Input Analog Ground. Connect pin 10 to pin 8. Reference Buffer Output. Bypass REFADJ with a 0.1F capacitor to AGND for internal reference mode. Connect REFADJ to AVDD to select external reference mode. Reference Input/Output. Bypass REF with a 10F capacitor to AGND for internal reference mode. External reference input when in external reference mode. High-Byte Enable Input. Used to multiplex the 16-bit conversion result. 1: MSB available on the data bus. 0: LSB available on the data bus. Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C is low. The second falling edge of CS starts the conversion. The third falling edge of CS loads the result onto the bus when R/C is high. Digital Ground Digital Supply Voltage. Bypass with a 0.1F capacitor to DGND. Tri-State Digital-Data Output. D0 is the LSB. Tri-State Digital-Data Output Tri-State Digital-Data Output Tri-State Digital-Data Output FUNCTION
5
R/C
6 7 8 9 10 11 12
EOC AVDD AGND AIN AGND REFADJ REF
13
HBEN
14 15 16 17 18 19 20
CS DGND DVDD D0/D8 D1/D9 D2/D10 D3/D11
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16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range
Detailed Description
Converter Operation
The MAX1177 uses a successive-approximation (SAR) conversion technique with an inherent track-and-hold (T/H) stage to convert an analog input into a 16-bit digital output. Parallel outputs provide a high-speed interface to microprocessors (Ps). The Functional Diagram shows a simplified internal architecture of the MAX1177. Figure 3 shows a typical operating circuit for the MAX1177.
DVDD 1mA DO-D15 DO-D15 CLOAD = 20pF DGND a) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z b) HIGH-Z TO VOL, VOH TO VOL, AND VOL TO HIGH-Z CLOAD = 20pF DGND
Analog Input
Input Scaler The MAX1177 has an input scaler, which allows conversion of input voltages ranging from 0 to 10V, while operating from a single +5V analog supply. The input scaler attenuates and shifts the analog input to match the input range of the internal digital-to-analog converter (DAC). Figure 4 shows the equivalent input circuit of the MAX1177. This circuit limits the current going into AIN to less than 2mA. Track and Hold (T/H) In track mode, the internal hold capacitor acquires the analog signal (Figure 4). In hold mode, the T/H switches open and the capacitive DAC samples the analog input. During the acquisition, the analog input (AIN) charges capacitor CHOLD. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on CHOLD represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion time to restore node T/H OUT to zero within the limits of 16-bit resolution. Force CS low to put valid data on the bus after conversion is complete.
MAX1177
1mA
Figure 1. Load Circuits
tCSL CS tACQ R/C tDH EOC
tCSH
REF POWERDOWN CONTROL tDS tDV tEOC
tCONV
tDO
HBEN HIGH-Z D7/D15-D0/D8 tDO tDO1 HIGH/LOW BYTE VALID tBR HIGH-Z HIGH/LOW BYTE VALID
Figure 2. MAX1177 Timing Diagram
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16-Bit, 135ksps, Single-Supply ADC with to 10V Input Range MAX1177
Power-Down Modes
Select standby mode or shutdown mode with the R/C bit during the second falling edge of CS (see the Selecting Standby or Shutdown Mode section). The MAX1177 automatically enters either standby mode (reference and buffer on) or shutdown (reference and buffer off) after each conversion, depending on the status of R/C during the second falling edge of CS.
+5V ANALOG +5V DIGITAL
0.1F
0.1F
Internal Clock
The MAX1177 generates an internal conversion clock to free the P from the burden of running the SAR conversion clock. Total conversion time (tCONV) after entering hold mode (second falling edge of CS) to end-of-conversion (EOC) falling is 4.7s (max).
ANALOG INPUT AIN
AVDD
DVDD P DATA D0-D7 BUS OR D8-D15
MAX1177
R/C
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the MAX1177 (Figure 2). The first falling edge of CS powers up the device and puts it in acquire mode if R/C is low. The convert start is ignored if R/C is high. The device needs at least 12ms for the internal reference to wake up and settle before starting the conversion (CREFADJ = 0.1F, CREF = 10F), if powering up from shutdown.
HIGH BYTE LOW BYTE CS HBEN
EOC REF REFADJ 0.1F 10F
AGND DGND
Selecting Standby or Shutdown Mode
The MAX1177 has a selectable standby or low-power shutdown mode. In standby mode, the ADC's internal reference and reference buffer do not power down between conversions, eliminating the need to wait for the reference to power up before performing the next conversion. Shutdown mode powers down the reference and reference buffer after completing a conversion. The reference and reference buffer require a minimum of 12ms to power up and settle from shutdown (CREFADJ = 0.1F, CREF = 10F). The state of R/C at the second falling edge of CS selects which power-down mode the MAX1177 enters upon conversion completion. Holding R/C low causes the device to enter standby mode. The reference and buffer are left on after the conversion completes. R/C high causes the MAX1177 to enter shutdown mode and power-down the reference and buffer after conversion (Figures 5 and 6). Set the voltage at R/C high during the second falling edge of CS to realize the lowest current operation.
Figure 3. Typical Operating Circuit for the MAX1177
MAX1177
R2 3.92k AIN R3 17.79k 161
R1 3.4k TRACK S1 HOLD TRACK HOLD S2 CHOLD 30pF T/H OUT
S1, S2 = T/H SWITCH R2 = 3.92k R3 = 17.79k
Figure 4. Equivalent Input Circuit
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16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range MAX1177
ACQUISITION CONVERSION DATA OUT ACQUISITION CONVERSION DATA OUT
CS
CS
R/C
R/C
EOC REF AND BUFFER POWER
EOC REF AND BUFFER POWER
Figure 5. Selecting Standby Mode
Figure 6. Selecting Shutdown Mode
Standby Mode
While in standby mode, the supply current is less than 3.7mA (typ). The next falling edge of CS with R/C low causes the MAX1177 to exit standby mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time. Shutdown Mode In shutdown mode, the reference and reference buffer are shut down between conversions. Shutdown mode reduces supply current to 0.5A (typ) immediately after the conversion. The next falling edge of CS with R/C low causes the reference and buffer to wake up and enter acquisition mode. To achieve 16-bit accuracy, allow 12ms for the internal reference to wake up (CREFADJ = 0.1F, CREF = 10F).
100k
+5V
MAX1177
68k REFADJ
150k
0.1F
Internal and External Reference
Internal Reference The internal reference of the MAX1177 is internally buffered to provide +4.096V output at REF. Bypass REF to AGND and REFADJ to AGND with 10F and 0.1F, respectively. Sink or source current at REFADJ to make fine adjustments to the internal reference. The input impedance of REFADJ is nominally 5k. Use the circuit in Figure 7 to adjust the internal reference to 1.5%. External Reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the MAX1177's internal buffer amplifier. Using the buffered REFADJ input
Figure 7. MAX1177 Reference Adjust Circuit
makes buffering the external reference unnecessary. The input impedance of REFADJ is typically 5k. The internal buffer output must be bypassed at REF with a 10F capacitor. Connect REFADJ to AVDD to disable the internal buffer. Directly drive REF using an external 3.8V to 4.2V reference. During conversion, the external reference must be able to drive 100A of DC load current and have an output impedance of 10 or less. For optimal performance, buffer the reference through an op amp and bypass REF with a 10F capacitor. Consider the MAX1177's equivalent input noise (0.6 LSB) when choosing a reference.
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16-Bit, 135ksps, Single-Supply ADC with to 10V Input Range MAX1177
OUTPUT CODE 1111 1111 1111 1111 1111 1111 1111 1110 1111 1111 1111 1101 INPUT RANGE = 0V TO +10V FULL-SCALE TRANSITION
MAX1177
AIN ANALOG INPUT
FULL-SCALE RANGE (FSR) = +10V
MAX427
0000 0000 0000 0011 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 0 1 2 3
1 LSB =
FSR x VREF 65536 x 4.096
65,535 65,534 65,536 INPUT VOLTAGE (LSB)
Figure 8. MAX1177 Transfer Function
Figure 9. MAX1177 Fast-Settling Input Buffer
Reading the Conversion Result
EOC is provided to flag the P when a conversion is complete. The falling edge of EOC signals that the data is valid and ready to be output to the bus. D0-D15 are the parallel outputs of the MAX1177. These tri-state outputs allow for direct connection to a microcontroller I/O bus. The outputs remain high impedance during acquisition and conversion. Data is loaded onto the output bus with the third falling edge of CS with R/C high (after tDO). Bringing CS high forces the output bus back to high impedance. The MAX1177 then waits for the next falling edge of CS to start the next conversion cycle (Figure 2). HBEN toggles the output between the high/low byte. The low byte is loaded onto the output bus when HBEN is low, and the high byte is on the bus when HBEN is high.
change in input signal. The input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. Figure 9 shows an example of this circuit using the MAX427.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital ground planes with only one point connecting the two ground systems (analog and digital) as close to the device as possible. Route digital signals far away from sensitive analog and reference inputs. If digital lines must cross analog lines, do so at right angles to minimize coupling digital noise onto the analog lines. If the analog and digital sections share the same supply, isolate the digital and analog supply by connecting them with a low-value (10) resistor or ferrite bead. The ADC is sensitive to high-frequency noise on the AV DD supply. Bypass AV DD to AGND with a 0.1F capacitor in parallel with a 1F to 10F low-ESR capacitor with the smallest capacitor closest to the device. Keep capacitor leads short to minimize stray inductance.
Transfer Function
Figure 8 shows the MAX1177 output transfer function. The output is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to achieve 16-bit accuracy and prevent loading the source. When the input signal is multiplexed, switch the channels immediately after acquisition, rather than near the end of, or after, a conversion. This allows more time for the input buffer amplifier to respond to a large step
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16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1177 are measured using the end-point method.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals: SignalRMS SINAD(dB) = 20 x log (Noise + Distortion)RMS
MAX1177
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows: ENOB = SINAD -1.76 6.02
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of 1 LSB guarantees no missing codes and a monotonic transfer function.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76)dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. The SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 THD = 20 x log V1
where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component.
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16-Bit, 135ksps, Single-Supply ADC with to 10V Input Range MAX1177
Functional Diagram
REFADJ 5k REFERENCE 8 BITS 8 BITS D0-D7 OR D8-D15 HBEN AVDD AGND DVDD DGND
OUTPUT REGISTERS REF
AIN
INPUT SCALER
CAPACITIVE DAC
AGND SUCCESSIVEAPPROXIMATION REGISTER AND CONTROL LOGIC
MAX1177
CLOCK
CS R/C
EOC
Pin Configuration
TOP VIEW
D4/D12 1 D5/D13 2 D6/D14 3 D7/D15 4 R/C 5 EOC 6 AVDD 7 AGND 8 AIN 9 AGND 10 20 D3/D11 19 D2/D10 18 D1/D9 17 D0/D8
Chip Information
TRANSISTOR COUNT: 15,383 PROCESS: BiCMOS
MAX1177
16 DVDD 15 DGND 14 CS 13 HBEN 12 REF 11 REFADJ
TSSOP
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16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX1177
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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