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M74HC699
U/D 4 BIT BINARY COUNTER/REGISTER (3-STATE)
s
s
s
s
s
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HIGH SPEED: fMAX = 53 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) for QA to QD OUTPUT |IOH| = IOL = 4mA (MIN) for RCO OUTPUT BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 699
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HC699B1R M74HC699M1R T&R M74HC699RM13TR M74HC699TTR
DESCRIPTION The M74HC699 is an high speed CMOS UP / DOWN COUNTER REGISTER (3 STATE) fabricated with silicon gate C2MOS technology The M74HC699 is a 4 BIT BINARY COUNTER with REGISTER. The device counts on the positive edge of the counter clock input (CCK) when selected by the "Counter Mode". If the input U/D is held "H", the internal counter counts up, and held "L", counts down. The internal counter's outputs are stored in the output register at the positive edge of register clock (RCK).
The counter features enable P and enable T and a ripple-carry output for easy expansion. The register/counter select input, R/C, selects the counter when low or the register when high for the three state outputs, QA, QB, QC, and QD. Both the counter clock CCR and register clock RCK are positive-edge triggered. The counter clear CCLR is active low and is synchronous. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2 3, 4, 5, 6 7, 14 8 9 11 12 13 15 to 18 19 10 20 SYMBOL U/D CCK A to D ENP/ENT CCLR RCK R/C G LOAD QA to QD RCO GND VCC NAME AND FUNCTION Up Down Counter Selector Counter Clock Data Inputs Enable P and T Counter Clear (Active LOW) Register Clock Counter/Register Select Enable Input Load Counter (Active LOW) Data Outputs Load Counter (Active High) Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS CCLR LOAD X L H H H H H H X X X X L H H H H X X X ENP X X X H X L L X X X ENT X X X X H L L X X X X X CCK X U/D X X X X X H L X X X RCK X X X X X X X X R/C X L L L L L L L H H G H L L L L L L L L L a' OUTPUTS FUNCTION QA QB QC QD Z L a Z L b Z L c Z L d HIGH IMPEDANCE CLEAR COUNTER LOAD COUNTER NO COUNT NO COUNT COUNT UP COUNT DOWN NO COUNT d' LOAD REGISTER NO LOAD
NO CHANGE NO CHANGE COUNT UP COUNT DOWN NO CHANGE b' c'
NO CHANGE
X : Don't Care Z : High Impedance a-d : The level of steady state inputs at inputs A through D respectively. a'-d' : The level of steady state outputs at internal counter outputs QA' through QD' respectively RCO = (UP * QA * QB * QC * QD * ENT + UP * QA * QB * QC * QD * ENT)
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BLOCK DIAGRAM
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current per Output PIN (RCO) (QA to QD) Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 35 70 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current PD Tstg TL
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 C; derate to 300mW by 10mW/C from 65C to 85C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns
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DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOH High Level Output Voltage (RCO) 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage (QA - QD) 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage (RCO) 2.0 4.5 6.0 4.5 6.0 II IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current 6.0 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-6.0 mA IO=-7.8 mA IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=20 A IO=20 A IO=20 A IO=6.0 mA IO=7.8 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 0.1 0.1 0.26 0.26 0.1 0.5 4 1.9 4.4 5.9 4.13 5.63 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 0.1 0.1 0.1 0.33 0.33 1 5 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 0.1 0.1 0.1 0.40 0.40 1 10 80 A A A V V V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage (QA - QD)
VIL
V
VOH
ICC
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 CL (pF) TA = 25C Min. Typ. 25 7 6 30 8 7 90 28 24 103 32 27 82 24 20 95 28 24 109 32 27 61 20 17 73 24 20 63 18 15 12 45 53 45 15 13 57 19 16 32 17 14 40 8 7 Max. 60 12 10 75 15 13 215 43 37 245 49 42 185 37 31 215 43 37 245 49 42 155 31 26 185 37 31 140 28 24 4 20 24 120 24 20 150 30 26 115 23 20 75 15 13 150 30 26 190 38 32 145 29 25 95 19 16 Value -40 to 85C Min. Max. 75 19 13 95 19 16 270 54 46 305 61 52 230 46 39 270 54 46 305 61 52 195 39 33 230 46 39 175 35 30 3.4 17 20 180 36 31 225 45 38 175 35 30 110 22 19 -55 to 125C Min. Max. 90 18 15 115 23 20 325 65 55 370 74 63 280 56 48 325 65 55 370 74 63 235 47 40 280 56 48 210 42 36 ns Unit
tTLH tTHL Output Transition Time (Qn) tTLH tTHL Output Transition Time (RCO) tPLH tPHL Propagation Delay Time (CCK - Q)
50
50
ns
50
ns
150
tPLH tPHL Propagation Delay Time (RCK - Q)
50
ns
150
tPLH tPHL Propagation Delay Time (CCK - RCO) tPLH tPHL Propagation Delay Time (R/C - Q)
50
ns
50
ns
150
tPLH tPHL Propagation Delay Time (ENT - RCO) fMAX Maximum Clock Frequency
50 5 25 30 RL = 1 K
ns
50
MHz
tPZL tPZH High Impedance Output Enable Time
50
ns
150
RL = 1 K
ns
tPLZ tPHZ High Impedance Output Disable Time tW(L) tW(H) Minimum Pulse Width (CCK, RCK)
50
RL = 1 K
ns
50
ns
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Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 CL (pF) TA = 25C Min. Typ. 16 4 3 64 16 14 16 4 3 44 11 9 44 11 9 Max. 50 10 9 150 30 26 50 10 9 100 20 17 100 20 17 5 5 5
Value -40 to 85C Min. Max. 65 13 11 190 38 32 65 13 11 125 25 21 125 25 21 5 5 5 -55 to 125C Min. Max. 75 15 13 220 44 37 75 15 13 150 30 26 145 29 25 5 5 5 ns Unit
ts
Minimum Set-Up Time (CCLR) Minimum Set-up Time (LOAD, ENT, ENP) Minimum Set-up Time (A, B, C, D) Minimum Set-up Time (CCK - RCK) Minimum Set-up Time (U/D) Minimum Hold Time
50
ts
50
ns
ts
50
ns
ts
50
ns
ts
50
ns
th
50
ns
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 5 71 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/2 (per circuit)
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TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open VCC GND
WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 2 : MINIMUM PULSE WIDTH, REMOVAL TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 4 : MINIMUM SETUP AND HOLD TIME, PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
WAVEFORM 5 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 6 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
WAVEFORM 7 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
WAVEFORM 8 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
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Plastic DIP-20 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 TYP. MAX. inch
P001J
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SO-20 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.020 13.00 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.393 0.050 0.450 0.300 0.050 0.029 0.512 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch
PO13L
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TSSOP20 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.260 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0087225C
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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