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INTEGRATED CIRCUITS
74F175A Quad D flip-flop
Product specification Supersedes data of 1996 Mar 12 IC15 Data Handbook 2000 Jun 30
Philips Semiconductors
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
FEATURES
* Four edge-triggered D-type flip-flops * Buffered common clock * Buffered asynchronous Master Reset * True and complementary outputs * Industrial temperature range available (-40C to +85C) * PNP light loading inputs
DESCRIPTION
The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. All Q outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and complementary outputs are required, and the CP and MR are common to all storage elements.
PIN CONFIGURATION
MR 1 16 VCC 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP
Q0 2 Q0 3 D0 4 D1 5 Q1 6 Q1 7 GND 8
SF00718
TYPE 74F175A
TYPICAL fmax 160MHz
TYPICAL SUPPLY CURRENT (TOTAL) 22mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F175AN N74F175AD INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F175AN I74F175AD PKG. DWG. #
16-pin plastic DIP 16-pin plastic SO
SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0 - D3 MR CP Q0-Q3 Q0-Q3 Data inputs Master reset input (active-Low) Clock input (active rising edge) True outputs Complementary outputs DESCRIPTION 74F175A 74F175A 74F175A 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 50/33 50/33 LOAD VALUE HIGH/LOW 20A/20A 20A/20A 20A/20A 1.0mA/20mA 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
2000 Jun 30
2
853-0047 24024
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
LOGIC SYMBOL
4 5 12 13
IEC/IEEE SYMBOL
1 9 R C1 2 D0 D1 D2 D3 4 1D 3 7 5 6 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 10 12 11 15 2 3 7 6 10 11 15 14 13 14
9 1
CP MR
VCC = Pin 16 GND = Pin 8
SF00719
SF00720
LOGIC DIAGRAM
D0 4 CP 9 D1 5 D2 12 D3 13
D
Q
D
Q
D
Q
D
Q
CP RD MR VCC = Pin 16 GND = Pin 8 1 3 2 Q0 Q0
CP RD
CP RD
CP Q RD
6 Q1
7 Q1
11 Q2 Q2
10 Q3
14
15 Q3
SF00721
FUNCTION TABLE
INPUTS MR L H H CP X Dn X h I OUTPUTS Qn L H L Qn H L H OPERATING MODE Reset (clear) Load "1" Load "0" H = High voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time before the Low-to-High clock transition X = Don't care = Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb b Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Commercial range O erating Operating free air tem erature range temperature Industrial range Storage temperature range -40 to +85 -65 to +150 PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 UNIT V V mA V mA
C C C
2000 Jun 30
3
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIK IOH IOL Tamb b Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Commercial range Operating free air temperature range Industrial range 0 -40 4.5 2.0 0.8 -18 -1 20 +70 +85 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA UNIT
C C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VOH VOL High-level out ut voltage output Low-level output voltage VCC= MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = 0.0V, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX -60 22 "10%VCC "5%VCC "10%VCC "5%VCC MIN 2.5 2.7 3.4 0.30 0.30 -0.73 0.5 0.5 -1.2 100 20 -20 -150 31 V V A A A mA mA V LIMITS TYP2 MAX UNIT
VIK II IIH IIL IOS ICC
Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3
Supply current (total)
Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS Tamb = 25C SYMBOL PARAMETER TEST CONDITION MIN fmax tPLH tPHL tPLH tPHL tPHL tPHL 2000 Jun 30 Maximum clock frequency Propagation delay CP to Qn or Qn Propagation delay MR to Qn Propagation delay MR to Qn Waveform 1 Waveform 1 Waveform 3 Waveform 3 140 3.0 4.5 4.5 4.5 VCC = +5V CL = 50pF, RL = 500 TYP 160 4.0 6.0 6.5 6.0 6.5 8.5 9.0 8.0 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 125 2.5 4.0 4.5 4.0 7.5 9.0 10.0 9.0 MAX Tamb = *40C to +85C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 110 2.5 4.0 4.5 4.0 8.0 10.0 11.0 10.0 MAX MHz ns ns ns UNIT
4
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
AC SETUP REQUIREMENTS
LIMITS Tamb = 25C SYMBOL PARAMETER TEST CONDITION MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) tREC Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP CP Pulse width High or Low MR Pulse width Low Recovery time MR to CP Waveform 2 Waveform 2 Waveform 1 Waveform 3 Waveform 3 3.0 3.0 0.0 0.0 3.0 4.0 3.5 4.0 VCC = +5V CL = 50pF, RL = 500 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 3.5 3.5 0.0 0.0 3.5 5.0 3.5 4.5 MAX Tamb = *40C to +85C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 4.0 4.0 0.0 0.0 4.0 5.5 4.0 5.0 MAX ns ns ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.3V.
1/fmax MR CP VM tw(H) tPHL VM tPLH Qn VM tw(L) tPLH CP VM tPHL tPHL Qn tPLH VM VM VM tw(L) tREC VM VM VM
Qn
VM
SF00722
Qn
VM
Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency
SF00723
Waveform 3. Master Reset pulse width, Master Reset to output delay and Master Reset to Clock recovery time
Dn VM ts(H) CP VM th(H) VM ts(L) VM th(L)
VM
VM
SF00191
Waveform 2. Data setup time and hold times
2000 Jun 30
5
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
2000 Jun 30
6
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
2000 Jun 30
7
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
2000 Jun 30
8
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
NOTES
2000 Jun 30
9
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 06-00 Document order number: 9397-750 07531
Philips Semiconductors
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