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FEATURES 14-Bit 30 MSPS A/D Converter 30 MSPS Correlated Double Sampler (CDS) 4 dB 6 dB 6-Bit Pixel Gain Amplifier (PxGA(R)) 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single-Supply Operation Low Power: 153 mW @ 3 V Supply Space-Saving 48-Lead LFCSP Package APPLICATIONS High Performance Digital Still Cameras Industrial/Scientific Imaging
Complete 14-Bit 30 MSPS CCD Signal Processor AD9824
PRODUCT DESCRIPTION
The AD9824 is a complete analog signal processor for CCD applications. It features a 30 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9824's signal chain consists of an input clamp, a correlated double sampler (CDS), PxGA, a digitally controlled VGA, a black level clamp, and a 14-bit A/D converter. Additional input modes are also provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power-down modes. The AD9824 operates from a single 3 V power supply, typically dissipates 153 mW, and is packaged in a 48-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS HD VD VRT VRB PBLK
4dB CCDIN CDS
6dB
COLOR STEERING 2dB~36dB 2:1 MUX VGA
BAND GAP REFERENCE
DRVDD DRVSS
PxGA
ADC
14
DOUT
CLP 6 CLPDM 10 AUX1IN 2:1 MUX AUX2IN CLP CONTROL REGISTERS BUF 8 BLK CLAMP LEVEL CLPOB CLP
DVDD
AD9824
DIGITAL INTERFACE
INTERNAL TIMING
DVSS
SL
SCK
SDATA
SHP
SHD
DATACLK
PxGA is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD9824-SPECIFICATIONS
GENERAL SPECIFICATIONS (T
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage Data Output Coding VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB)
Specifications subject to change without notice.
MIN
to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
Min -20 -65 2.7 Typ Max +85 +150 3.6 Unit C C V
(Specified Under Each Mode of Operation) 5 0.5 30 14 0.5 14 2.0 Straight Binary 2.0 1.0 1.0 mW mW MHz Bits LSB Bits Guaranteed V
V V
DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, C = 20 pF, unless otherwise noted.)
L
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA
Specifications subject to change without notice.
Symbol VIH VIL IIH IIL CIN VOH VOL
Min 2.1
Typ
Max
Unit V V A A pF V V
0.6 10 10 10 2.2 0.5
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AD9824 CCD-MODE SPECIFICATIONS (T
Parameter POWER CONSUMPTION
MAXIMUM CLOCK RATE CDS Gain Allowable CCD Reset Transient 1 Max Input Range Before Saturation 1 Max CCD Black Pixel Amplitude 1 PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range (Two's Complement Coding) Min Gain (PxGA Gain Code 32) Max Gain (PxGA Gain Code 31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Gain Code 77) Max Gain (VGA Gain Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level SYSTEM PERFORMANCE Gain Accuracy2 Low Gain (VGA Code 77) Max Gain (VGA Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) POWER-UP RECOVERY TIME Reference Standby Mode Total Shutdown Mode Power-Off Condition
NOTES 1 Input signal characteristics defined as follows:
MIN
to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 30 MHz, unless otherwise noted.)
Typ
153
Min
Max
Unit
mW MHz
Notes
See TPC 1 for Power Curves
30 0 500 1.0 200 1.0 1.6 64 Guaranteed -2.5 9.5 1.6 2.0 1024 Guaranteed 2 36 256 0 1020
dB mV V p-p mV V p-p V p-p Steps
See Input Waveform in Footnote 1 PxGA Gain at 4 dB
See Figure 28 for PxGA Gain Curve dB dB V p-p V p-p Steps See Figure 29 for VGA Gain Curve dB dB Steps Measured at ADC Output LSB LSB Specifications Include Entire Signal Chain Gain = (0.0353 x Code) +3.3 5.5 38.2 6 39.4 0.1 2.0 40 1 3 15 6.5 40.2 dB dB % LSB rms dB ms ms ms 12 dB Gain Applied AC Grounded Input, 6 dB Gain Applied Measured with Step Change on Supply Normal Clock Signals Applied
500mV TYP RESET TRANSIENT 200mV MAX OPTICAL BLACK PIXEL
2
1V MAX INPUT SIGNAL RANGE
PxGA gain fixed at Code 63 (3.3 dB).
Specifications subject to change without notice.
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AD9824-SPECIFICATIONS
AUX1-MODE SPECIFICATIONS (T
Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain
Specifications subject to change without notice.
MIN
to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
Min Typ 120 30 0 1.0 2.0 1023 0 36 Max Unit mW MHz dB V p-p V p-p Steps dB dB
AUX2-MODE SPECIFICATIONS
Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain ACTIVE CLAMP Clamp Level Resolution Clamp Level (Measured at ADC Output) Min Clamp Level Max Clamp Level
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
Min Typ 120 30 (Same as AUX1-MODE) 2.0 512 0 18 256 0 1020 V p-p Steps dB dB Steps LSB LSB Max Unit mW MHz
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AD9824 TIMING SPECIFICATIONS Serial Timing in Figures 21-24.)
Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth CLPOB Pulsewidth* SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay Inhibited Clock Period DATA OUTPUTS Output Delay Output Hold Time Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read
Specifications subject to change without notice.
(CL = 20 pF, fSAMP = 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7,
Symbol tCP tADC tSHP tSHD tCDM tCOB tS1 tS2 tID tINH tOD tH Min 33 13 5 5 4 2 0 15 10 13 7.6 9 16 Typ 33 16.7 8.3 8.3 10 20 8.3 16.7 3.0 Max Unit ns ns ns ns Pixels Pixels ns ns ns ns ns ns Cycles MHz ns ns ns ns ns
7.0
fSCLK tLS tLH tDS tDH tDV
10 10 10 10 10 10
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
ABSOLUTE MAXIMUM RATINGS With Respect To Min Max AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 300
ORDERING GUIDE
Model
Unit V V V V V V V V V C C
Temperature Range -20C to +85C
Package Description LFCSP
Package Option CP-48
Parameter AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL BYP1-3, CCDIN Junction Temperature Lead Temperature (10 sec)
AD9824KCP
THERMAL CHARACTERISTICS
Thermal Resistance 48-Lead LFCSP Package JA = 26C/W* *JA is measured using a 4-layer PCB with the exposed paddle soldered to the board.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9824 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9824
PIN CONFIGURATIONS
D0 (LSB) SDATA DVDD2 DVSS STBY
SCK
VRB
VRT
NC
48 47 46 45 44 43 42 41 40 39 38 37
D2 1 D3 2 D4 3 D5 4 D6 5 D7 6 D8 7 D9 8 D10 9 D11 10 D12 11 (MSB) D13 12 NC = NO CONNECT
NC
36 35 34 33
D1
SL
PIN 1 IDENTIFIER
AUX1IN AVSS AUX2IN AVDD2 BYP3 NC CCDIN BYP2 BYP1 AVDD1 AVSS AVSS
AD9824
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24
DRVDD
DVDD1
HD
CLPDM
CLPOB
SHD
DRVSS
DVSS
DATACLK
PIN FUNCTION DESCRIPTIONS Pin Number 1-12 13 14 15, 41 16 17 18 19 20 21 22 23 24 25, 26, 35 27 28 29 30 31 32 33 34 36 37 38 39 40 42 43 44 45 46 47, 48 Name D2-D13 DRVDD DRVSS DVSS DATACLK DVDD1 HD PBLK CLPOB SHP SHD CLPDM VD AVSS AVDD1 BYP1 BYP2 CCDIN NC BYP3 AVDD2 AUX2IN AUX1IN NC VRT VRB DVDD2 NC STBY SL SDATA SCK D0-D1 Type DO P P P DI P DI DI DI DI DI DI DI P P AO AO AI NC AO P AI AI NC AO AO P NC DI DI DI DI DI Description Digital Data Outputs. Pin 12 (D13) is MSB. Digital Output Driver Supply Digital Output Driver Ground Digital Ground Digital Data Output Latch Clock Digital Supply 1 Horizontal Drive. Used with VD for color steering control. Preblanking Clock Input Black Level Clamp Clock Input CDS Sampling Clock for CCD's Reference Level CDS Sampling Clock for CCD's Data Level Input Clamp Clock Input Vertical Drive. Used with HD for color steering control. Analog Ground Analog Supply 1 Internal Bias Level Decoupling Internal Bias Level Decoupling Analog Input for CCD Signal Internally Not Connected Internal Bias Level Decoupling Analog Supply 2 Analog Input Analog Input Internally Not Connected A/D Converter Top Reference Voltage Decoupling A/D Converter Bottom Reference Voltage Decoupling Digital Supply 2 Internally Not Connected Standby Mode, Active High. Same as total power-down mode. Serial Digital Interface Load Pulse Serial Digital Interface Data Serial Digital Interface Clock Digital Data Outputs. Pin 47 (D0) is LSB.
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
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PBLK
SHP
VD
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AD9824
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 14-bit resolution indicates that all 16,384 codes, respectively, must be present over all operating conditions.
Peak Nonlinearity
chain at the specified gain setting. The output noise can be converted to an equivalent voltage using the relationship 1 LSB = (ADC Full Scale/2N codes) where N is the bit resolution of the ADC. For the AD9824, 1 LSB is 125 V.
Power Supply Rejection (PSR)
Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9824 from a true straight line. The point used as "zero scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a Level 1, 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range.
Total Output Noise
The PSR is measured with a step change applied to the supply pins. This represents a high frequency disturbance on the AD9824's power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
Internal Delay for SHP/SHD
The internal delay (also called aperture delay) is the time delay that occurs from when a sampling edge is applied to the AD9824 until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock's rising edge to the instant the actual internal sample is taken.
The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal
EQUIVALENT INPUT CIRCUITS
DVDD
ACVDD
330
ACVSS
DVSS
ACVSS
Figure 1. Digital Inputs--SHP, SHD, DATACLK, CLPOB, CLPDM, HD, VD, PBLK, SCK, and SL
DVDD DRVDD
Figure 3. CCDIN (Pin 30)
DATA
DVDD
DVDD
DATA IN
THREESTATE
DOUT
DATA OUT
330
RNW
DVSS DVSS DVSS
DVSS
DRVSS
Figure 2. Data Outputs--D0-D13
Figure 4. SDATA (Pin 45)
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AD9824-Typical Performance Characteristics
190 180 170
100 90 80
POWER DISSIPATION - mW
160 150 VDD = 3.0V 140 130 VDD = 2.7V 120 110 100 10
OUTPUT NOISE - LSB
VDD = 3.3V
70 60 50 40 30 20 10 0 0 255 511 VGA GAIN CODE - LSB 767 1023
20 SAMPLE RATE - MHz
30
TPC 1. Power vs. Sample Rate
TPC 3. Output Noise vs. VGA Gain
0.5
0.25
0
-0.25
-0.5 0
2000
4000
6000
8000
10000 12000 14000 16000
TPC 2. Typical DNL Performance
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AD9824
CCD MODE AND AUX MODE TIMING
CCD SIGNAL
tID
N
N+1
N+2
N+9
N+10
tID
SHP
tS1
SHD
tS2
tCP
tINH
DATACLK
tOD
OUTPUT DATA N-10 N-9
tH
N-8 N-1 N
NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 5. CCD Mode Timing
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
HORIZONTAL BLANKING
DUMMY PIXELS
EFFECTIVE PIXELS
CCD SIGNAL
CLPOB
CLPDM
PBLK
OUTPUT DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
NOTES 1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
Figure 6. Typical CCD Mode Line Clamp Timing
N VIDEO SIGNAL
N+9 N+1
tID tCP
N+8 N+2
DATACLK
tOD
OUTPUT DATA N-10 N-9
tH
N-8 N-1 N
Figure 7. AUX Mode Timing
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AD9824
PIXEL GAIN AMPLIFIER (PxGA) TIMING
FRAME N 0101... HD LINE 0 2323... LINE 1 0101... LINE 2 LINE M-1 LINE M 0101... LINE 0 2323... LINE 1 FRAME N+1 0101... LINE 2 LINE M-1 LINE M VD
*0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
5 PIXEL MIN VD
HD
3ns MIN
3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0
GAIN1
GAIN0
GAINX
GAIN2
GAIN3
NOTES 1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES. 2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns. 3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101. 4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
VD 0101... HD LINE 0 2323... LINE 1
EVEN FIELD
ODD FIELD
0101... LINE 2 LINE M-1 LINE M
0101... LINE 0
2323... LINE 1
0101... LINE 2 LINE M-1 LINE M
*0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
VD
5 PIXEL MIN HD
3ns MIN
3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0
GAIN1
GAIN0
GAINX
GAIN2
GAIN3
NOTES 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101. 3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
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AD9824
VD 012012012... HD *0 = GAIN0, 1 = GAIN1, 2 = GAIN2 LINE N ...01201 012012012... LINE N+1
Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
5 PIXEL MIN VD 5 PIXEL MIN HD 3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0
GAIN1
GAIN2
GAIN0
GAINX
GAIN0
GAIN1
NOTES 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.
Figure 13. PxGA Mode 3 (3-Color) Detailed Timing
VD 01230123012... HD
LINE N ...01230 012301230123...
LINE N+1
*0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
5 PIXEL MIN VD 5 PIXEL MIN HD 3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0
GAIN1
GAIN2
GAIN0
GAINX
GAIN0
GAIN1
NOTES 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.
Figure 15. PxGA Mode 4 (4-Color) Detailed Timing
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AD9824
VD 0101... HD LINE 0 0101... LINE 1 ODD FIELD EVEN FIELD 0101... LINE 2 LINE M-1 LINE M 2323... LINE 0 2323... LINE 1 2323... LINE 2 LINE M-1 LINE M
*0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
VD 5 PIXEL MIN HD 3ns MIN 3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0
GAIN1
GAIN0
GAINX
GAIN2
GAIN3
NOTES 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101. 3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323. 4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323... (ODD).
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
VD 0101... HD LINE 0 1212... LINE 1
FRAME N 0101... LINE 2 LINE M-1 LINE M 0101... LINE 0 1212... LINE 1
FRAME N+1 0101... LINE 2 LINE M-1 LINE M
* 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
5 PIXEL MIN VD
HD 3ns MIN 3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0
GAIN1
GAIN0
GAINX
GAIN1
GAIN2
NOTES 1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES. 2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns. 3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101. 4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
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AD9824
VD
HD
3ns MIN
3ns MIN
SHP
PxGA GAIN
GAIN0
GAIN1
GAIN0
GAIN2
GAIN3
NOTES 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. VD = 0 AND HD = 0 SELECTS GAIN0. 3. VD = 0 AND HD = 1 SELECTS GAIN1. 4. VD = 1 AND HD = 0 SELECTS GAIN2. 5. VD = 1 AND HD = 1 SELECTS GAIN3.
Figure 20. PxGA Mode 7 (User-Specified) Detailed Timing
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AD9824
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map
Register Name
Operation VGA Gain Clamp Level Control PxGA Gain0 PxGA Gain1 PxGA Gain2 PxGA Gain3
Address A0 A1 A2
000 10 0 010 110 001 101 011 111
D0 D1 D2
D3
Data Bits D4 D5
D6
D7
01
D8
12
D9
01
D10
01 MSB 01 X X X X X X X
Channel Select Power-Down CCD/AUX1/2 Modes LSB LSB Color Steering Mode Selection LSB LSB LSB LSB PxGA On/Off
Software OB Clamp Reset On/Off
MSB Clock Polarity Select for SHP/SHD/CLP/DATA MSB MSB MSB MSB X X X X 01 X X X X
X 01 X X X X
X ThreeState X X X X
NOTES 1 Internal use only. Must be set to zero. 2 Must be set to one.
RNW SDATA 0 A0 A1 A2 TEST BIT 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
SCK
tDH
tLS
SL NOTES 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. RNW = READ-NOT-WRITE. SET LOW FOR WRITE OPERATION. 3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW. 4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
tLH
Figure 21. Serial Write Operation
RNW SDATA 1 A0 A1 0
TEST BIT 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
SCK
tDH
tDV
tLS
SL
tLH
NOTES 1. RNW = READ-NOT-WRITE. SET HIGH FOR READ OPERATION. 2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW. 3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE AND IS UPDATED ON SCK FALLING EDGES.
Figure 22. Serial Readback Operation
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AD9824
RNW A0 A1 SDATA 0 0 0 A2 0 0 11 BITS OPERATION D0 ... 10 BITS ACG GAIN ... D9 8 BITS CLAMP LEVEL D0 ... D7 10 BITS CONTROL D0 ... D9 6 BITS PxGA GAIN0 D0 ... D5 6 BITS PxGA GAIN1 D0 ... D5 6 BITS PxGA GAIN2 D0 ... D5 6 BITS PxGA GAIN3 D0 ... D5
D10 D0
SCK 1 SL 2 3 4 5 6
... 16 17
... 26 27
... 34 35
... 44 45
... 50 51
... 56 57
... 62 63
... 68
...
NOTES 1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME. 2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER. 3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Figure 23. Continuous Serial Write Operation to All Registers
RNW SDATA 0
A0 0
A1 0
A2 1 0 D0 D1
PxGA GAIN0 D2 D3 D4 D5 D0 D1
PxGA GAIN1 D2 D3 D4 D5
PxGA GAIN2 D0 ... D5
PxGA GAIN3 D0 ... D5
SCK 1 SL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
... 23 24
... 29
...
Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers
Table II. Operation Register Contents (Default Value x000) D10 01 D9 01 D8 01 D7 12 D6 01 Optical Black Clamp D5 0 Enable Clamping 1 Disable Clamping Reset D4 0 Normal 1 Reset All Registers to Default Power-Down Modes D3 D2 0 0 1 1 0 1 0 1 Normal Power Test Only Standby Total Power-Down Channel Selection D1 D0 0 0 1 1 0 1 0 1 CCD Mode AUX1 Mode AUX2 Mode Test Only
NOTES 1 Must be set to zero. 2 Set to one.
Table III. VGA Gain Register Contents (Default Value x000) D10 X MSB D9 0 D8 0 D7 0 D6 1 D5 0 * * * 1 1 D4 1 D3 1 D2 1 D1 1 LSB D0 1 Gain (dB) 2.0 * * * 35.965 36.0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
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AD9824
Table IV. Clamp Level Register Contents (Default Value x080) D10 X D9 X D8 X MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 * * * 1 1 1 1 1 1 1 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 Clamp Level (LSB) 0 4 8 * * * 1016
1
1
1
1
1
1
1
1
1020
Table V. Control Register Contents (Default Value x000) Data Out D10 D9 DATACLK D8 D7 D6 CLP/PBLK D5 SHP/SHD D4 PxGA D32 Color Steering Modes D2 D1 D0
X
0 Enable 01 1 Three-State
01
0 Rising Edge Trigger 0 Active Low 0 Active Low 1 Falling Edge Trigger 1 Active High 1 Active High
0 Disable 0 1 Enable 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Steering Disabled Mosaic Separate Interlace 3-Color 4-Color VD Selected Mosaic Repeat User Specified
NOTES 1 Must be set to zero. 2 When D3 = 0 (PxGA disabled), the PxGA gain is fixed to Code 63 (3.3dB).
Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000) D10 D9 D8 D7 D6 MSB D5 D4 D3 D2 D1 LSB D0 Gain (dB)*
X
X
X
X
X
0
1
1
* * *
1
1
1
+9.5
* * *
0 1
0 1
0 1
* * *
0 1
0 1
0 1
+3.5 +3.3
* * *
1
0
0
0
0
0
-2.5
*Control Register Bit D3 must be set high (PxGA Enable) to use the PxGA Gain Registers.
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AD9824
CIRCUIT DESCRIPTION AND OPERATION
The AD9824 signal processing chain is shown in Figure 25. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V to be compatible with the 3 V single supply of the AD9824.
Correlated Double Sampler
gain change on the system black level. Another advantage of removing this offset at the input stage is to maximize system headroom. Some area CCDs have large black level offset voltages, which, if not corrected at the input stage, can significantly reduce the available headroom in the internal circuitry when higher VGA gain settings are used. Horizontal timing is shown in Figure 6. It is recommended that the CLPDM pulse be used during valid CCD dark pixels. CLPDM may be used during the optical black pixels, either together with CLPOB or separately. The CLPDM pulse should be a minimum of 4 pixels wide.
PxGA
The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 5 illustrates how the two CDS clocks, SHP and SHD, are used to sample the reference level and data level of the CCD signal, respectively. The CCD signal is sampled on the rising edges of SHP and SHD. Placement of these two clock signals is critical in achieving the best performance from the CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by internal propagation delays.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD's optical black offset. This offset exists in the CCD's shielded black reference pixels. Unlike some AFE architectures, the AD9824 removes this offset in the input stage to minimize the effect of a
The PxGA provides separate gain adjustment for the individual color pixels. A programmable gain amplifier with four separate values, the PxGA has the capability to "multiplex" its gain value on a pixel-to-pixel basis. This allows lower output color pixels to be gained up to match higher output color pixels. Also, the PxGA may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed. The four different gain values are switched according to the color steering circuitry. Seven different color steering modes for different types of CCD color filter arrays are programmed in the AD9824's Control Register. For example, mosaic separate steering mode accommodates the popular "Bayer" arrangement of red, green, and blue filters (see Figure 26).
VD HD
COLOR STEERING 2
3
PxGA MODE SELECTION
GAIN0 4:1 MUX DC RESTORE 6 GAIN1 GAIN2 GAIN3 2dB TO 36dB 0.1 F CCDIN CDS PxGA VGA PxGA GAIN REGISTERS INTERNAL VREF 2V FULL SCALE 14-BIT ADC 14 DOUT
-2dB TO +10dB INPUT OFFSET CLAMP CLPDM VGA GAIN REGISTER 10 8-BIT DAC OPTICAL BLACK CLAMP DIGITAL FILTERING 8 CLAMP LEVEL REGISTER CLPOB
Figure 25. CCD Mode Block Diagram
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AD9824
CCD: PROGRESSIVE BAYER R Gb R Gb Gr B Gr B R Gb R Gb Gr B Gr B LINE0 LINE1 LINE2 MOSAIC SEPARATE COLOR STEERING MODE GAIN0, GAIN1, GAIN0, GAIN1... GAIN2, GAIN3, GAIN2, GAIN3... GAIN0, GAIN1, GAIN0, GAIN1...
Variable Gain Amplifier
Figure 26. CCD Color Filter Example: Progressive Scan
CCD: INTERLACED BAYER EVEN FIELD R R R R Gr Gr Gr Gr R R R R Gr Gr Gr Gr LINE0 LINE1 LINE2 VD SELECTED COLOR STEERING MODE GAIN0, GAIN1, GAIN0, GAIN1... GAIN0, GAIN1, GAIN0, GAIN1... GAIN0, GAIN1, GAIN0, GAIN1...
The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface. Combined with approximately 4 dB from the PxGA stage, the total gain range for the AD9824 is 6 dB to 40 dB. The minimum gain of 6 dB is needed to match -a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems (such as ADI's AD9803), the equivalent gain range is 0 dB to 34 dB. The VGA gain curve follows a "linear-in-dB" shape. The exact VGA gain can be calculated for any gain register value by using the following equation: Code Range 0-1023 Gain Equation (dB) Gain = (0.0353)(Code)
ODD FIELD Gb Gb Gb Gb B B B B Gb Gb Gb Gb B B B B LINE0 LINE1 LINE2 GAIN2, GAIN3, GAIN2, GAIN3... GAIN2, GAIN3, GAIN2, GAIN3...
As shown in the CCD Mode Specifications, only the VGA gain range from 2 dB to 36 dB has tested and guaranteed accuracy. This corresponds to a VGA gain code range of 77 to 1023. The Gain Accuracy Specifications also include a PxGA gain of approximately 3.3 dB, for a total gain range of 6 dB to 40 dB.
36
30
GAIN2, GAIN3, GAIN2, GAIN3...
VGA GAIN - dB
24
Figure 27. CCD Color Filter Example: Interlaced
18
The same Bayer pattern can also be interlaced, and the VD selected mode should be used with this type of CCD (see Figure 27). The color steering performs the proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers) and is synchronized by the user with vertical (VD) and horizontal (HD) sync pulses. For more detailed information, see the PxGA Timing section. The PxGA gain for each of the four channels is variable from -2.5 dB to +9.5 dB, controlled in 64 steps through the serial interface. The PxGA gain curve is shown in Figure 28.
10
12
6
0
0
127
255 383 511 639 767 VGA GAIN REGISTER CODE
895
1023
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
8
6
4
2
0
-2
-4 32 (100000)
40
48
58
0
8
16
24
31 (011111)
PxGA GAIN REGISTER CODE
The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD's black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the clamp level register. The clamp level is adjustable from 0 to 1020 LSB, in 256 steps. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the post processing, the AD9824 optical black clamping may be disabled using Bit D5 in the Operation Register (see Serial Interface Timing and Internal Register Description section). When the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. Horizontal timing is shown in Figure 6. The CLPOB pulse should be placed during the CCD's optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulsewidths may be used, but clamp noise may increase and the ability to track low frequency variations in the black level will be reduced. -18- REV. 0
PxGA GAIN - dB
Figure 28. PxGA Gain Curve
AD9824
A/D Converter
The AD9824 uses high performance ADC architecture, optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB, as shown in TPC 2. Instead of the 1 V full-scale range used by the earlier AD9801 and AD9803 products from Analog Devices, the AD9824's ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range (see TPC 3).
AUX1 Mode
The VGA gains up the signal level with respect to the 0.4 V bias level. Signal levels above the bias level will be further increased to a higher ADC code, while signal levels below the bias level will be further decreased to a lower ADC code.
AUX2 Mode
For applications that do not require CDS, the AD9824 can be configured to sample ac-coupled waveforms. Figure 30 shows the circuit configuration for using the AUX1 channel input (Pin 36). A single 0.1 F ac-coupling capacitor is needed between the input signal driver and the AUX1IN pin. An on-chip dc-bias circuit sets the average value of the input signal to approximately 0.4 V, which is referenced to the midscale code of the ADC. The VGA Gain Register provides a gain range of 0 dB to 36 dB in this mode of operation (see VGA Gain Curve, Figure 29).
For sampling video-type waveforms, such as NTSC and PAL signals, the AUX2 channel provides black level clamping, gain adjustment, and A/D conversion. Figure 31 shows the circuit configuration for using the AUX2 channel input (Pin 34). An external 0.1 F blocking capacitor is used with the on-chip video clamp circuit to level shift the input signal to a desired reference level. The clamp circuit automatically senses the most negative portion of the input signal and adjusts the voltage across the input capacitor. This forces the black level of the input signal to be equal to the value programmed into the Clamp Level Register (see Serial Interface Timing and Internal Register Description). The VGA provides gain adjustment from 0 dB to 18 dB. The same VGA Gain Register is used, but only the 9 MSBs of the gain register are used (see Table VII.)
0.8V
??V
0.4V 5k 0dB TO 36dB
0.1 F INPUT SIGNAL
AUX1IN VGA ADC MIDSCALE
0.4V
0.4V
10 VGA GAIN REGISTER
Figure 30. AUX1 Circuit Configuration
VGA GAIN REGISTER 9 BUFFER VIDEO SIGNAL AUX2IN VGA 0.1 F VIDEO CLAMP CIRCUIT LPF 8 CLAMP LEVEL REGISTER CLAMP LEVEL ADC
0dB TO 18dB
Figure 31. AUX2 Circuit Configuration
Table VII. VGA Gain Register Used for AUX2-Mode
D10 X
MSB D9 0 1
D8 X 0
D7 X 0
D6 X 0
D5 X 0 * * * 1
D4 X 0
D3 X 0
D2 X 0
D1 X 0
LSB D0 X 0
Gain (dB) 0.0 0.0 * * * 18.0
1
1
1
1
1
1
1
1
1
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-19-
AD9824
APPLICATIONS INFORMATION
The AD9824 is a complete analog front end (AFE) product for digital still camera and camcorder applications. As shown in Figure 32, the CCD image (pixel) data is buffered and sent to the AD9824 analog input through a series input capacitor. The AD9824 performs the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion.
The AD9824's digital output data is then processed by the image processing ASIC. The internal registers of the AD9824-- used to control gain, offset level, and other functions--are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE.
CCD VOUT 0.1 F
AD9824
ADCOUT CCDIN REGISTERDATA BUFFER CDS/CLAMP TIMING CCD TIMING TIMING GENERATOR
DIGITAL OUTPUTS SERIAL INTERFACE DIGITAL IMAGE PROCESSING ASIC
V-DRIVE
Figure 32. System Applications Diagram
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REV. 0
AD9824
3V ANALOG SUPPLY 0.1 F 1.0 F SERIAL INTERFACE 3 1.0 F
D1 D0 (LSB)
SDATA
DVDD2 VRB
DVSS
STBY
SCK
VRT
48 47 46 45 44 43 42 41 40 39 38 37
D2 1 D3 2 D4 3 D5
4 5
NC
NC
SL
PIN 1 IDENTIFIER
36 35 34 33
AUX1IN AVSS AUX2IN AVDD2 BYP3 NC CCDIN BYP2 BYP1 AVDD1 AVSS AVSS 0.1 F 0.1 F 3V ANALOG SUPPLY 0.1 F 0.1 F CCD SIGNAL 0.1 F 0.1 F 3V ANALOG SUPPLY
D6
D7 6 D8 D9 D10 D11 D12 (MSB) D13 DATA OUTPUTS 14
8 9
AD9824
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
7
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DRVDD
DVDD1
DATACLK
CLPDM
HD
CLPOB
SHD
SHP
DRVSS
DVSS
PBLK
VD
3V DRIVER SUPPLY
NC = NO CONNECT
0.1 F 8 CLOCK INPUTS
0.1 F 3V ANALOG SUPPLY
Figure 33. Recommended Circuit Configuration for CCD-Mode
Internal Power-On Reset Circuitry
After power-on, the AD9824 will automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes will be ignored until the internal reset operation is completed.
Grounding and Decoupling Recommendations
As shown in Figure 33, a single ground plane is recommended for the AD9824. This ground plane should be as continuous as possible, particularly around Pins 25 through 39. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and
their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9824, but a separate digital driver supply may be used for DRVDD (Pin 13). DRVDD should always be decoupled to DRVSS (Pin 14), which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing digital power dissipation and potential noise coupling. If the digital outputs (Pins 1-12) must drive a load larger than 20 pF, buffering is recommended to reduce digital code transition noise. Alternatively, placing series resistors close to the digital output pins may also help reduce noise.
REV. 0
-21-
AD9824
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches)
48-Lead Frame Chip Scale Package LFCSP 7 x 7 mm Body (CP-48)
0.60 (0.0236) 0.42 (0.0165) 0.24 (0.0094) 0.30 (0.0118) 0.23 (0.0091) 0.18 (0.0071)
7.00 (0.2756) BSC SQ
4
37
48 1
PIN 1 INDICATOR
36
TOP VIEW
6.75 (0.2657) BSC SQ
BOTTOM VIEW
5.45 (0.2146) 5.30 (0.2087) SQ 5.15 (0.2028)
0.50 (0.0197) 0.40 (0.0157) 0.30 (0.0118) 0.90 (0.0354) MAX 0.85 (0.0335) NOM 0.20 (0.0079) REF 12 MAX 0.70 (0.0315) MAX 0.65 (0.0276) NOM
25 24
1 13 2
5.50 (0.2165) REF
SEATING PLANE
0.50 (0.0197) BSC
0.05 (0.0020) 0.01 (0.0004) COPLANARITY 0.00 (0.0000)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-220
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REV. 0
-23-
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C02956-0-5/02(0)
PRINTED IN U.S.A.

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