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* 8 AVR(R) * RISC - 120 - - 32 8 - - 20 MHz 20 MIPS - 1K Flash : 10,000 - 64 EEPROM : 100,000 - 64 SRAM - EEPROM - 8 / PWM - 4 10 ADC - - - - SPI - / - - - - I/O - 8 PDIP/SOIC: 6 I/O : - ATTINY13V1.8 - 5.5V - ATTINY132.7 - 5.5V - ATTINY13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V - ATTINY13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V - : 1 MHz, 1.8V: 240A - : < 0.1A at 1.8V * * 1KB Flash 8 ATTINY13 * * * * * * Figure 1. ATTINY13 PDIP/SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/ADC1/T0/PCINT2) PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) Rev. 2535D-AVR-04/04 ATTINY13 AVR RISC 8 CMOS ATTINY13 1 MIPS/MHz Figure 2. ATTINY13 8-BIT DATABUS STACK POINTER WATCHDOG OSCILLATOR CALIBRATED INTERNAL OSCILLATOR SRAM VCC WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 TIMING AND CONTROL PROGRAM COUNTER GND PROGRAM FLASH INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS INTERRUPT UNIT PROGRAMMING LOGIC INSTRUCTION DECODER X Y Z CONTROL LINES ALU DATA EEPROM STATUS REGISTER ADC / ANALOG COMPARATOR DATA REGISTER PORT B DATA DIR. REG.PORT B PORT B DRIVERS RESET CLKI PB0-PB5 2 ATTINY13 2535D-AVR-04/04 ATTINY13 AVR 32 (ALU) CISC 10 ATTINY13 1K Flash EEPROM SRAM I/O 32 64 64 6 1 8 / / 4 10 ADC CPU SRAM T/C ADC ADC CPU ADC I/O ADC Atmel SPI ATTINY13 AVR C / VCC GND B (PB5..PB0) B 6 I/O B B P48 RESET P30Table 12 C C 3 2535D-AVR-04/04 AVR CPU AVR CPU Figure 3. AVR Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit Watchdog Timer Indirect Addressing Instruction Decoder Direct Addressing ALU Control Lines Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines AVR Harvard CPU ( ) Flash 32 8 ALU ALU 6 3 16 16 X Y Z 4 ATTINY13 2535D-AVR-04/04 ATTINY13 ALU ALU / 16 16 32 (PC) SRAM SRAM SP I/O SRAM 5 AVR AVR I/O I/O 64 CPU SPI I/O 0x20 - 0x5F ALU AVR ALU 32 ALU ALU 3 / 5 2535D-AVR-04/04 ALU AVR SREG Bit / 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: I I I RETI I I SEI CLI * Bit 6 - T: BLD BST T BST T BLD T * Bit 5 - H: H BCD * Bit 4 - S: , S = N V S N 2 V * Bit 3 - V: 2 2 * Bit 2 - N: * Bit 1 - Z: * Bit 0 - C: AVR RISC / * * * * 8 8 8 8 8 16 16 16 Figure 4 CPU 32 Figure 4. AVR CPU 7 R0 R1 0 Addr. 0x00 0x01 6 ATTINY13 2535D-AVR-04/04 ATTINY13 R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X X Y Y Z Z 0x0D 0x0E 0x0F 0x10 0x11 0x02 Figure 4 32 SRAM X Y Z 7 2535D-AVR-04/04 XYZ R26..R31 Figure 5 Figure 5. X Y Z 15 X 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0 15 Y 7 R29 (0x1D) 15 Z 7 R31 (0x1F) YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E) YL 0 0 ZL 0 0 / AVR SRAM 0x60 PUSH POP RET RETI AVRI/O8 AVR SPL SPH Bit 15 SP7 7 / R/W 1 14 SP6 6 R/W 0 13 SP5 5 R/W 0 12 SP4 4 R/W 1 11 SP3 3 R/W 1 10 SP2 2 R/W 1 9 SP1 1 R/W 1 8 SP0 0 R/W 1 SPL 8 ATTINY13 2535D-AVR-04/04 ATTINY13 AVR CPU clkCPU Figure 6 Harvard 1 MIPS/MHz / / Figure 6. T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7 ALU Figure 7. ALU T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back AVR I P40" " RESET INT0 - 0 I I RETI I "1" "0" I 9 2535D-AVR-04/04 AVR CLI CLI CLI EEPROM EEPROM in r16, SREG cli ; ; EEPROM ; SREG (I ) sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 ; SREG C char cSREG; cSREG = SREG; /* SREG */ /* */ __disable_interrupt(); EECR |= (1< ATTINY13 2535D-AVR-04/04 ATTINY13 SEI sei ; sleep ; ; : MCU C _SEI(); /* */ _SLEEP(); /* */ /* : MCU */ AVR 4 4 4 PC 3 MCU MCU 4 4 PC( ) SREG I 11 2535D-AVR-04/04 AVR ATTINY13 Flash ATTINY13 AVR ATTINY13 EEPROM ATTINY131KFlash AVR 16 32 Flash 512 x 16 Flash 10,000 ATTINY13 (PC) 9 512P97"" SPIFlash ( LPM ) P9" " Figure 8. Program Memory 0x0000 0x01FF 12 ATTINY13 2535D-AVR-04/04 ATTINY13 SRAM Figure 9 ATTINY13 SRAM 160 I/O SRAM 32 64 I/O 64 SRAM 5 R26 R31 Y Z 63 X Y Z ATTINY1332 64I/O64SRAM P6" " Figure 9. Data Memory 32 Registers 64 I/O Registers 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 Internal SRAM (64 x 8) 0x009F Figure 10 SRAM clkCPU Figure 10. SRAM T1 T2 T3 clkCPU Address Data WR Data RD Compute Address Address valid Memory Access Instruction Next Instruction EEPROM ATTINY13 64 EEPROM EEPROM 100,000 EEPROM P100 EEPROM EEPROM I/O 13 EEPROM / 2535D-AVR-04/04 Read Write EEPROM Table 1 EEPROM / VCC / CPU P18" EEPROM " EEPROM EEPROM P15" " P16" " EEPROM CPU 4 EEPROM CPU 2 EEPROM EEARL Bit / 7 - R 0 6 - R 0 5 EEAR5 R/W X 4 EEAR4 R/W X 3 EEAR3 R/W X 2 EEAR2 R/W X 1 EEAR1 R/W X 0 EEAR0 R/W X EEARL * Bits 7..6 - Res: * Bits 5..0 - EEAR5..0: EEPROM EEPROM EEARL 64 EEPROM EEPROM 0 63EEAR EEPROM EEPROM EEDR Bit / 7 EEDR7 R/W X 6 EEDR6 R/W X 5 EEDR5 R/W X 4 EEDR4 R/W X 3 EEDR3 R/W X 2 EEDR2 R/W X 1 EEDR1 R/W X 0 EEDR0 R/W X EEDR * Bits 7..0 - EEDR7..0: EEPROM EEPROM EEDR EEAR EEDR EEARL 14 ATTINY13 2535D-AVR-04/04 ATTINY13 EEPROM EECR Bit / 7 - R 0 6 - R 0 5 EEPM1 R/W X 4 EEPM0 R/W X 3 EERIE R/W 0 2 EEMPE R/W 0 1 EEPE R/W X 0 EERE R/W 0 EECR * Bit 7 - Res: * Bit 6 - Res: * Bits 5, 4 - EEPM1 EEPM0: EEPROM EEPE ( ) Table 1 EEPE EEPMn EEPROM EEPMn 0b00 Table 1. EEPROM EEPM1 0 0 1 1 EEPM0 0 1 0 1 3.4 ms 1.8 ms 1.8 ms - * Bit 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * Bit 2 - EEMPE: EEPROM EEMPE EEPE "1" EEMPE "1" EEPE EEPROM EEMPE "0" EEPE EEMPE "1" * Bit 1 - EEPE: EEPROM EEPE EEPROM EEPE "1" EEPMn EEPROM EEPE"1" EEMPE"1" EEPROM EEPE EEPE CPU * Bit 0 - EERE: EEPROM EEREEEPROM EEPROM EERE EEARL EEPROM EEPROM CPU 4 EEPROM EEPE EEPROM EEARL EEPROM EEARL EEDR EEPMn EEPE ( EEMPE ) / Table 1 EEPE EEPROM 15 2535D-AVR-04/04 ( ) ( ) EEARL EEPMn 0b01 EEPE ( EEMPE ) ( Table 1) EEPE EEPROM EEARL EEDR EEPMn 0b10 EEPE ( EEMPE ) ( Table 1) EEPE EEPROM EEPROM P22" - OSCCAL" 16 ATTINY13 2535D-AVR-04/04 ATTINY13 C EEPROM EEPROM_write: ; sbic EECR,EEPE rjmp EEPROM_write ; ldi out r16, (0< C void EEPROM_write(unsigned char ucAddress, unsigned char ucData) { /* */ while(EECR & (1< 2535D-AVR-04/04 C EEPROM EEPROM_read: ; sbic EECR,EEPE rjmp EEPROM_read ; r17 out EEARL, r17 ; EERE sbi EECR,EERE ; in ret r16,EEDR C unsigned char EEPROM_read(unsigned char ucAddress) { /* */ while(EECR & (1< CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD 18 ATTINY13 2535D-AVR-04/04 ATTINY13 I/O ATTINY13 I/O P150" " ATTINY13 I/O I/O I/O LD/LDS/LDD ST/STS/STD 32 I/O 0x00 - 0x1FI/OSBICBI SBISSBIC IN OUT 0x00 - 0x3F SRAM LD ST I/O 0x20 "0" I/O "1" AVR CBI SBI CBI SBI 0x00 0x1F I/O 19 2535D-AVR-04/04 Figure 11AVR P26" " Figure 11 Figure 11. ADC General I/O Modules CPU Core RAM Flash and EEPROM clkI/O clkADC AVR Clock Control Unit clkCPU clkFLASH Reset Logic Watchdog Timer Source clock Clock Multiplexer Watchdog clock Watchdog Oscillator External Clock Calibrated RC Oscillator CPU clkCPU I/O clkI/O Flash clkFLASH ADC clkADC CPUAVR CPU I/O I/O / I/O I/O Flash Flash CPU ADC ADCCPUI/O ADC ATTINY13 Flash AVR Table 2. (1) RC 128 kHz Note: 1. "1" "0" CKSEL1..0 01, 10 00 11 20 ATTINY13 2535D-AVR-04/04 ATTINY13 CPU CPU MCU WDT Table 3 Table 3. 4 ms 64 ms 512 8K (8,192) CKSEL = "10" SUT = "10" CKDIV8 9.6MHz RC 8 ISP 21 2535D-AVR-04/04 RC RC 9.6 MHz 4.8 MHz 3V 25C CKDIV8 8 P24" " Table 4 CKSEL OSCCAL RC 3V 25C 10% www.atmel.com/avr 3% P99" " Table 4. RC CKSEL1..0 10 (1) 9.6 MHz 4.8 MHz 01 Note: 1. SUT Table 5 . Table 5. RC SUT1..0 00 01 10 (1) 6 CK 6 CK 6 CK (VCC = 5.0V) 14CK 14CK + 4 ms 14CK + 64 ms BOD 11 Note: 1. OSCCAL Bit / 7 - R 0 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL * Bit 7 - Res: * Bits 6..0 - CAL6..0: OSCCAL 0x7F EEPROM Flash EEPROM Flash 10% 9.6 MHz 4.8 MHz 22 ATTINY13 2535D-AVR-04/04 ATTINY13 MCU RC 2% OSCCAL 0x20 Table 6. RC OSCCAL 0x00 0x3F 0x7F 50% 75% 100% 100% 150% 200% CLKI Figure 12 CKSEL "00" Figure 12. EXTERNAL CLOCK SIGNAL CLKI GND SUT Table 7 Table 7. SUT1..0 00 01 10 11 6 CK 6 CK 6 CK 14CK 14CK + 4 ms 14CK + 64 ms BOD MCU 2% MCU P24" " 23 2535D-AVR-04/04 128 kHz 128 kHz128 kHz 3V25C CKSEL "11" Table 8 SUT Table 8. 128 kHz SUT1..0 00 01 10 11 6 CK 6 CK 6 CK 14CK 14CK + 4 ms 14CK + 64 ms BOD ATTINY13 CLKPR CPU clkI/O clkADC clkCPU clkFLASH Table 9 Bit / 7 CLKPCE CLKPR 6 - 5 - 4 - 3 CLKPS3 2 CLKPS2 1 CLKPS1 0 CLKPS0 CLKPR R/W 0 R 0 R 0 R 0 R/W R/W R/W R/W * Bit 7 - CLKPCE: CLKPCE "1" CLKPS CLKPR"0"CLKPCE CLKPCE CLKPS CLKPCE CLKPCE * Bits 6..4 - Res: * Bits 3..0 - CLKPS3..0: 3 - 0 MCU Table 9 CLKPS 1. CLKPCE "1" CLKPR "0" 2. CLKPS CLKPCE "0" CKDIV8CLKPS CKDIV8 CLKPS"0000" CKDIV8 CLKPS "0011" 8 CLKPS 24 ATTINY13 2535D-AVR-04/04 ATTINY13 CKDIV8 CKDIV8 Table 9. CLKPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CLKPS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKPS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CLKPS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 256 CPU CLKPS T1 + T2 T1 + 2*T2 2 T1 T2 25 2535D-AVR-04/04 AVR MCU AVR MCUCR SE SLEEP ( ADC ) MCUCR SM1 SM0 Table 10 MCU 4 MCU SLEEP SRAM MCU P20Figure 11 ATTINY13 MCU MCUCR MCU Bit / 7 - R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 -- R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bit 5 - SE: MCU SLEEP SE SLEEP SEMCU SE * Bits 4, 3 - SM1..0: 2..0 Table 10 Table 10. SM1 0 0 1 1 SM0 0 1 0 1 ADC * Bit 2 - Res: 26 ATTINY13 2535D-AVR-04/04 ATTINY13 SM1..0 00 SLEEP MCU CPU ADC / clkCPU clkFLASH MCU MCU ACSR ACD ADC ADC SM1..0 01 SLEEP MCU CPU ADC clkI/O clkCPU clkFLASH ADC ADC AD ADC BOD SPM/EEPROM INT0 MCUADC SM1..0 10 SLEEP MCU BOD INT0 MCU MCU P51" " Table 11. X X X SPM/ EEPROM Other I/O X INT0 clkFLASH clkADC clkCPU ADC Note: X X X X X X X(1) X (1) X X 1. INT0 ADC X X clkIO 27 2535D-AVR-04/04 AVR ADC ADC P76" " ADC P73" " BOD BODLEVEL BOD P32" " BOD BOD ADC P34" " P40" " I/O clkI/O ADC clkADC P45" " VCC/2 VCC/2 DIDR0 P75" 0 - DIDR0" BOD 28 ATTINY13 2535D-AVR-04/04 ATTINY13 AVR I/O JMP Figure 13 Table 12 I/O MCU SUT CKSEL P20" " The ATTINY13 4 * * * * VPOT MCU RESET MCU VBOT MCU Figure 13. DATA BUS MCU Status Register (MCUSR) PORF BORF EXTRF WDRF Power-on Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER Brown-out Reset Circuit Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[1:0] SUT[1:0] 29 2535D-AVR-04/04 Table 12. (1) ( ) VPOT ( )(2) VRST tRST Notes: RESET RESET TA = -40 - 85C TA = -40 - 85C VCC = 1.8V - 5.5V VCC = 1.8V - 5.5V 0.1 VCC 1.1 0.9 VCC 2.5 V V s 1.2 V 1. 2. VPOT 30 ATTINY13 2535D-AVR-04/04 ATTINY13 (POR) Table 12 VCC POR POR POR CC V VCC RESET Figure 14. MCU RESET VCC VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET Figure 15. MCU RESET VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET 31 2535D-AVR-04/04 RESET ( Table 12) VRST( ) tTOUT MCU Figure 16. CC ATTINY13 BOD(Brown-out Detection) VCC BODLEVEL BOD VBOT+ = VBOT + VHYST/2 VBOT- = VBOT - VHYST/2 Table 13. BODLEVEL (1) BODLEVEL [1..0] 11 10 01 00 Note: VBOT VBOT BOD 1.8 2.7 4.3 V VBOT 1. VBOT VCC = VBOT VCC Table 14. VHYST tBOD 50 2 mV s BOD BOD VCC (VBOT- Figure 17) BOD VCC (VBOT+ Figure 17) tTOUT MCU VCC Table 12 tBOD BOD 32 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 17. VCC VBOTVBOT+ RESET TIME-OUT tTOUT INTERNAL RESET 1 CK tTOUT P40 Figure 18. CC CK MCU MCUSR MCU MCU Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR * Bits 7..4 - Res: * Bit 3 - WDRF: "0" * Bit 2 - BORF: "0" * Bit 1 - EXTRF: "0" * Bit 0 - PORF: "0" 33 2535D-AVR-04/04 ATTINY13 ADC Table 15 1. BOD ( BODLEVEL [1..0] ) 2. (ACSR ACBG ) 3. ADC BOD ACBG ADC Table 15. (1) VBG tBG IBG Note: 1. 1.0 1.1 40 15 1.2 70 V s A 34 ATTINY13 2535D-AVR-04/04 ATTINY13 ATTINY13 (WDT) * * 3 - - - * 16ms 8s * Figure 19. 128kHz OSCILLATOR OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K WATCHDOG RESET WDE WDP0 WDP1 WDP2 WDP3 MCU RESET WDIF INTERRUPT WDIE 128 kHz WDT WDT WDT WDTON (WDE)(WDTIE)10 1. WDCE WDE "1" WDE "1" 2. WDE WDP WDCE 35 2535D-AVR-04/04 C WDT ( ) (1) WDT_off: ; cli ; WDT wdr ; MCUSR WDRF in andi out r16, MCUSR r16, (0xff & (0< ; C (1) void WDT_off(void) { __disable_interrupt(); __watchdog_reset(); /* MCUSR WDRF*/ MCUSR &= ~(1< 36 ATTINY13 2535D-AVR-04/04 ATTINY13 (1) WDT_Prescaler_Change: ; cli ; wdr ; in ori out ; -ldi out ; -sei ret r16, WDTCR r16, (1< ; C (1) void WDT_Prescaler_Change(void) { __disable_interrupt(); __watchdog_reset(); /* */ WDTCR |= (1< Bit / 7 WDTIF R/W 0 6 WDTIE R/W 0 5 WDP3 R/W 0 4 WDCE R/W 0 3 WDE R/W X 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR 37 2535D-AVR-04/04 * Bit 7 - WDTIF: WDTIF "1" SREG I WDTIE * Bit 6 - WDTIE: SREG I WDE WDE WDTIF WDTIE WDTIF( ) WDTIE Table 16. WDTON 0 0 0 0 1 WDE 0 0 1 1 x WDTIE 0 1 0 1 x * Bit 4 - WDCE: WDE WDCE WDE / "1" WDCE * Bit 3 - WDE: WDE MCUSR WDRF WDRF WDE WDE WDRF * Bit 5, 2..0 - WDP3..0: 3, 2, 1 0 WDP3..0 P39Table 17 38 ATTINY13 2535D-AVR-04/04 ATTINY13 . Table 17. WDP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WDP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2K (2048) 4K (4096) 8K (8192) 16K (16384) 32K (32768) 64K (65536) 128K (131072) 256K (262144) 512K (524288) 1024K (1048576) VCC = 5.0V 16 ms 32 ms 64 ms 0.125 s 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s 39 2535D-AVR-04/04 ATTINY13 ATTINY13 AVR P9" " Table 18. 1 2 3 4 5 6 7 8 9 10 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 RESET INT0 PCINT0 TIM0_OVF EE_RDY ANA_COMP TIM0_COMPA TIM0_COMPB WDT ADC 0 1 / EEPROM / A / B ADC ATTINY13 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 ; 0x000A 0x000B 0x000C 0x000D ... ... RESET: ldi out sei 40 ATTINY13 2535D-AVR-04/04 ATTINY13 I/O I/O AVR I/O - - SBI CBI LED VCC Figure 20 P112" " Figure 20. I/O Rpu Pxn Logic Cpin See Figure "General Digital I/O" for Details "x" "n" PORTB3 B 3 PORTxn I/O P50"I/O " I/O : - PORTx - DDRx - PINx / PINx "1" "0" "1" MCUCR PUD I/O P41" I/O " P46" " I/O I/O I/O Figure 21 I/O 41 2535D-AVR-04/04 Figure 21. I/O(1) PUD Q D DDxn Q CLR RESET WDx RDx 1 Pxn Q D PORTxn Q CLR 0 RESET WRx SLEEP RRx WPx SYNCHRONIZER D Q D Q RPx PINxn L Q Q clk I/O PUD: SLEEP: clkI/O: PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER Note: 1. WRx, WPx, WDx, RRx, RPx RDx clkI/O, SLEEP PUD : DDxn PORTxn PINxn P50"I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0") PINxn "1" PORTxn DDRxn SBI ( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) MCUCR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b10) 42 ATTINY13 2535D-AVR-04/04 DATA BUS ATTINY13 Table 19 Table 19. DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD (in MCUCR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( ) DDxn PINxn Figure 21 PINxn Figure 22 tpd,max tpd,min Figure 22. SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx 43 2535D-AVR-04/04 SYNC LATCH PINxn tpd,max tpd,min 1/2 ~ 11/2 Figure 23 out in nop out SYNC LATCH tpd Figure 23. SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx 44 ATTINY13 2535D-AVR-04/04 ATTINY13 B 0 1 2 3 4 5 4 nop (1) ... ; ; ldi ldi out out nop r16,(1< C unsigned char i; ... /* */ /* */ PORTB = (1< ( ) 45 2535D-AVR-04/04 VCC GND I/O Figure 24 Figure 21 AVR Figure 24. (1) PUOExn PUOVxn 1 0 PUD DDOExn DDOVxn 1 0 Q D DDxn Q CLR PVOExn PVOVxn WDx RESET RDx 1 Pxn 0 Q D 1 0 PORTxn PTOExn WPx DIEOExn DIEOVxn 1 0 Q CLR RESET RRx WRx SLEEP SYNCHRONIZER D SET RPx Q D Q PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE PUD: WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn: PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WPx, WDx, RLx, RPxRDx I/O, SLEEP clk PUD 46 ATTINY13 2535D-AVR-04/04 DATA BUS ATTINY13 Table 20 Figure 24 Table 20. PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE DDxnPORTxn PUD PUOV / / DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn PTOE ,PORTxn DIEOV DIEOE MCU ( ) DIEOE DIEOV / / MCU ( ) / PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO / 47 2535D-AVR-04/04 MCU MCUCR Bit / 7 - R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bits 7, 2- Res: * Bit 6 - PUD: 1 DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P42" " B B Table 21 Table 21. B PB5 PB4 PB3 PB2 PB1 PB0 Notes: 1. 2. 3. 4. 5. RESET/dW/ADC0/PCINT5(1) ADC2/PCINT4(2) ADC3/CLKI/PCINT3(3) SCK/ADC1/T0/PCINT2(4) MISO/AIN1/OC0B/INT0/PCINT1/RXD(5) MOSI/AIN0/OC0A/PCINT0/TXD(6) I/O ADC ADC ADC / ADC 0 / PWM B 0 6. /PWMA Table 22 P49Table 23 B P46Figure 24 48 ATTINY13 2535D-AVR-04/04 ATTINY13 Table 22. PB5..PB3 PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: PB5/RESET/ ADC0/PCINT5 RSTDISBL 1 RSTDISBL(1) * DWEN(1) 0 0 0 RSTDISBL + (PCINT5 * PCIE + ADC0D) ADC0D PCINT5 RESET ADC0 (1) (1) PB4/ADC2/PCINT4 (1) PB3/ADC3/CLKI/PCINT3 0 0 0 0 0 0 0 PCINT3 * PCIE + ADC3D ADC3D PCINT3 ADC3 * DWEN 0 0 0 0 0 0 0 PCINT4 * PCIE + ADC2D ADC2D PCINT4 ADC2 1. 1 "0" ( ) Table 23. PB2..PB0 PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PB2/SCK/ADC1/ T0/PCINT2 0 0 0 0 0 0 0 PCINT2 * PCIE + ADC1D ADC1D T0/INT0/ PCINT2 ADC1 PB1/MISO/AIN1/ OC0B/INT0/PCINT1 0 0 0 0 OC0B OC0B 0 PCINT1 * PCIE + AIN1D AIN1D PCINT1 PB0/MOSI/AIN0/AREF/ OC0A/PCINT0 0 0 0 0 OC0A OC0A 0 PCINT0 * PCIE + AIN0D AIN0D PCINT0 49 2535D-AVR-04/04 I/O B PORTB Bit / 7 - 6 - 5 PORTB5 4 PORTB4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 B DDRB Bit / 7 - 6 - 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB R 0 R 0 B PINB Bit / 7 - 6 - 5 PINB5 R/W N/A 4 PINB4 R/W N/A 3 PINB3 R/W N/A 2 PINB2 R/W N/A 1 PINB1 R/W N/A 0 PINB0 R/W N/A PINB R 0 R 0 50 ATTINY13 2535D-AVR-04/04 ATTINY13 INT0PCINT5..0 INT0PCINT5..0 PCINT5..0PCI PCMSK PCINT5..0 MCU MCUCR INT0 I/O P20" " INT0 ( ) I/O MCU MCU P20" " SUT CKSEL MCU MCUCR A Bit / 7 - R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bits 1, 0 - ISC01, ISC00: 0 Bit1 Bit0 0 INT0 SREG I Table 24 MCU INT0 Table 24. 0 ISC01 0 0 1 1 ISC00 0 1 0 1 INT0 INT0 INT0 INT0 51 2535D-AVR-04/04 GIMSK Bit / 7 - R 0 6 INT0 R/W 0 5 PCIE R/W 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIMSK * Bits 7, 4..0 - Res: * Bit 6 - INT0: 0 INT0 '1' SREG I 0 1/0 (ISC01 ISC00) INT0 INT0 * Bit 5 - PCIE: PCIE '1' SREG I PCINT5..0 PCI PCINT5..0 PCMSK0 GIFR Bit / 7 - R 0 6 INTF0 R/W 0 5 PCIF R/W 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR * Bits 7, 4..0 - Res: * Bit 6 - INTF0: 0 INT0 INTF0 SREG I GIMSK INT0 "1" MCU "1" INT0 * Bit 5 - PCIF: PCINT5..0 PCIF "1" SREG I GIMSK PCIE "1"MCU "1" 52 ATTINY13 2535D-AVR-04/04 ATTINY13 PCMSK Bit / 7 - R 0 6 - R 0 5 PCINT5 R/W 1 4 PCINT4 R/W 1 3 PCINT3 R/W 1 2 PCINT2 R/W 1 1 PCINT1 R/W 1 0 PCINT0 R/W 1 PCMSK * Bits 7, 6 - Res: * Bits 5..0 - PCINT5..0: 5..0 PCINT5..0 I/O PCINT5..0 PCIE PCINT5..0 53 2535D-AVR-04/04 PWM 8 / 0 T/C0 8 / PWM * * * ( ) * PWM * PWM * * (TOV0, OCF0A OCF0B) Figure 258/ P1"ATTINY13" CPUI/O I/OP65"8 / " Figure 25. 8 T/C Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) = OCRnA Fixed TOP Value Waveform Generation OCnA DATA BUS OCnB (Int.Req.) Waveform Generation OCnB = OCRnB TCCRnA TCCRnB T/C(TCNT0)(OCR0A OCR0B) 8 ( Int.Req. ) TIFR0 TIMSK0 TIFR0 TIMSK0 T/C T0 ( )T/C T/C clkT0 (OCR0A OCR0B) T/C PWM OC0 P56" " (OCF0A OCF0B) "n" T/C 0 "x" A B TCNT0 T/C0 54 ATTINY13 2535D-AVR-04/04 ATTINY13 Table 25 Table 25. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR0A T/C T/C T/C TCCR0B CS02:0 P71"T/C " 8 T/C Figure 26 Figure 26. DATA BUS TOVn (Int.Req.) Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn ( ) count direction clear clkTn top bottom TCNT0 1 1 TCNT0 ( ) T/C clkT0 TCNT0 TCNT0 (0) 55 2535D-AVR-04/04 clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( ) T/C (TCCR0A) WGM01 WGM00 (TCCR0B) WGM02 OC0A P59" " T/CTOV0WGM01:0 TOV0CPU 8TCNT0OCR0A(OCR0B) TCNT0 OCR0A OCR0B OCF0A( OCF0B) CPU OCF0A( OCF0B) "1" WGM2:0 COM0x1:0 max bottom (P59" " ) Figure 27 Figure 27. DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom FOCn Waveform Generator OCnx WGMn1:0 COMnX1:0 56 ATTINY13 2535D-AVR-04/04 ATTINY13 PWM OCR0x OCR0x top bottom PWM OCR0x CPU OCR0x CPU OCR0x PWM FOC0x "1" OCF0x / OC0x (COM01:0 OC0x "0"-"1" ) CPU TCNT0 OCR0x TCNT0 TCNT0 TCNT0 T/C TCNT0 OCR0x TCNT0 BOTTOM OC0x OC0x FOC0x OC0x COM0x1:0 COM0x1:0 TCNT0 57 2535D-AVR-04/04 COM0x1:0 COM0x1:0 (OC0x) COM0x1:0 OC0x Figure 28 COM0x1:0 I/O I/O I/O COM0x1:0 I/O (DDR PORT) OC0xOC0x OC0x OC0x Figure 28. COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCn Pin OCnx D Q 0 DATA BUS PORT D Q DDR clk I/O COM0x1:0 I/O OC0x DDR OC0x DDR_OC0x OC0x COM0x1:0 P65"8 / " COM0x1:0 CTC PWM COM0x1:0 = 0 OC0x PWM P65Table 26 PWM P65Table 27 PWM P65Table 28 COM0x1:0 PWM FOC0x 58 ATTINY13 2535D-AVR-04/04 ATTINY13 - T/C - (WGM02:0) (COM0x1:0) COM0x1:0 PWM PWM COM0x1:0 (P58" " ) P63"T/C " Figure 32 Figure 33 Figure 34 Figure 35 (WGM02:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV0 TOV0 9 TOV0 CPU CTC( ) CTC (WGM02:0 = 2) OCR0A TCNT0 OCR0A OCR0A TOP CTC Figure 29 TCNT0 TCNT0 OCR0A TCNT0 Figure 29. CTC OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period 1 2 3 4 (COMnx1:0 = 1) OCF0A TOP TOP CTC TOP BOTTOM OCR0A TCNT0 0xFF 0x00 OCF0A CTC OC0A COM0A1:0 = 1 OC0A fOC0 = fclk_I/O/2 (OCR0 A= 0x00) f clk_I/O f OCnx = --------------------------------------------------2 N ( 1 + OCRnx ) N (1 8 64 256 1024) 59 2535D-AVR-04/04 TOV0 MAX 0x00 PWM PWM (WGM02:0 = 3 7) PWM PWM PWM BOTTOM TOP BOTTOM WGM2:0 = 3 TOP 0xFF WGM2:0 = 7 TOPOCR0A OC0xTCNT0OCR0x BOTTOM OC0x PWM PWM PWM DAC ( ) PWM TOP Figure 30 TCNT0 PWM PWM TCNT0 OCR0x TCNT0 Figure 30. PWM OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn OCn (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 TOP T/C TOV0 PWM OC0x PWM COM0x1:0 2 PWM 3 PWM WGM02 COM0A1:0 "1" AC0A OC0B ( P65Table 27) OC0x PWM OC0x OCR0x TCNT0 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = -----------------N 256 N (1 8 64 256 1024) OCR0A PWM OCR0A BOTTOM MAX+1OCR0AMAX COM0A1:0 60 ATTINY13 2535D-AVR-04/04 ATTINY13 OC0x(COM0x1:0 = 1) 50% OCR0A 0 foc0 = fclk_I/O/2 CTC OC0A PWM 61 2535D-AVR-04/04 PWM PWM (WGM02:0 = 1 5) PWM BOTTOM TOP TOP BOTTOM WGM2:0 = 1 TOP 0xFF WGM2:0 = 5 TOP OCR0A TOP TCNT0 OCR0x OC0x BOTTOM TCNT0 OCR0x OC0x TOP TCNT0 TOP Figure 31 TCNT0 PWM PWM TCNT0 OCR0x TCNT0 Figure 31. PWM OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn OCn (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 BOTTOM T/C TOV0 PWM OC0x PWM COM0x1:0 2 PWM COM0x1:0 3 PWM WGM02 COM0A0 "1" OC0A OC0B ( P65Table 28) OC0x OCR0x TCNT0 OC0x PWM PWM f clk_I/O f OCnxPCPWM = -----------------N 510 N (1 8 64 256 1024) OCR0A PWM PWM OCR0A BOTTOM OCR0A MAX PWM 62 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 31 2 OCn BOTTOM * Figure 31 OCR0A MAX OCR0A MAX OCn BOTTOM T/C MAX OCn OCR0A OCn * T/C T/C clkT0 Figure 32 T/C PWM MAX Figure 32. T/C clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 33 Figure 33. T/C fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 34 ( CTC )OCF0x OCR0A TOP Figure 34. T/C OCF0x fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx 63 2535D-AVR-04/04 Figure 35 CTC PWM OCF0A TCNT0 OCR0A TOP Figure 35. T/C CTC fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRnx TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFnx 64 ATTINY13 2535D-AVR-04/04 ATTINY13 8 / T/C A TCCR0A Bit / 7 COM0A1 6 COM0A0 5 COM0B1 4 COM0B0 3 - 2 - 1 WGM01 0 WGM00 TCCR0A R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 * Bits 7:6 - COM01A:0: A (OC0A) COM0A1:0 OC0A I/O OC0A DDR OC0A COM0A1:0 WGM02:0 Table 26 WGM02:0 CTC ( PWM) COM0A1:0 Table 26. PWM COM01 0 0 1 1 COM00 0 1 0 1 OC0A OC0A OC0A OC0A Table 27 WGM01:0 PWM COM01:0 Table 27. PWM (1) COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0A WGM02 = 0: OC0A WGM02 = 1: OC0A OC0A TOP OC0A OC0A TOP OC0A 1. OCR0A TOP COM01 TOP OC0 P60" PWM " Table 28 WGM02:0 PWM COM0A1:0 Table 28. PWM (1) COM0A1 0 0 1 1 COM0A0 0 1 0 1 OC0A WGM02 = 0: OC0A WGM02 = 1: OC0A OC0A OC0A OC0A OC0A 65 2535D-AVR-04/04 Note: 1. OCR0A TOP COM0A1 TOP OC0A P62" PWM " * Bits 5:4 - COM0B1:0: B OC0B COM0B1:0 OC0B 1 OC0B COM0B1:0 WGM01:0 Table 26 WGM02:0 CTC COM0B1:0 Table 29. PWM COM01 0 0 1 1 COM00 0 1 0 1 OC0B OC0B OC0B OC0B Table 27 WGM02:0 PWM COM0B1:0 Table 30. PWM (1) COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0B OC0A TOP OC0B OC0A TOP OC0B 1. OCR0B TOP COM0B1 TOP OC0B P60" PWM " Table 28 WGM02:0 PWM COM0B1:0 Table 31. PWM (1) COM0A1 0 0 1 1 Note: COM0A0 0 1 0 1 OC0B OC0B OC0B OC0B OC0B 1. OCR0B TOP COM0B1 TOP OC0B P62" PWM " * Bits 3, 2 - Res: * Bits 1:0 - WGM01:0: TCCR0B WGM02 TOP Table 32 T/C ( ) CTC PWM ( P59" " ) 66 ATTINY13 2535D-AVR-04/04 ATTINY13 Table 32. Mode 0 1 2 3 4 5 6 7 Notes: WGM2 0 0 0 0 1 1 1 1 WGM1 0 0 1 1 0 0 1 1 WGM0 0 1 0 1 0 1 0 1 T/C PWM CTC PWM PWM PWM TOP 0xFF 0xFF OCRA 0xFF - OCRA - OCRA OCRx TOP TOP - TOP - TOP TOV (1)(2) MAX BOTTOM MAX MAX - BOTTOM - TOP 1. MAX = 0xFF 2. BOTTOM = 0x00 67 2535D-AVR-04/04 T/C B TCCR0B Bit / 7 FOC0A 6 FOC0B 5 - 4 - 3 WGM02 2 CS02 1 CS01 0 CS00 TCCR0B W 0 W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bit 7 - FOC0A: A FOC0A WGM PWM PWM TCCR0B 1 OC0A COM0A1:0 FOC0A COM0A1:0 FOC0A OCR0ATOPCTC FOC0A 0 * Bit 6 - FOC0B: B FOC0B WGM PWM PWM TCCR0B 1 OC0B COM0B1:0 FOC0B COM0B1:0 FOC0B OCR0BTOPCTC FOC0B 0 * Bits 5:4 - Res: * Bit 3 - WGM02: P65"T/C A - TCCR0A" * Bits 2:0 - CS02:0: T/C Table 33. CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T0 T0 T/C0 T0 68 ATTINY13 2535D-AVR-04/04 ATTINY13 T/C TCNT0 Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0 TCNT0[7:0] T/C 8 TCNT0 TCNT0 TCNT0 OCR0x A OCR0A Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0A R/W 0 OCR0A[7:0] 8 TCNT0 OC0A B OCR0B Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0B R/W 0 OCR0B[7:0] 8 TCNT0 OC0B T/C TIMSK0 Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 OCIE0B R/W 0 2 OCIE0A R/W 0 1 TOIE0 R/W 0 0 - R 0 TIMSK0 * Bits 7..4, 0 - Res: * Bit 3 - OCIE0B: T/C B OCIE0B I "1" T/C B T/C TIFR0 OCF0B * Bit 2 - OCIE0A: T/C0 A OCIE0A I "1" T/C0 A T/C0 TIFR0 OCF0A * Bit 1 - TOIE0: T/C0 TOIE0 I "1" T/C0 T/C0 TIFR TOV0 T/C0 TIFR0 Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 OCF0B R/W 0 2 OCF0A R/W 0 1 TOV0 R/W 0 0 - R 0 TIFR0 * Bits 7..4, 0 - Res: 69 2535D-AVR-04/04 * Bit 3 - OCF0B: 0 B T/C OCR0B( 0B) OCF0B 1 SREG I OCIE0B(T/C0 B ) OCF0B * Bit 2 - OCF0A: 0 A T/C0 OCR0A( 0) OCF0A 1 SREG I OCIE0A(T/C0 ) OCF0A * Bit 1 - TOV0: T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0 WGM02:0 Table 32 P67" " 70 ATTINY13 2535D-AVR-04/04 ATTINY13 T/C CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T0 T/C clkT0 T0 ( ) Figure 36 T0 clkI/O CSn2:0 = 7 clkT1 CSn2:0 = 6 clkT0 Figure 36. T0 Tn_sync (To Clock Select Logic) Tn D LE Q D Q D Q clk I/O Synchronization Edge Detector T1/T0 2.5 3.5 T0 T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5 71 2535D-AVR-04/04 Figure 37. T/C0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: 1. (T0) Figure 36 T/C GTCCR Bit / 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 PSR10 R/W 0 GTCCR * Bit 7 - TSM: T/C TSM"1"T/C PSR10 T/C TSM "0" PSR10 T/C * Bit 0 - PSR10: T/C0 T/C0 TSM 72 ATTINY13 2535D-AVR-04/04 ATTINY13 AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure 38 Figure 38. (2) BANDGAP REFERENCE ACBG ACME ADEN ADC MULTIPLEXER OUTPUT (1) Notes: 1. P75Table 35. 2. P1Figure 1 P49Table 23 ADC B ADCSRB Bit / 7 - R 0 6 ACME R/W 0 5 - R 0 4 - R 0 3 - R 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB * Bit 6 - ACME: "1" ADC ( ADCSRA ADEN 0) ADC "0"AIN1 P75" " ACSR Bit / 7 ACD R/W 0 6 ACBG R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 - R 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: ACD ACD ACSR ACIE ACD * Bit 6 - ACBG: ACBG "1" ACBG AIN0 * Bit 5 - ACO: ACO 1 - 2 * Bit 4 - ACI: 73 2535D-AVR-04/04 ACIS1 ACIS0 ACI ACIE SREG I ACI ACI 1 * Bit 3 - ACIE: ACIE 1 I * Bit 2 - Res: * Bits 1, 0 - ACIS1, ACIS0: Table 34 Table 34. ACIS1/ACIS0 ACIS1 0 0 1 1 ACIS0 0 1 0 1 ACIS1/ACIS0 ACSR 74 ATTINY13 2535D-AVR-04/04 ATTINY13 ADC3..0 ADC ADC (ADCSRB ACME ) ADC (ADCSRA ADEN )ADMUX MUX1..0 Table 35 ACME ADEN AIN1 Table 35. ACME 0 1 1 1 1 1 ADEN x 1 0 0 0 0 MUX1..0 xx xx 00 01 10 11 AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 0 DIDR0 Bit / 7 - R 0 6 - R 0 5 ADC0D R/W 0 4 ADC2D R/W 0 3 ADC3D R/W 0 2 ADC1D R/W 0 1 AIN1D R/W 0 0 AIN0D R/W 0 DIDR0 * Bits 1, 0 - AIN1D, AIN0D: AIN1, AIN0 "1" AIN1/0 AIN1/0 "1" 75 2535D-AVR-04/04 * * * * * * * * * * * * * 10 0.5 LSB 2 LSB 13 - 260 s 15 kSPS ADC 0 - VCC ADC 1.1V ADC ADC ADC ATTINY13 10 ADC ADC 4 B 0V (GND) ADC ADC ADC Figure 39 1.1V VCC Figure 39. ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 8-BIT DATA BUS ADIF ADIE 15 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADC[9:0] 0 ADC MULTIPLEXER SELECT (ADMUX) MUX1 ADLAR REFS1 MUX0 ADC CTRL. & STATUS REGISTER (ADCSRA) ADATE ADPS2 ADPS1 ADSC ADEN ADIF TRIGGER SELECT MUX DECODER CHANNEL SELECTION PRESCALER START CONVERSION LOGIC VCC INTERNAL 1.1V REFERENCE 10-BIT DAC SAMPLE & HOLD COMPARATOR + ADC3 ADC2 ADC1 ADC0 INPUT MUX ADC MULTIPLEXER OUTPUT 76 ATTINY13 2535D-AVR-04/04 ATTINY13 ADC 10 GND VCC 1.1V ADMUX MUX ADC ADC ADC ADCSR ADEN ADEN ADEN ADC ADC ADC10 ADCADCHADCL ADMUX ADLAR 8 ADCH ADCL ADCH ADCL ADC ADCL ADCH ADC ADCH ADC ADCH ADCL ADC ADCHADCLADC ADSC 1 1 0 ADC ADCSRA ADATE ADCSRB ADTS ( ADTS ) ADC SREG I Figure 40. ADC ADTS[2:0] PRESCALER START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE CLKADC CONVERSION LOGIC EDGE DETECTOR ADC ADC ADC ADCSRA ADSC "1" ADC ADIF ADCSRA ADSC "1" ADSC ADSC "1" 77 2535D-AVR-04/04 Figure 41. ADC ADEN START CK Reset 7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE 50 kHz 200 kHz 10 ADC 200 kHz ADC ADCADCSRADPS 100 kHz ADC ADCSR ADEN ADC ADEN ADEN ADCSR ADSC ADEN 13 ADC ADC (ADCSRA ADEN ) 25 ADC ADC 1.5 ADC ADC 14.5 ADC ADC ADC ADIF ADSC ( ) ADSC ADC ADC CPU ADSC 1 Table 36 78 ATTINY13 2535D-AVR-04/04 CK/128 CK/16 CK/32 CK/64 CK/2 CK/4 CK/8 ATTINY13 Figure 42. ADC ( ) First Conversion Next Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result MUX and REFS Update Sample & Hold Conversion Complete MUX and REFS Update Figure 43. ADC One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update Figure 44. ADC One Conversion Next Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset Prescaler Reset 79 2535D-AVR-04/04 Figure 45. ADC One Conversion 11 12 13 Next Conversion 1 2 3 4 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result Conversion Complete Sample & Hold MUX and REFS Update Table 36. ADC & ( ) 13.5 1.5 2 ( ) 25 13 13.5 80 ATTINY13 2535D-AVR-04/04 ATTINY13 ADMUXMUXnREFS1:0CPU ADC ADC ADSCADC ADSC ADC ADMUX ADMUX ADATE ADEN ADMUX ADMUX 1. ADATE ADEN 2. ADC 3. ADMUX ADC ADC ADSC "1" ADC ADSC "1" ADC 81 2535D-AVR-04/04 ADC ADC (VREF)ADC VREF 0x3FFVREF VCC 1.1V AREF ADC ADC CPUI/O ADC 1. ADC ADC 2. ADC ( ) CPU ADC 3. ADC ADCCPU ADC ADC CPU ADC ADC CPU ( ADC )ADC ADEN "0" ADC 82 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 46. ADC ADCn ADC ( ) (S/H) ADC10 k S/H S/H (fADC/2) ADC Figure 46. IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2 83 2535D-AVR-04/04 (EMI) 1. 2. ADC CPU 3. ADC ADC n ADC GND VREF 2n (LSBs) 0 2n-1 * (0x000 0x001) (0.5 LSB) 0 LSB Figure 47. Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage * (0x3FE 0x3FF) ( 1.5 LSB) 0 LSB Figure 48. Output Code Gain Error Ideal ADC Actual ADC VREF Input Voltage 84 ATTINY13 2535D-AVR-04/04 ATTINY13 * (INL) INL0 LSB Figure 49. (INL) Output Code * (DNL) ( ) (1 LSB) 0 LSB INL Ideal ADC Actual ADC VREF Input Voltage Figure 50. (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage * * (1 LSB) 0.5 LSB ( ) 0.5 LSB ADC (ADIF ) ADC (ADCL, ADCH) V IN 1024 ADC = -------------------------V REF 85 2535D-AVR-04/04 VIN VREF ( P86Table 37 P86Table 38) 0x000 0x3FF 1LSB ADC ADMUX Bit / 7 - R 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 - R 0 3 - R 0 2 - R 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX * Bit 7 - Res: * Bit 6 - REFS0: Table 37 (ADCSRA ADIF ) Table 37. ADC REFS0 0 1 VCC * Bit 5 - ADLAR: ADC ADLARADCADC ADLAR ADLAR ADC P87"ADC - ADCL ADCH" * Bits 4:2 - Res: * Bits 1:0 - MUX1:0: ADC Table 38 (ADCSRA ADIF ) Table 38. MUX1..0 00 01 10 11 ADC0 (PB5) ADC1 (PB2) ADC2 (PB4) ADC3 (PB3) ADC A ADCSRA Bit / 7 ADEN R/W 0 6 ADSC R/W 0 5 ADATE R/W 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSRA * Bit 7 - ADEN: ADC ADENADC ADC ADC * Bit 6 - ADSC: ADC 86 ATTINY13 2535D-AVR-04/04 ATTINY13 ADSC ADC ADSC ( ADC ADSC ADC ADSC) 25 ADC 13 ADC ADSC "1"ADSC * Bit 5 - ADATE: ADC ADATE ADC ADC ADCSRB ADC ADTS * Bit 4 - ADIF: ADC ADC ADIF ADIE SREG I ADC ADIF 1 ADIF ADCSRA SBI CBI * Bit 3 - ADIE: ADC ADIE SREG I ADC * Bits 2:0 - ADPS2:0: ADC ADC Table 39. ADC ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 2 2 4 8 16 32 64 128 ADC ADCL ADCH ADLAR = 0 Bit 15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL ADLAR = 1 Bit 15 ADC9 14 ADC8 13 ADC7 12 ADC6 11 ADC5 10 ADC4 9 ADC3 8 ADC2 ADCH 87 2535D-AVR-04/04 ADC1 7 R R 0 0 ADC0 6 R R 0 0 - 5 R R 0 0 - 4 R R 0 0 - 3 R R 0 0 - 2 R R 0 0 - 1 R R 0 0 - 0 R R 0 0 ADCL ADC ADCL ADC ADCH 8 ADCH ADCL ADCH ADMUX ADLAR MUXn ADLAR 1 ( ) * ADC9:0: ADC ADC P85"ADC " ADC B ADCSRB Bit / 7 - R 0 6 ACME R/W 0 5 - R 0 4 - R 0 3 - R 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB * Bits 7, 5..3 - Res: * Bits 2:0 - ADTS2:0: ADC ADCSRA ADATE "1" ADTS2:0 ADC ADATE ADTS2:0 ADCSRA ADEN ADC (ADTS[2:0]=0) Table 40. ADC ADTS2 0 0 0 0 1 1 1 ADTS1 0 0 1 1 0 0 1 ADTS0 0 1 0 1 0 1 0 0 T/C A T/C T/C B 0 DIDR0 Bit / 7 - R 0 6 - R 0 5 ADC0D R/W 0 4 ADC2D R/W 0 3 ADC3D R/W 0 2 ADC1D R/W 0 1 AIN1D R/W 0 0 AIN0D R/W 0 DIDR0 * Bits 5..2 - ADC3D..ADC0D: ADC3..0 88 ATTINY13 2535D-AVR-04/04 ATTINY13 "1" ADC "0" ADC3..0 89 2535D-AVR-04/04 * * * * * * * * * * RESET (C HLL) ( ) debugWIRE CPU AVR debugWIRE DWEN debugWIRE RESET ( ) I/O Figure 51. The debugWIRE 1.8 - 5.5V VCC dW dW(RESET) GND Figure 51 debugWIRE MCU debugWIRE CKSEL debugWIRE * * * * dW/(RESET) 10k debugWIRE RESET VCC debugWIRE RESET debugWIRE AVR AVR Studio(R) BREAK BREAK 90 ATTINY13 2535D-AVR-04/04 ATTINY13 BREAK Flash AVR Studio(R) debugWIRE Flash debugWIRE debugWIRE (dW) (RESET) debugWIRE CPU debugWIRE I/O CPU I/O debugWIRE DWEN debugWire DWEN I/O debugWIRE debugWire DWDR debugWire Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 DWDR R/W 0 DWDR[7:0] DWDR MCU debugWIRE 91 2535D-AVR-04/04 Flash MCU ( ) SPM 1 * * * * * * 2 ( ) 1 Boot Loader - - 2 SPM Z "00000011" SPMCSR SPMR1 R0 Z PCPAGE Z * ( ) CPU Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE SPM EEPROM Z "00000101" SPMCSR SPMR1 R0 Z PCPAGE Z * CPU 92 ATTINY13 2535D-AVR-04/04 ATTINY13 Flash Z SPM Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0 Flash (P99Table 46) Figure 52 Boot Loader LPMZ ZLSB ( Z0) Figure 52. SPM(1) BIT Z - REGISTER PCMSB PROGRAM COUNTER PCPAGE 15 ZPCMSB ZPAGEMSB 10 0 PAGEMSB PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. Figure 52 P99Table 46 93 2535D-AVR-04/04 (SPM) SPMCSR Boot Loader SPMCSR Bit 7 - 6 - 5 - 4 3 2 1 PGERS 0 SELFPRGEN SPMCSR CTPB RFLB PGWRT / R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bits 7..5 - Res: * Bit 4 - CTPB: CTPB * Bit 3 - RFLB: SPMCSR RFLB SELFPRGEN LPM ( Z Z0) P95"EEPROM SPMCSR " * Bit 2 - PGWRT: SELFPRGEN SPM Z R1 R0 SPM PGWRT CPU * Bit 1 - PGERS: SELFPRGEN SPM Z R1 R0 SPM PGERS CPU * Bit 0 - SELFPRGEN: SPM CTPB RFLB PGWRT PGERS SPM SELFPRGEN SPM R1:R0 Z Z LSB SPM SPM SELFPRGEN SELFPRGEN "10001" "01001" "00101" "00011" "00001" 94 ATTINY13 2535D-AVR-04/04 ATTINY13 EEPROM SPMCSR EEPROM Flash SPMCSR EECR EEWE 0x0001 Z SPMCSR RFLB SELFPRGEN RFLB CPU LPM CPU LPM CPU SPM RFLB SELFPRGEN RFLB SELFPRGEN LPM Bit Rd 7 - 6 - 5 - 4 - 3 - 2 - 1 LB2 0 LB1 0x0000ZSPMCSRRFLB SELFPRGEN SPMCSR CPU LPM (FLB) P98Table 45 Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0 0x0003 Z SPMCSR RFLB SELFPRGEN SPMCSR CPU LPM (FHB) P98Table 44 Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0 / "0" / "1" 95 2535D-AVR-04/04 Flash VCC CPU Flash Flash Flash Flash Flash CPU Flash ( ) 1. AVR RESET BOD 2. AVR CPU SPMCSR Flash SPM Flash RC Flash Table 41 CPU Flash Table 41. SPM Flash ( SPM ) 3.7 ms 4.5 ms 96 ATTINY13 2535D-AVR-04/04 ATTINY13 ATTINY13 The ATTINY13 2 ("0") ("1") Table 43 "1" DWEN debugWIRE DWEN debugWIRE Table 42. (1) 7 6 5 4 3 2 LB2 LB1 Note: 1 0 - - - - - - 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1. "1" "0" (1)(2) Table 43. LB 1 2 LB2 1 1 LB1 1 0 Flash EEPROM (1) debugWire Flash EEPROM (1) debugWire 3 Notes: 0 0 1. LB1 LB2 2. "1" , "0" 97 2535D-AVR-04/04 ATTINY13 Table 44 Table 45 "0" Table 44. - - - SELFPRGEN DWEN(3) BODLEVEL1 BODLEVEL0 RSTDISBL Notes: 1. 2. 3. 4. (4) (1) (1) 7 6 5 4 3 2 1 0 - - - debugWire BOD BOD 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) BODLEVEL P32Table 13 RSTDISBL DWEN P48" B " DWEN P97" " RSTDISBL Table 45. SPIEN (1) 7 6 5 4 3 2 1 0 EEPROM 8 0 ( SPI ) 1 ( EEPROM ) 1 ( ) 0 ( ) 1 ( )(3) 0 ( )(3) 1 ( )(4) 0 ( )(4) EESAVE WDTON(2) CKDIV8(5) SUT1 SUT0 CKSEL1 CKSEL0 Notes: 1. 2. 3. 4. SPI SPIEN P37" - WDTCR" SUT1..0 P22Table 5 CKSEL1..0 RC 9.6 MHz P22Table 4 5. P24" " 1(LB1) 98 ATTINY13 2535D-AVR-04/04 ATTINY13 EESAVE Atmel ATTINY13 1. 0x000: 0x1E ( Atmel ) 2. 0x001: 0x90 ( 1KB Flash ) 3. 0x002: 0x07 ( 0x001 0x90 ATTINY13) ATTINY13 RC 0x000 OSCCAL RC Table 46. Flash Flash 512 (1K ) 16 PCWORD PC[3:0] 32 PCPAGE PC[8:4] PCMSB 8 Table 47. EEPROM EEPROM 64 4 PCWORD EEA[1:0] 16 PCPAGE EEA[5:2] EEAMSB 5 99 2535D-AVR-04/04 RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P100Table 48 SPI SPI SPI Figure 53. (1) +1.8 - 5.5V RESET PB5 VCC PB2 SCK PB1 MISO GND PB0 MOSI Notes: 1. CLKI Table 48. MOSI MISO SCK PB0 PB1 PB2 I/O I O I EEPROM MCU ( ) EEPROM 0xFF CKSEL (SCK) fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > ck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU >f 100 ATTINY13 2535D-AVR-04/04 ATTINY13 ATTINY13 SCK ATTINY13 SCK Figure 54 Figure 55 ATTINY13 ( Table 50 4 ) 1. RESET SCK "0" VCC GND SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. (0x53) 4 0x53 RESET 4. Flash 5LSB 8 tWD_FLASH ( Table 49.) Flash 5. A: EEPROM EEPROM tWD_EEPROM ( Table 49) 0xFF B: EEPROM EEPROM 2 LSB EEPROM EEPROM 4 MSB EEPROM EEPROM tWD_EEPROM ( Table 47.) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC 101 2535D-AVR-04/04 . Table 49. Flash EEPROM tWD_FLASH tWD_EEPROM tWD_ERASE tWD_FUSE 4.5 ms 4.0 ms 4.0 ms 4.5 ms Figure 54. SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE MSB LSB MSB LSB 102 ATTINY13 2535D-AVR-04/04 ATTINY13 Table 50. 1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx 0000 000a 000x xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxxx bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM b EEPROM b i i EEPROM EEPROM b EEPROM "0" "1" P97Table 42 "0" P97Table 42 b o "0" "1" "0" "1" P80Table 36 "0" "1" "0" "1" P80Table 36 o = "1" "0" EEPROM EEPROM EEPROM ( ) EEPROM( ) RDY/BSY Note: 0100 1100 1010 0000 1100 0000 1100 0001 0000 000a 000x xxxx 000x xxxx 0000 0000 bbbb xxxx xxbb bbbb xxbb bbbb 0000 00bb xxxx xxxx oooo oooo iiii iiii iiii iiii 1100 0010 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 0101 0000 0101 1000 0011 1000 1111 0000 00xx xxxx 0000 0000 111x xxxx 000x xxxx 1010 0000 1010 1000 0000 0000 0000 1000 000x xxxx 0000 0000 xxbb bb00 xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii oooo oooo oooo oooo oooo oooo xxxx xxxo a = b = H = 0 - 1 - o = i = x = 103 2535D-AVR-04/04 Figure 55. MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH Table 51. TA = -40C-85C, VCC = 1.8 - 5.5V ( ) 1/tCLCL tCLCL 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Note: (ATTINY13V) (ATTINY13V) (ATTINY13L, VCC = 2.7 - 5.5V) (ATTINY13L, VCC = 2.7 - 5.5V) (ATTINY13, VCC = 4.5V - 5.5V) (ATTINY13, VCC = 4.5V - 5.5V) SCK SCK SCK MOSI SCK MOSI MISO SCK 1. fck < 12 MHz 2 tCLCLfck >= 12 MHz 3 tCLCL 0 1,000 0 104 0 67 2 tCLCL* 2 tCLCL* tCLCL 2 tCLCL TBD TBD TBD 16 9.6 1 MHz ns MHz ns MHz ns ns ns ns ns ns ATTINY13 Flash EEPROM 104 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 56. +11.5 - 12.5V PB5 (RESET) SERIAL CLOCK INPUT +1.8 - 5.5V VCC PB2 SCK PB3 (CLKI) PB1 MISO GND PB0 MOSI Table 52. SDI SII SDO SCI PB0 PB1 PB2 PB3 I/O I I O I ( 220ns) (SCI) 220 ns Table 53. SDI SII SDO Prog_enable[0] Prog_enable[1] Prog_enable[2] 0 0 0 105 2535D-AVR-04/04 ATTINY13 ( Table 55) 1. VCC GND 4.5 - 5.5V 2. RESET "0" SCI 6 3. Table 53 Prog_enable "000" 100 ns 4. RESET VHVRST - 5.5V Prog_enable tHVRST Prog_enable 5. Prog_enable Prog_enable[2]/SDO tHVRST Prog_enable[2] 6. 50 s SDI/SII Table 54. VCC 4.5V 5.5V RESET VHVRST 11.5V 11.5V Prog_enable tHVRST 100 ns 100 ns * * * 0xFF EEPROM (EESAVE) Flash 0xFF Flash 256 EEPROM 256 Flash EEPROM(1) Flash / EEPROM Note: 1. EESAVE EEPROM 1. " " ( Table 55) 2. Instr. 3 SDO 3. " " 106 ATTINY13 2535D-AVR-04/04 ATTINY13 Flash Flash P103Table 50 Flash Flash 1. " Flash" ( Table 55) 2. Flash 3. Flash Instr. 3 SDO 4. 2 3 Flash 5. " " ATTINY13 Figure 58 Figure 59 Table 56 Figure 57. Flash PCMSB PROGRAM COUNTER PCPAGE PAGEMSB PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Figure 58. SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 MSB LSB SCI PB3 0 1 2 3 4 5 6 7 8 9 10 107 2535D-AVR-04/04 EEPROM EEPROM P104Table 51 EEPROM EEPROM ( Table 55) 1. " EEPROM" 2. EEPROM 3. EEPROM Instr. 2 SDO 4. 2 3 EEPROM 5. " " Flash Flash ( Table 55) 1. " Flash" 2. Flash SDO EEPROM EEPROM ( Table 55) 1. " EEPROM" 2. EEPROM SDO / Table 55 Table 55 SCI "0" RESET "1" VCC 108 ATTINY13 2535D-AVR-04/04 ATTINY13 Table 55. ATTINY13 SDI Chip Erase SII SDO Load "Write Flash" Command SDI SII SDO SDI SII Load Flash Page Buffer SDO SDI SII SDO Load Flash High SDI Address and SII Program Page SDO Load "Read Flash" Command SDI SII SDO SDI SII Read Flash Low SDO and High Bytes SDI SII SDO Load "Write EEPROM" Command Load EEPROM Page Buffer SDI SII SDO SDI SII SDO SDI SII SDO SDI SII Write EEPROM Byte SDO SDI SII SDO Load "Read EEPROM" Command SDI SII SDO Instr.1/5 0_1000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0001_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ bbbb_bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0010_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0001_0001_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_00bb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_00bb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_0000_0011_00 0_0100_1100_00 x_xxxx_xxxx_xx Instr.2/6 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx Instr.3 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr.4 Instr. 3 SDO Flash 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_dddd_dddd_00 0_0011_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1101_00 x_xxxx_xxxx_xx Instr. 1 - 5 Note 1 Instr 5. Instr. 3 SDO Flash Instr. 2 - 3 Flash 256 Instr. 1 Note 1 Flash 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 p_pppp_pppx_xx EEPROM 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr 5 - 6. 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqqx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr. 1, 3 - 6 256 Instr. 2 Instr. 1 - 4 Note 2 Instr. 2 SDO EEPROM Instr. 1 - 2 EEPROM Instr. 1 - 5 Instr. 5 SDO Note 3 Program EEPROM Page Instr. 5 EEPROM 109 2535D-AVR-04/04 Table 55. ATTINY13 (Continued) Read EEPROM Byte SDI SII SDO SDI SII SDO Instr.1/5 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0100_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0010_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx Instr.2/6 0_aaaa_aaaa_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_A987_6543_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_000F_EDCB_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0021_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1010_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_00bb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0000_1100_00 x_xxxx_xxxx_xx Instr.3 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 A_9876_543x_xx 0_0000_0000_00 0_0111_1110_00 x_xxFE_DCBx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_x21x_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx Instr.4 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqq0_00 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr. 1, 3 - 4 256 Instr. 2 Instr. 4 SDO A - 3 = "0" Instr. 4 SDO F - B = "0" Instr. 4 SDO 2 - 1 = "0" Write Fuse Low Bits SDI Write Fuse High SII Bits SDO SDI Write Lock Bits SII SDO Read Fuse Low Bits SDI SII SDO A - 3 = "0" SDI Read Fuse High SII Bits SDO SDI Read Lock Bits SII SDO Read Signature Bytes SDI SII SDO F - B = "0" 2, 1 = "0" 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqqx_xx 0_0000_0000_00 0_0111_1100_00 p_pppp_pppx_xx Instr 2 4 SDI Read SII Calibration Byte SDO Load "No Operation" Command SDI SII SDO Note: a = b = d = e = p = q = x = 1 = 12 = 23 = CKSEL0 4 = CKSEL1 5 = SUT0 6 = SUT1 7 = CKDIV8 8 = WDTON 9 = EESAVE A = SPIEN B = RSTDISBL C = BODLEVEL0 D= BODLEVEL1 E = MONEN F = SELFPRGEN 1. 256 (bbbb_bbbb) 2. 256 (bbbb_bbbb) 3. EEPROM EEPROM EEPROM EEPROM Notes: 110 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 59. CC CK Table 56. VCC = 5.0V 10% ( ) 110 110 50 50 16 2.5 tSHSL tSLSH tIVSH tSHIX tSHOV tWLWH_PFB r SCI (PB3) SCI (PB3) SDI (PB0) SII (PB1) SCI (PB3) SCI (PB3) SDI (PB0) SII (PB1) SCI (PB3) SDO (PB2) Instr. 3 ns ns ns ns ns ms 111 2535D-AVR-04/04 * ........................................................ -55C +125C ........................................................ -65C +150C RESET............ -0.5V VCC+0.5V RESET .................................. -0.5V +13.0V .................................................................... 6.0V I/O DC ............................................. 40.0 mA *NOTICE: " " VCC GND DC .................................... 200.0 mA VIL VIH VIH2 VOL VOL1 VOH VOH1 IIL IIH RRST Rpu TA = -40C -85C, VCC = 1.8V -5.5V ( )(1) (PB5 PB1 PB0) (4) RESET RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V Vcc = 5.5V, ( ) Vcc = 5.5V, ( ) -0.5 0.6VCC(3) 0.9VCC(3) 0.2VCC VCC +0.5 VCC +0.5 0.7 0.5 0.7 0.5 V V V V V V V V V V V (4) (PB4 PB3 PB2) (5) (PB5 PB1 PB0) (5) (PB4 PB3 PB2) I/O I/O Reset I/O 4.2 2.5 4.2 2.5 1 1 30 20 80 50 0.55 3.5 12 0.08 0.41 1.6 <5 < 0.5 0.25 1.5 5.5 16 1 A A k k mA mA mA mA mA mA A A 1MHz, VCC = 2V 4MHz, VCC = 3V ICC 8MHz, VCC = 5V 1MHz, VCC = 2V 4MHz, VCC = 3V 8MHz, VCC = 5V WDT , VCC = 3V WDT , VCC = 3V 112 ATTINY13 2535D-AVR-04/04 ATTINY13 Notes: 1. AVR 2. " " 3. " " 4. ( ) I/O ( PB5PB1:0 20 mA CC = 5V 10 V mA VCC = 3V PB4:210 mA VCC = 5V 5 mAVCC = 3V) 1] IOL 60 mA IOL VOL 5. ( ) I/O ( PB5PB1:0 20 mA CC = 5V 10 V mA VCC = 3V PB4:210 mA VCC = 5V 5 mAVCC = 3V) : 1] IOL 60 mA IOL VOL Figure 60. V IH1 V IL1 Table 57. VCC=1.8-5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 1000 400 400 2.0 2.0 2 1 VCC=2.7-5.5V 0 104 50 50 1.6 1.6 2 9.6 VCC=4.5-5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s % tCLCL 113 2535D-AVR-04/04 VCC VCC. Figure 61 Figure 62 1.8V < VCC < 2.7V 2.7V < VCC < 4.5V VCC Figure 61. ATTINY13V VCC 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 62. ATTINY13 VCC 20 MHz 10 MHz Safe Operating Area 2.7V 4.5V 5.5V 114 ATTINY13 2535D-AVR-04/04 ATTINY13 ADC Table 58. ADC -40C - 85C VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 1 MHz ( INL DNL ) VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 1 MHz (INL) VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 200 kHz VREF = 4VVCC = 4V ADC = 200 kHz 13 50 GND 38.5 1.0 1.1 100 1.2 2 (1) (1) (1) 10 Bits LSB 3 LSB 1.5 LSB 2.5 LSB 1 LSB (DNL) 0.5 LSB 2.5 LSB VIN VINT RAIN Notes: 1. 1.5 260 1000 VREF LSB s kHz V kHz V M 115 2535D-AVR-04/04 ATTINY13 I/O I/O I/O I/O CL*VCC*f CL = VCC = f = I/O Figure 63. (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 1.2 1 5.5 V 5.0 V 0.8 ICC (mA) 4.5 V 4.0 V 3.3 V 0.6 0.4 2.7 V 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 116 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 64. (1 - 24 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 24 MHz 18 16 14 12 ICC (mA) 5.5V 5.0V 4.5V 4.0V 10 8 6 4 2 0 0 2 4 6 3.3V 2.7V 1.8V 8 10 12 14 16 18 20 22 24 Frequency (MHz) Figure 65. VCC ( RC 9.6MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 9.6 MHz 8 7 6 5 ICC (mA) 85 C -40 C 25 C 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 117 2535D-AVR-04/04 Figure 66. VCC ( RC 4.8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4.8 MHz 4.5 4 3.5 3 ICC (mA) 25 C -40 C 85 C 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 67. VCC ( WDT 128 kHz) ACTIVE SUPPLY CURRENT vs. V CC INTERNAL WD OSCILLATOR, 128 KHz 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 C 25 C 85 C ICC (mA) VCC (V) 118 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 68. VCC (32 kHz ) ACTIVE SUPPLY CURRENT vs. V CC 32 kHz EXTERNAL CLOCK 0.04 0.035 0.03 0.025 ICC (mA) 25 C 85 C 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 69. (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (0.1 - 1.0 MHz) 0.9 0.8 0.7 0.6 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 119 2535D-AVR-04/04 Figure 70. (1 - 24 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 24 MHz 12 5.5V 10 5.0V 4.5V 8 ICC (mA) 6 4.0V 3.3V 4 2 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 22 24 Frequency (MHz) Figure 71. VCC ( RC 9.6 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 9.6 MHz 2.5 2 85 C 25 C -40 C ICC (mA) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 120 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 72. VCC ( RC 4.8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4.8 MHz 1.2 1 85 C 25 C -40 C 0.8 ICC (mA) 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 73. VCC ( RC 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL WD OSCILLATOR, 128 KHz 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 C 25 C 85 C ICC (mA) VCC (V) 121 2535D-AVR-04/04 Figure 74. VCC (32 kHz ) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL CLOCK 10 9 8 7 85 C 25 C -40 C ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 75. VCC ( ) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 1.8 1.6 1.4 1.2 85 C ICC (uA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 C 25 C VCC (V) 122 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 76. VCC ( ) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 10 9 8 7 -40 C 85 C 25 C ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 77. I/O (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 160 140 85 C 120 25 C -40 C 100 IOP (uA) 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) 123 2535D-AVR-04/04 Figure 78. I/O (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7 80 85 C 70 60 25 C -40 C 50 IOP (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 79. (Reset) Reset (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 -40 C 100 25 C 85 C 80 IRESET (uA) 60 40 20 0 0 1 2 3 4 5 VRESET (V) 124 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 80. (Reset) Reset (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 2.7V 60 -40 C 50 25 C 85 C 40 IRESET (uA) 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 81. I/O ( VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, VCC = 5V 70 60 50 -40 C 25 C 85 C IOH (mA) 40 30 20 10 0 0 1 2 3 4 5 6 VOH (V) 125 2535D-AVR-04/04 Figure 82. I/O ( VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, VCC = 2.7V 25 -40 C 20 25 C 85 C IOH (mA) 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 83. I/O ( VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, VCC = 1.8V 7 25 C 6 -40 C 85 C 5 IOH (mA) 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) 126 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 84. I/O ( VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, VCC = 5V 50 45 -40 C 40 25 C 35 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 85 C IOL (mA) VOL (V) Figure 85. I/O ( VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Low Power Ports, VCC = 2.7V 20 18 -40 C 16 25 C 14 IOL (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 85 C 2.5 VOL (V) 127 2535D-AVR-04/04 Figure 86. I/O ( VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, 1.8V 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -40 C 25 C 85 C IOL (mA) VOL (V) Figure 87. I/O (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 5V 90 80 -40 C 70 60 25 C 85 C IOH (mA) 50 40 30 20 10 0 2 3 4 5 6 VOH (V) 128 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 88. I/O (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 35 30 25 -40 C 25 C 85 C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 89. I/O (VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 10 9 -40 C 25 C 8 7 85 C IOH (mA) 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) 129 2535D-AVR-04/04 Figure 90. I/O (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 100 90 80 70 -40 C 25 C 85 C IOL (mA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 91. I/O (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 40 35 -40 C 30 25 25 C 85 C IOL (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) 130 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 92. I/O (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 14 12 10 IOL (mA) -40 C 25 C 85 C 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2 Figure 93. Reset I/O - (VCC = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 5V 1.6 1.4 -40 C 1.2 25 C 1 IOH (mA) 85 C 0.8 0.6 0.4 0.2 0 2 3 4 5 VOH (V) 131 2535D-AVR-04/04 Figure 94. Reset I/O - (VCC = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 2.5 -40 C 2 25 C IOH (mA) 1.5 85 C 1 0.5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 95. Reset I/O - (VCC = 1.8V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 2.5 -40 C 2 25 C IOH (mA) 1.5 1 85 C 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) 132 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 96. Reset I/O - (VCC = 5V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 14 -40 C 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 25 C 85 C IOL (mA) VOL (V) Figure 97. Reset I/O - (VCC = 2.7V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 4.5 4 3.5 -40 C 25 C 3 85 C IOL (mA) 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 VOL (V) 133 2535D-AVR-04/04 Figure 98. Reset I/O - (VCC = 1.8V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 1.6 1.4 1.2 -40 C 25 C 1 IOL (mA) 85 C 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 99. I/O VCC (VIH, I/O '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3 85 C 25 C -40 C 2.5 2 Threshold (V) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 134 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 100. I/O VCC (VIL, I/O '0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 2.5 85 C 25 C -40 C 2 Threshold (V) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 101. I/O VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.45 0.4 -40 C 0.35 Input Hysteresis (V) 0.3 25 C 0.25 0.2 85 C 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 135 2535D-AVR-04/04 Figure 102. Reset I/O VCC (VIH,Reset '1') RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3 2.5 2 Threshold (V) -40 C 1.5 25 C 1 85 C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 103. Reset I/O VCC (VIL,Reset '0') RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 2 Threshold (V) 1.5 85 C 1 25 C 0.5 -40 C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 136 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 104. Reset VCC RESET PIN AS IO - PIN HYSTERESIS vs. VCC 0.7 0.6 -40 C 0.5 Input Hysteresis (V) 25 C 0.4 85 C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 105. Reset VCC (VIH,Reset '1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 2 Threshold (V) 1.5 -40 C 1 85 C 25 C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 137 2535D-AVR-04/04 Figure 106. Reset VCC (VIL,Reset '0') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 2 Threshold (V) 1.5 1 85 C 25 C -40 C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 107. Reset VCC RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 0.5 -40 C 0.4 Threshold (V) 0.3 85 C 0.2 25 C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 138 ATTINY13 2535D-AVR-04/04 ATTINY13 BOD Figure 108. BOD (BOD 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.5 Rising VCC 4.4 Threshold (V) 4.3 Falling VCC 4.2 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 109. BOD (BOD 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.9 Rising V CC 2.8 Threshold (V) 2.7 Falling V CC 2.6 -60 -40 -20 0 20 40 60 80 100 Temperature (C) 139 2535D-AVR-04/04 Figure 110. BOD (BOD 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V 1.9 Rising V CC 1.85 Threshold (V) 1.8 Falling V CC 1.75 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 111. VCC BANDGAP VOLTAGE vs. VCC 1.06 1.04 1.02 Bandgap Voltage (V) 85C 25C 1 0.98 0.96 0.94 0.92 1.5 2.5 3.5 4.5 5.5 -40C VCC (V) 140 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 112. (VCC = 5V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE VCC = 5V 0.008 0.007 Comparator Offset Voltage (V) 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 85 C 25 C -40 C Common Mode Voltage (V) Figure 113. (VCC= 2.7V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE VCC = 2.7V 0.003 0.0025 Comparator Offset Voltage (V) 85 C 25 C 0.002 -40 C 0.0015 0.001 0.0005 0 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3 141 2535D-AVR-04/04 Figure 114. 9.6MHz RC CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10.3 10.1 9.9 9.7 FRC (MHz) 9.5 5.5 V 9.3 4.5 V 9.1 2.7 V 8.9 8.7 8.5 -60 -40 -20 0 20 40 60 80 100 1.8 V Temperature (C) Figure 115. 9.6MHz RC VCC CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. VCC 11 10.5 85 C 10 FRC (MHz) 9.5 25 C -40 C 9 8.5 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 142 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 116. 9.6MHz RC Osccal CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 18 25 C 16 14 12 10 8 6 4 2 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 FRC (MHz) OSCCAL VALUE Figure 117. 4.8 MHz RC CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.1 5 4.9 F RC (MHz) 4.8 4.7 1.8 V 5.5 V 4.0 V 2.7 V 4.6 4.5 -60 -40 -20 0 20 Temperature (C) 40 60 80 100 143 2535D-AVR-04/04 Figure 118. 4.8 MHz RC VCC CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. VCC 5.2 85 C 5 FRC (MHz) 4.8 25 C -40 C 4.6 4.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 119. 4.8 MHz RC Osccal CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 10 9 8 7 FRC (MHz) 25 C 6 5 4 3 2 1 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 127 OSCCAL VALUE 144 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 120. 128 kHz VCC 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. VCC 120 -40 C 115 FRC (kHz) 25 C 110 105 85 C 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 121. 128 kHz 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 118 116 114 112 FRC (kHz) 110 1.8 V 108 106 104 102 100 -60 -40 -20 0 20 40 60 80 100 2.7 V 4.0 V 5.5 V Temperature (C) 145 2535D-AVR-04/04 Figure 122. BOD VCC BROWNOUT DETECTOR CURRENT vs. VCC 35 30 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 C 25 C 85 C ICC (uA) VCC (V) Figure 123. ADC VCC ADC CURRENT vs. VCC 350 -40 C 300 25 C 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 85 C ICC (uA) VCC (V) 146 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 124. VCC ANALOG COMPARATOR CURRENT vs. VCC 140 -40 C 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 25 C 85 C ICC (uA) VCC (V) Figure 125. VCC PROGRAMMING CURRENT vs. Vcc 4 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 C 25 C 85 C VCC (V) 147 2535D-AVR-04/04 Figure 126. VCC (0.1 - 1.0 MHz ) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 0.14 5.5 V 0.12 5.0 V 0.1 ICC (mA) 4.5 V 4.0 V 3.3 V 2.7 V 0.08 0.06 0.04 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 1.8 V Figure 127. VCC (1 - 24MHz ) RESET SUPPLY CURRENT vs. VCC 1 - 24 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 3.5 3 2.5 2 1.5 5.5V 5.0V 4.5V ICC (mA) 4.0V 1 3.3V 0.5 1.8V 0 0 2 4 6 8 10 12 2.7V 14 16 18 20 22 24 Frequency (MHz) 148 ATTINY13 2535D-AVR-04/04 ATTINY13 Figure 128. VCC RESET PULSE WIDTH vs. V 2500 CC 2000 Pulsewidth (ns) 1500 1000 500 0 1.8 2.1 2.5 2.7 3 3.3 VCC (V) 85 C 25 C -40 C 3.5 4 4.5 5 5.5 6 149 2535D-AVR-04/04 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 SREG SPL GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A DWDR OCR0B GTCCR CLKPR WDTCR EEARL EEDR EECR PORTB DDRB PINB PCMSK DIDR0 ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Bit 7 I - Bit 6 T - Bit 5 H - Bit 4 S - SP[7:0] - Bit 3 V - Bit 2 N - Bit 1 Z - Bit 0 C - P6 P8 - - - - - - - FOC0A INT0 INTF0 - - - PUD - FOC0B PCIE PCIF - - - SE - - - - - - CTPB SM1 - - - - OCIE0B OCF0B RFLB SM0 WDRF WGM02 T/C0 (8 ) - - OCIE0A OCF0A PGWRT - BORF CS02 - - TOIE0 TOV0 PGERS ISC01 EXTRF CS01 - - - - SELFPRGEN P52 P52 P69 P69 P94 P69 P48 P33 P65 P69 P22 T/C - A ISC00 PORF CS00 - COM0A1 COM0A0 COM0B1 COM0B0 DWDR[7:0] - - - - T/C- B TSM CLKPCE - - - - - - - - - - - WDTIF WDTIE WDP3 WDCE - - - - - - EEPM1 EEPM0 - - - - - - - - - - - - - PORTB5 DDB5 PINB5 PCINT5 ADC0D PORTB4 DDB4 PINB4 PCINT4 ADC2D - - - - - - - - - - - ACD - ADEN ACBG REFS0 ADSC ACO ADLAR ADATE ACI - ADIF ACIE - ADIE - - ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 PORTB3 DDB3 PINB3 PCINT3 ADC3D PORTB2 DDB2 PINB2 PCINT2 ADC1D PORTB1 DDB1 PINB1 PCINT1 EIN1D PORTB0 DDB0 PINB0 PCINT0 AIN0D EEPROM EEPROM EERIE EEMWE EEWE EERE WDE WDP2 WDP1 WDP0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 - - - PSR10 - - WGM01 WGM00 P68 P91 P69 P72 P24 P37 P14 P14 P15 P50 P50 P50 P53 P75, P88 P73 P86 P86 P87 P87 ADC ADC - ACME - - - - - - ADTS2 ADTS1 ADTS0 P88 150 ATTINY13 2535D-AVR-04/04 ATTINY13 Note: 1. 0 I/O 2. CBI SBI 0x00 - 0x1F SBIS SBIC 3. 1 AVR CBI SBI CBI SBI 0x00 - 0x1F 151 2535D-AVR-04/04 ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k k 1 2 (Z) (Z) Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd "0" "1" I/O "0" I/O "1" "1" "0" "1" "0" "1" "0" T "1" T "0" "1" "0" I/O I/O Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 # RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL 152 ATTINY13 2535D-AVR-04/04 ATTINY13 ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH Rd Rd Rd s s Rr, b Rd, b T T 2 2 SREG T SREG T SREG SREG Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (z) R1:R0 Rd P P Rr STACK Rr Rd STACK Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr SRAM SRAM I/O I/O (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only MCU NOP SLEEP WDR BREAK None None None 153 2535D-AVR-04/04 (MHz) ATTINY13V-10PI ATTINY13V-10PJ(2) ATTINY13V-10SI ATTINY13V-10SJ(2) ATTINY13V-10SSI ATTINY13V-10SSJ(2) ATTINY13-20PI ATTINY13-20PJ(2) ATTINY13-20SI ATTINY13-20SJ(2) ATTINY13-20SSI ATTINY13-20SSJ(2) 8P3 8P3 8S2 8S2 S8S1 S8S1 8P3 8P3 8S2 8S2 S8S1 S8S1 10(3) 1.8 - 5.5 (-40C 85C) 20(3) 2.7 - 5.5 (-40C 85C) Notes: 1. wafer Atmel 2. 3. VCC P114" VCC " 8P3 8S2 S8S1 8- 0.300" PDIP 8- 0.209" EIAJ SOIC 8- 0.150" JEDEC SOIC 154 ATTINY13 2535D-AVR-04/04 ATTINY13 8P3 E E1 1 N Top View c eA End View D e D1 A2 A SYMBOL COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365 0.210 0.195 0.022 0.070 0.045 0.014 0.400 2 5 6 6 3 3 b2 b3 4 PLCS L D1 E E1 e eA L b 0.325 0.280 4 3 Side View 4 0.150 2 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B R 155 2535D-AVR-04/04 8S2 C 1 E E1 N L Top View End View e A SYMBOL b COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE A1 A A1 b C 1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0 1.27 BSC 2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8 4 2, 3 5 5 D D E1 E L Side View e Notes: 1. 2. 3. 4. 5. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm. 10/7/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. R 8S2 REV. C 156 ATTINY13 2535D-AVR-04/04 ATTINY13 S8S1 1 E1 E N Top View e b A A1 SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE D E E1 5.79 3.81 1.35 0.1 4.80 0.17 0.31 0.4 1.27 BSC 0o 6.20 3.99 1.75 0.25 4.98 0.25 0.51 1.27 8o Side View C A A1 D C L b L End View e Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 7/28/03 TITLE S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. A R 2325 Orchard Parkway San Jose, CA 95131 S8S1 157 2535D-AVR-04/04 ATTINY13 Rev. B ATTINY13 * * * * * Flash, EEPROM debugWIRE 1. 2.7 V EEPROM 0x00 0xFF 0xFF 2. Flash, EEPROM, R D Y / B S Y RDY/BSY D 3. OTP - - - 128 kHz (CKSEL[1..0] = 11) (SUT[1..0] = 00) Debugwire (DWEN = 0) RSTDISBL = 0 9.6 MHz (CKSEL[1..0] = 10) (SUT[1..0] = 00) Debugwire (DWEN = 0) RSTDISBL = 0 4.8 MHz (CKSEL[1..0] = 01) (SUT[1..0] = 00) Debugwire (DWEN = 0) RSTDISBL = 0 4. debugWIRE debugWIRE (DWEN = 0) EEPROM 5. 158 ATTINY13 2535D-AVR-04/04 ATTINY13 ATTINY13 Rev. A A 159 2535D-AVR-04/04 ATTINY13 Rev. 2535D-04/04 Rev. 2535C-02/04 1. 2. 3. 4. - 12MHz 10MHz - 24MHz 20MHz P103" " P114" VCC " P154" " Rev. 2535B-01/04 Rev. 2535C-02/04 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. C IAR WDTIF WDIF WDTIE WDIE P8" " P22" RC " P22" - OSCCAL" P35" " P80"ADC " P100" " P112" " P154" " P158" " rev. C Rev. 2535A-06/03 Rev. 2535B-01/04 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. P2Figure 2 P30Table 12, P39Table 17, P86Table 37 P113Table 57 P22" RC " P35" " P100Figure 53 P105Figure 56 P48"MCU - MCUCR" , P68"T/C B - TCCR0B" and P75" 0 - DIDR0" P112" " DC P114" VCC " P115"ADC " P116"ATTINY13 " P154" " P155" " P158" " EEAR EEARL 160 ATTINY13 2535D-AVR-04/04 |
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