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19-2362; Rev 1; 3/02
2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
General Description
The MAX3875A is a compact, low-power clock recovery and data retiming IC for 2.488Gbps SDH/SONET applications. The fully integrated phase-locked loop recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock. Differential PECL-compatible outputs are provided for both clock and data signals, and an additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTLcompatible loss-of-lock (LOL) monitor. The MAX3875A is designed for both section-regenerator and terminal-receiver applications in OC-48/STM-16 transmission systems. Its jitter performance exceeds all of the SONET/SDH specifications. This device operates from a single +3.3V to +5.0V supply over a -40C to +85C temperature range. The typical power consumption is only 400mW with a +3.3V supply. It is available in a 32-pin TQFP package, as well as in die form.
Features
o Exceeds ANSI, ITU, and Bellcore SONET/SDH Regenerator Specifications o 400mW Power Dissipation (at +3.3V) o Clock Jitter Generation: 0.003UIRMS o Single +3.3V or +5V Power Supply o Fully Integrated Clock Recovery and Data Retiming o Additional High-Speed Input Facilitates System Loopback Diagnostic Testing o Tolerates >2000 Consecutive Identical Digits o Loss-of-Lock Indicator o Differential PECL-Compatible Data and Clock Outputs
MAX3875A
Ordering Information
PART MAX3875AEHJ MAX3875AE/D TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFP Dice*
Applications
SDH/SONET Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects 2.488Gbps ATM Receiver Digital Video Transmission SDH/SONET Test Equipment
* Dice are designed to operate over this range, but are tested and guaranteed at TA = +25C only. Contact factory for availability. Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V +3.3V PHOTODIODE VCC 0.01F 0.01F VCC PHADJ+ PHADJ- LOL SDO+ SDO82 SDISLBISLBI+ SIS FIL+ FILSCLKO+ SCLKO82 82 82 +3.3V MAX3885 130 130 1:16 DESERIALIZER 130 130 TTL +3.3V +3.3V
MAX3866
IN
OUT+
SDI+
PRE/POSTAMPLIFIER LOP TTL OUT-
MAX3875A
SYSTEM LOOPBACK
TTL
1F
________________________________________________________________ Maxim Integrated Products
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3875A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +7.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ...........(VCC - 0.5V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............10mA PECL Output Voltage (SDO+, SDO-, SCLKO+, SCLKO-) .......................(VCC + 0.5V) PECL Output Current, (SDO+, SDO-, SCLKO+, SCLKO-).....56mA Voltage at LOL, SIS, PHADJ+, PHADJ-, FIL+, FIL- .................................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) TQFP (derate 16.1mW/C above +85C) ........................1.0W Operating Temperature Range MAX3875EHJ..................................................-40C to +85C Operating Junction Temperature (die) ..............-55C to +150C Storage Temperature Range .............................-60C to +160C Processing Temperature (die) .........................................+400C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at +3.3V and TA = +25C.) (Note 1) PARAMETER Supply Current Differential Input Voltage (SDI, SLBI) Single-Ended Input Voltage (SDI, SLBI) Input Termination to VCC (SDI, SLBI) PECL Output High Voltage (SDO, SCLKO) PECL Output Low Voltage (SDO, SCLKO) TTL Input High Voltage (SIS) TTL Input Low Voltage (SIS) TTL Input Current (SIS) TTL Output High Voltage (LOL) TTL Output Low Voltage (LOL) VOH VOL SYMBOL ICC VID VIS RIN VOH VOL VIH VIL -10 2.4 TA = 0C to +85C TA = -40C TA = 0C to +85C TA = -40C VCC - 1.025 VCC - 1.085 VCC - 1.81 VCC - 1.83 2.0 0.8 +10 VCC 0.4 CONDITIONS Excluding PECL output termination Figure 1 50 VCC - 0.4 45 VCC - 0.88 VCC - 0.88 VCC - 1.62 VCC - 1.555 MIN TYP 122 MAX 167 800 VCC + 0.2 UNITS mA mVP-P V V V V V A V V
Note 1: Dice are tested at TA = +25C only.
tCK SDI+ SDI25mV MIN 400mV MAX SCLKO+ tCK-Q SDO
(SDI+) (SDI-)
VID
50mVP-P MIN 800mVP-P MAX
Figure 1. Input Amplitude 2
Figure 2. Output Clock-to-Q Delay
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at +3.3V and TA = +25C.) (Note 2) PARAMETER Serial Output Clock Rate Clock-to-Q Delay Jitter Peaking Jitter Transfer Bandwidth JP JBW f = 70kHz Jitter Tolerance f = 100kHz f = 1MHz f = 10MHz (Note 3) Jitter Generation Clock Output Edge Speed Data Output Edge Speed Tolerated Consecutive Identical Digits Input Return Loss (SDI, SLBI) 100kHz to 2.5GHz 2.5GHz to 4.0GHz JGEN Jitter BW = 12kHz to 20MHz 20% to 80% 20% to 80% 1.91 1.76 0.41 0.21 Figure 2 f 2MHz 1.1 3.6 2.75 0.67 0.45 0.003 0.026 70 108 2000 -17 -15 0.006 0.056 UIRMS UIP-P ps ps bits dB UIP-P 110 SYMBOL CONDITIONS MIN TYP 2.488 290 0.1 2.0 MAX UNITS Gbps ps dB MHz
MAX3875A
Note 2: AC characteristics are guaranteed by design and characterization. Note 3: See Typical Operating Characteristics for worst-case distribution.
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT)
MAX3875A toc01
RECOVERED CLOCK JITTER
PRBS = 215 - 1
MAX3875A toc02
JITTER TOLERANCE
MAX3875A toc03
10
INPUT JITTER (UIP-P)
223 - 1 PATTERN VIN = 20mVP-P
TA = +85C
DATA
1 BELLCORE MASK
CLOCK RMS = 1.2ps 0.1 100ps/div 10ps/div PRBS = 223 - 1 50mVP-P INPUT 10k 100k 1M 10M JITTER FREQUENCY (Hz)
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3875A
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
JITTER TOLERANCE vs. INPUT VOLTAGE
MAX3875A toc04
DISTRIBUTION OF JITTER TOLERANCE
MAX3875A toc05a
JITTER TRANSFER
0 -0.3 JITTER TRANSFER (dB) -0.6 -0.9 -1.2 -1.5 -1.8 -2.1 -2.4 -2.7 PRBS = 223 - 1 1k 10k 100k 1M 10M -3.0 BELLCORE MASK
MAX3875A toc05
0.8 0.7 JITTER TOLERANCE (UIP-P) 0.6 0.5 0.4 0.3 0.2 JITTER FREQUENCY = 5MHz JITTER FREQUENCY = 1MHz
30 25 PERCENT OF UNITS (%) 20 15 10 5 MEAN = 0.41 = 0.028 fJITTER = 10MHz VCC = +3.0V TA = -40C
0.3
0.1 0 1
PRBS = 223 - 1 0 10 100 1000 0.20 0.34 0.48 0.62 INPUT VOLTAGE (mVP-P) JITTER TOLERANCE (UIP-P)
JITTER FREQUENCY (Hz)
BIT ERROR RATE vs. INPUT VOLTAGE
MAX3875A toc06
SUPPLY CURRENT vs. TEMPERATURE
140 SUPPLY CURRENT (mA) 135 130 125 VCC = +3.3V 120 115 VCC = +5.0V
MAX3875A toc07
10-3 10-4 10-5 BIT ERROR RATE 10-6 10-7 10-8 10-9 PRBS = 223 - 1 10-10 6.0 6.1 6.2 6.3 6.4 6.5
145
110 105 6.6 -50 -25 0 25 50 75 100
INPUT VOLTAGE (mVP-P)
AMBIENT TEMPERATURE (C)
Pin Description
PIN 1, 2, 8, 9, 10, 16, 26, 29, 32 3, 6, 11, 14, 15, 17, 20, 21, 24 4 5 7 12 13 18 NAME GND Supply Ground FUNCTION
VCC SDI+ SDISIS SLBI+ SLBISCLKO-
Positive Supply Voltage Positive Data Input. 2.488Gbps serial data stream. Negative Data Input. 2.488Gbps serial data stream. Signal Input Selection, TTL. Low for normal data input. High for system loopback input. Positive System Loopback Input. 2.488Gbps serial data stream. Negative System Loopback Input. 2.488Gbps serial data stream. Negative Serial Clock Output, PECL, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-.
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
Pin Description (continued)
PIN 19 22 23 25 27 28 30 31 NAME SCLKO+ SDOSDO+ LOL PHADJPHADJ+ FILFIL+ FUNCTION Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+. Negative Data Output, PECL compatible, 2.488Gbps Positive Data Output, PECL compatible, 2.488Gbps Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10k pull-up resistor) Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. Negative Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-. Positive Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-.
MAX3875A
SIS
PHADJ+ PHADJ-
FIL+
FIL-
SDO+ SDI+ AMP SDIMUX SLBI+ AMP SLBILOL TTL PHASE AND FREQUENCY DETECTOR LOOP FILTER I VCO Q CML SCLKO+ SCLKOD CK Q CML SDO-
MAX3875A
Figure 3. Functional Diagram
Detailed Description
The MAX3875A consists of a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, and PECL output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques.
800mVP-P. The bit error rate is better than 1 x 10-10 for input signals as small as 10mVp-p, although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information.
Phase Detector
The phase detector incorporated in the MAX3875A produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The external phase adjust pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment.
Input Amplifier
Input amplifiers are implemented for both the main data and system loopback inputs. These amplifiers accept a differential input amplitude from 50mV P-P up to
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3875A
Frequency Detector
The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector.
HO(j2f) (dB)
OPEN-LOOP GAIN
CF = 1.0F fZ = 2.6kHz
CF = 0.1F fZ = 26kHz
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor, CF, is required to set the PLL damping ratio. Refer to Design Procedure for guidelines on selecting this capacitor. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 1.2psRMS within a jitter bandwidth of 12kHz to 20MHz.
f (kHz) 1 10 100 1000
Figure 4. Open-Loop Transfer Function
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the MAX3875A frequency detector. A loss-of-lock condition is signaled immediately with a TTL low. When the PLL is frequency locked, LOL switches to TTL high in approximately 800ns. Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3875A. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal.
H(j2f) (dB) CF = 0.1F 0 CLOSED-LOOP GAIN -3 CF = 1.0F
Design Procedure
Setting the Loop Filter
The MAX3875A is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 1.1MHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 4 and 5 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to: fz = 1 2 60 CF
f (kHz) 1 10 100 1000
Figure 5. Closed-Loop Transfer Function
For an overdamped system (fZ/fL) < 0.25, the jitter peaking (MP) of a second-order system can be approximated by: f MP = 20log 1+ Z fL For example, using CF = 0.1F results in a jitter peaking of 0.2dB. Reducing CF below 0.01F may result in PLL instability. The recommended value for CF = 1.0F to guarantee a maximum jitter peaking of less than 0.1dB. CF must be a low TC, high-quality capacitor of type X7R or better.
()
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
Input and Output Terminations
The MAX3875A's digital outputs (SDO+, SDO-, SCLKO+, SCLKO-) are designed to interface with PECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50 to VCC - 2V can be used with fixed impedance transmission lines for proper termination. To ensure best performance, the differential outputs must have balanced loads. The input termination can be driven differentially, or can be driven single-ended by externally biasing SDI- or SLBI- to the center of the voltage swing.
System Loopback
The MAX3875A is designed to allow system loopback testing. The user can connect a serializer output in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3875A for system diagnostics. To select the SLBI inputs, apply a TTL logic high to the SIS pin.
MAX3875A
PECL Input Levels
When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50 termination (Figure 6). AC coupling is also required to maintain the input common-mode level.
Jitter Tolerance and Input Sensitivity Trade-Offs
When the received data amplitude is higher than 50mVP-P, the MAX3875A provides a typical jitter tolerance of 0.45UI at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UI, leaving a jitter allowance of 0.3UI for receiver preamplifier and postamplifier design. The BER is better than 1 x 10 -10 for input signals greater than 10mVP-P. At 10mVP-P, jitter tolerance will be degraded, but will still be above the SDH/SONET requirement. The user can make a trade-off between jitter tolerance and input sensitivity according to the specific application. Refer to the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Amplitude graphs.
Layout
The MAX3875A's performance can be significantly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to VCC as possible. Take care to isolate the input from the output signals to reduce feedthrough.
VCC
Applications Information
Consecutive Identical Digits (CID)
The MAX3875A has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 x 10-10. The CID tolerance is tested using a 213 - 1 PRBS, substituting a long run of zeros to simulate the worst case. A CID tolerance of 2000 bits is typical.
PECL LEVELS 0.1F SDI0.1F 25 SDI+
50
50
100
25
Phase Adjust
The internal clock is aligned to the center of the data eye. For specific applications this sampling position can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input voltages up to 1.5V. A simple resistor-divider with a bypass capacitor is sufficient to set these levels. When the PHADJ inputs are not used, they should be tied directly to VCC.
MAX3875A
Figure 6. PECL Input Interface
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3875A
Pin Configuration
PHADJ+ PHADJ-
Chip Topography
FIL+ GND PHADJ- LOL GND FIL- PHADJ+ GND
TOP VIEW
GND GND FIL+ FIL-
GND 26
32 GND GND VCC SDI+ SDIVCC SIS GND 1 2 3 4 5 6 7 8 9 GND
31
30
29
28
27
LOL 25 24 VCC 23 SDO+ 22 SDO21 VCC
VCC GND GND VCC SDI+ SDIVCC SIS GND SDO+ SDOVCC 0.072" VCC (1.828mm) SCLKO+ SCLKOVCC GND
MAX3875A
20 VCC 19 SCLKO+ 18 SCLKO17 VCC
10 GND
11 VCC
12 SLBI+
13 SLBI-
14 VCC
15 VCC
16 GND
GND
TQFP
SLBI+ VCC VCC VCC SLBI- N.C. N.C. 0.071" (1.803mm)
TRANSISTOR COUNT: 1515
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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