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GAL20VP8
High-Speed E2CMOS PLD Generic Array LogicTM Features
* HIGH DRIVE E2CMOS(R) GAL(R) DEVICE -- TTL Compatible 64 mA Output Drive -- 15 ns Maximum Propagation Delay -- Fmax = 80 MHz -- 10 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology * ENHANCED INPUT AND OUTPUT FEATURES -- Schmitt Trigger Inputs -- Programmable Open-Drain or Totem-Pole Outputs -- Active Pull-Ups on All Inputs and I/O pins * E CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * EIGHT OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs -- Programmable Output Polarity -- Architecturally Compatible with Standard GAL20V8 * PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- Ideal for Bus Control & Bus Arbitration Logic -- Bus Address Decode Logic -- Memory Address, Data and Control Circuits -- DMA Control * ELECTRONIC SIGNATURE FOR IDENTIFICATION
2
Functional Block Diagram
I/CLK I I IMUX
CLK
8 I 8 I
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (64 X 40)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I 8 I 8 OLMC
OE
OLMC
I/O/Q
I/O/Q
I I
I IMUX I/OE
Description
The GAL20VP8, with 64 mA drive capability and 15 ns maximum propagation delay time is ideal for Bus and Memory control applications. The GAL20VP8 is manufactured using Lattice Semiconductor's advanced E2CMOS process which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. System bus and memory interfaces require control logic before driving the bus or memory interface signals. The GAL20VP8 combines the familiar GAL20V8 architecture with bus drivers as its outputs. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The 64mA output drive eliminates the need for additional devices to provide bus-driving capability. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
I/CLK I/O/Q NC
DIP
1 24 I I I/O/Q
I I
25 I/O/Q I/O/Q
I
I
28
4 I I Vcc NC I I I 11 12 9 7 5
I
2
I
26
I I Vcc I I I I I I/OE 12 6
GAL 20VP8
18
I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q I/O/Q I/O/Q 13 I
GAL20VP8
Top View
14 16
23
I/O/Q NC
21
GND I/O/Q
19 18
I/O/Q
I/OE
I/O/Q
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
I/O/Q
I
I
NC
I
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
20vp8_03
1
Specifications GAL20VP8
GAL20VP8 Ordering Information
Commercial Grade Specifications
Tpd (ns)
15
Tsu (ns)
8
Tco (ns)
10
Icc (mA)
115 115
Ordering #
GAL20VP8B-15LP GAL20VP8B-15LJ GAL20VP8B-25LP GAL20VP8B-25LJ
Package
24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC
25
10
15
115 115
Part Number Description
XXXXXXXX _ XX X XX
GAL20VP8B Device Name Grade Blank = Commercial
Speed (ns) L = Low Power Power
Package P = Plastic DIP J = PLCC
2
Specifications GAL20VP8
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 and AC2 bit of each of the macrocells controls the input/output and totem-pole/open-drain configuration. These two global and 24 individual architecture bits define all possible configurations in a GAL20VP8. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits.
Compiler Support for OLMC
Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1(2) and pin 12(14) are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1(2) and pin 12(14) become dedicated inputs and use the feedback paths of pin 22(26) and pin 14(17) respectively. Because of this feedback path usage, pin 22(26) and pin 14(17) do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins (pins 17(20) and 19(23)) will not have the feedback option as these pins are always configured as dedicated combinatorial output. In addition to the architecture configurations, the logic compiler software also supports configuration of either totem-pole or opendrain outputs. The actual architecture bit configuration, again, is transparent to the user with the default configuration being the standard totem-pole output.
3
Specifications GAL20VP8
Registered Mode
In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page.
CLK
Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - AC2=1 defines totem pole output. - AC2=0 defines open-drain output. - Pin 1(2) controls common CLK for the registered outputs. - Pin 12(14) controls common OE for the registered outputs. - Pin 1(2) & Pin 12(14) are permanently configured as CLK & OE for registered output configuration.
D
Q Q
XOR
OE
Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - AC2=1 defines totem pole output. - AC2=0 defines open-drain output. - Pin 1(2) & Pin 12(14) are permanently configured as CLK & OE. for registered output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications GAL20VP8
Registered Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
24(28)
0 4 8 12 16 20 24 28 32 36 PTD 2640
23(27)
0000
OLMC
XOR-2560 AC1-2632 AC2-2706
22(26)
0280
2(3)
0320
OLMC
XOR-2561 AC1-2633 AC2-2707
21(25)
0600
3(4)
0640
OLMC
XOR-2562 AC1-2634 AC2-2708
20(24)
0920
4(5)
0960
OLMC
XOR-2563 AC1-2635 AC2-2709
19(23)
1240
5(6)
1280
OLMC
XOR-2564 AC1-2636 AC2-2710
17(20)
1560
7(9)
1600
OLMC
XOR-2565 AC1-2637 AC2-2711
16(19)
1880
8(10)
1920
OLMC
XOR-2566 AC1-2638 AC2-2712
15(18)
2200
9(11)
2240
OLMC
XOR-2567 AC1-2639 AC2-2713
14(17)
2520
10(12) 11(13)
13(16)
OE
2703
12(14)
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
5
Specifications GAL20VP8
Complex Mode
In the Complex mode, macrocells are configured as output only or I/O functions. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 14(17) & 22(26)) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1(2) and 12(14) are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - AC2=1 defines totem pole output. - AC2=0 defines open-drain output. - Pin 15(18) through Pin 21(25) are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - AC2=1 defines totem pole output. - AC2=0 defines open-drain output. - Pin 14(17) and Pin 22(26) are configured to this function.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6
Specifications GAL20VP8
Complex Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2) 24(28)
0 4 8 12 16 20 24 28 32 36 PTD 2640
23(27)
0000
OLMC
XOR-2560 AC1-2632 AC2-2706 22(26)
0280
2(3)
0320
OLMC
XOR-2561 AC1-2633 AC2-2707 21(25)
0600
3(4)
0640
OLMC
XOR-2562 AC1-2634 AC2-2708 20(24)
0920
4(5)
0960
OLMC
XOR-2563 AC1-2635 AC2-2709 19(23)
1240
5(6)
1280
OLMC
XOR-2564 AC1-2636 AC2-2710 17(20)
1560
7(9)
1600
OLMC
XOR-2565 AC1-2637 AC2-2711 16(19)
1880
8(10)
1920
OLMC
XOR-2566 AC1-2638 AC2-2712 15(18)
2200
9(11)
2240
OLMC
XOR-2567 AC1-2639 AC2-2713 14(17)
2520
10(12) 11(13)
13(16) 12(14)
2703
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
7
Specifications GAL20VP8
Simple Mode
In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. Pins 1(2) and 12(14) are always available as data inputs into the AND array. The center two macrocells (pins 17(20) & 19(23)) cannot be used in the input configuration. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram.
Vcc
Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - AC2=1 defines totem pole output. - AC2=0 defines open-drain output. - All OLMC except pins 17(20) & 19(23) can be configured to this function. Combinatorial Output Configuration for Simple Mode
XOR
Vcc
XOR
- SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - AC2=1 defines totem pole output. - AC2=0 defines open-drain output. - Pins 17(20) & 19(23) are permanently configured to this function.
Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - AC2=1 defines totem pole output. - AC2=0 defines open-drain output. - All OLMC except pins 17(20) & 19(23) can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
8
Specifications GAL20VP8
Simple Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2) 24(28)
0 4 8 12 16 20 24 28 32 36 PTD 2640
23(27)
0000
OLMC
XOR-2560 AC1-2632 AC2-2706
22(26)
0280
2(3)
0320
OLMC
XOR-2561 AC1-2633 AC2-2707
21(25)
0600
3(4)
0640
OLMC
XOR-2562 AC1-2634 AC2-2708
20(24)
0920
4(5)
0960
OLMC
XOR-2563 AC1-2635 AC2-2709
19(23)
1240
5(6)
1280
OLMC
XOR-2564 AC1-2636 AC2-2710
17(20)
1560
7(9)
1600
OLMC
XOR-2565 AC1-2637 AC2-2711
16(19)
1880
8(10)
1920
OLMC
XOR-2566 AC1-2638 AC2-2712
15(18)
2200
9(11)
2240
OLMC
XOR-2567 AC1-2639 AC2-2713
14(17)
2520
10(12) 11(13)
13(16) 12(14)
2703
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
9
Specifications GAL20VP8
Absolute Maximum Ratings(1)
Supply voltage VCC ........................................ -.5 to +7V Input voltage applied .......................... -2.5 to VCC +1.0V Off-state output voltage applied ......... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Ambient Temperature with Power Applied ........................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input Clamp Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C Vcc = Min. IIN = -32mA CONDITION MIN.
Vss - 0.5
TYP.4 -- --
MAX. 0.8 Vcc+1
UNITS V V V A A V V mA mA mA
VIL VIH VI1 IIL2 IIH VOL VOH IOL IOH IOS3
2.0 -- -- -- -- 2.4 -- -- -60
-1.2
-- -- -- -- -- -- --
0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH
-100
10 0.5 -- 64 -32 -400
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L -15/-25
--
90
115
mA
1) Characterized but not 100% tested. 2) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 4) Typical values are at Vcc = 5V and TA = 25 C
10
Specifications GAL20VP8
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAMETER COM
TEST COND1. A A -- -- -- A
DESCRIPTION Input or I/O to Combinational Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled 3 2 -- 8 0 55.5
-15 MIN. MAX. 15 10 4.5 -- -- --
-25 MIN. MAX. 3 2 -- 10 0 40 25 15 10 -- -- -- UNITS ns ns ns ns ns MHz
tpd tco tcf2 tsu th
fmax3
A A
80 80
-- --
50 50
-- --
MHz MHz
twh twl ten tdis
-- -- B B C C
6 6 -- -- -- --
-- -- 15 12 15 12
10 10 -- -- -- --
-- -- 20 15 20 15
ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 10 15 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
11
Specifications GAL20VP8
Switching Waveforms
INPUT or I/O FEEDBACK
VALID INPUT
tsu
INPUT or I/O FEEDBACK
th
CLK
VALID INPUT
tco
REGISTERED OUTPUT 1/fmax (external fdbk)
tpd
COMBINATIONAL OUTPUT
Combinatorial Output
Registered Output
INPUT or I/O FEEDBACK
OE
tdis
COMBINATIONAL OUTPUT
ten
REGISTERED OUTPUT
tdis
ten
Input or I/O to Output Enable/Disable
OE to Output Enable/Disable
twh
CLK 1/fmax (w/o fb)
twl
CLK 1/fmax (internal fdbk)
tcf
REGISTERED FEEDBACK
tsu
Clock Width
fmax with Feedback
12
Specifications GAL20VP8
fmax Descriptions
CLK
LOGIC ARRAY
REGISTER
CLK
tsu
tco
LOGIC ARRAY
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
tcf tpd
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC ARRAY REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT +5V
R1
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 500 500 500 R2 500 500 500 500 500 CL 50pF 50pF 50pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
13
Specifications GAL20VP8
Electronic Signature
An electronic signature word is provided in every GAL20VP8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL20VP8 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors can perform output register preload automatically.
Signature Cell
The security cell is provided on all GAL20VP8 devices to prevent unauthorized copying of the array patterns. Once programmed, the circuitry enabling array is disabled, preventing further programming or verification of the array. The cell can only be erased by reprogramming the device, so the original configuration can never be examined once this cell is programmed. Signature data is always available to the user.
Input Buffers
The GAL20VP8 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. GAL20VP8 input buffers have active pull-ups within their input structure. As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins for both devices be connected to another active input, VCC, or GND. Doing this will tend to improve noise immunity and reduce ICC for the device.
Latch-Up Protection
GAL20VP8 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups to eliminate any possibility of SCR induced latching.
Typical Input Pull-up Characteristic
0
During a programming cycle, a clear function performs a bulk erase of the array and the architecture word. In addition, the electronic signature word and the security cell are erased. This mode resets a previously configured device back to its original state, which is all JEDEC ones.
Input Current (A)
Bulk Erase Mode
-20
-40 -60
Schmitt Trigger Inputs
One of the enhancements of the GAL20VP8 for bus interface logic implementation is input gysteresis. The threshold of the positive going edge is 1.5V, while the threshold of the negative going edge is 1.3V. This provides a typical hysteresis of 200mV between positive and negative transitions of the inputs.
0
1.0
2.0
3.0
4.0
5.0
Input Voltage (Volts)
Programmable Open-Drain Outputs
In addition to the standard GAL20V8 type configuration, the outputs of the GAL20VP8 are individually programmable either as a standard totempole output or an open-drain output. The totempole output drives the specified VOH and VOL levels whereas the opendrain output drives only the specified VOL. The VOH level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by the AC2 fuse. When AC2 cell is erased (JEDEC "1") the output is configured as a totempole output and when AC2 cell is programmed (JEDEC "0") the output is configured as an open-drain. The default configuration when the device is in bulk erased state is totempole configuration. The AC2 fuses associated with each of the outputs is included in all of the logic diagrams.
Bulk Erase Mode
All eight outputs of the GAL20VP8 are capable of driving 64 mA loads when driving low and 32 mA loads when driving high. Near symmetrical high and low output drive capability provides small skews between high-to-low and low-to-high output transitions.
Output Register Preload
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system
14
Specifications GAL20VP8
Power-Up Reset
Vcc
Vcc (min.)
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
FEEDBACK/EXTERNAL OUTPUT REGISTER
Device Pin Reset to Logic "1"
Circuitry within the GAL20VP8 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown above. Because of the asynchro-
nous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL20VP8. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
Active Pull-up Circuit Active Pull-up Circuit
Vcc
ESD Protection Circuit
Vref
Vcc
Tri-State Control
Vcc
Vref
PIN
Data Output ESD Protection Circuit Feedback (To Input Buffer)
PIN
Vref = 3.1V Typical Input
Vref = 3.1V Typical Output
15
Specifications GAL20VP8
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
PT H->L PT L->H
1
RISE 1.1 FALL
PT H->L
1.1
PT L->H
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tco
Normalized Tpd
1.2 1.1 1 0.9 0.8 0.7 -55 -25
Normalized Tsu
PT H->L PT L->H
1.2 1.1 1 0.9 0.8 0.7
RISE FALL
1.3 1.2 1.1 1 0.9 0.8 0.7
PT H->L PT L->H
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
Delta Tco (ns)
-0.1 -0.2 -0.3 -0.4 -0.5 1 2 3 4 5 6 7 8
-0.25 -0.5 -0.75 -1 -1.25 1 2 3 4 5 6 7 8
RISE FALL
RISE FALL
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
6 6
Delta Tco vs Output Loading
RISE
RISE
Delta Tpd (ns)
4
Delta Tco (ns)
FALL
4
FALL
2
2
0
0
-2 0 50 100 150 200 250 300
-2 0 50 100 150 200 250 300
Output Loading (pF)
Output Loading (pF)
16
Specifications GAL20VP8
Typical AC and DC Characteristic Diagrams
Vol vs Iol
0.5 0.4 5 4
Voh vs Ioh
4.5
Voh vs Ioh
4.25
Voh (V)
0.3 0.2 0.1 0 0.00 20.00 40.00 60.00 80.00
3 2 1 0 0.00 10.00 20.00 30.00 40.00 50.00 60.00
Voh (V)
Vol (V)
4
3.75
3.5 0.00 1.00 2.00 3.00 4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.20 1.2
Normalized Icc vs Temp
1.40
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.10
1 0.9 0.8 0.7
Normalized Icc
-55 -25 0 25 75 100 125
1.1
1.30 1.20 1.10 1.00 0.90 0 25 50 75 100
1.00
0.90
0.80 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
3 0 10 20
Input Clamp (Vik)
Delta Icc (mA)
2.5
Iik (mA)
2 1.5 1 0.5 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
30 40 50 60 70 80 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
17

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