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19-2055; Rev 0; 5/01
MAX105 Evaluation Kit
General Description
The MAX105 evaluation kit (EV kit) is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX105, dual channel, 6-bit (800Msps), or the MAX107, dual channel, 6-bit (400Msps) high-speed analog-to-digital converter (ADC). The MAX105 ADC is able to process differential or single-ended analog inputs. The EV kit allows the user to evaluate the ADC with either type of signals. The digital output produced by the ADC can be easily sampled with a user-provided high-speed logic analyzer or data-acquisition system. The EV kit comes with the MAX105 installed. To evaluate the MAX107, replace the MAX105 with the MAX107. o Two Matched 6-Bit, 800 Msps ADCs o 0.8Vp-p Input Signal Range o Demultiplexed Differential LVDS Outputs o Square-Pin Headers for Easy Connection of Logic Analyzer to Digital Outputs o Four-layer PC Board with Separate Analog and Digital Power and Ground Connections o Fully Assembled and Tested with MAX105 Installed
Features
Evaluates: MAX105/MAX107
Component List
DESIGNATION C1, C5, C9, C13, C16, C18, C20, C22 C2, C6, C10, C14, C15, C17, C19, C21, C24-C28, C30 C3, C4, C7, C8, C11, C12 C23, C29 QTY 8 DESCRIPTION 47pF 10%, +50V COG ceramic capacitors (0402) Murata GRM36COG470K050AD 0.01F 10%, +16V X7R ceramic capacitors (0402) Murata GRM36X7R103K016AD 100pF 5%, +50V COG ceramic capacitors (0402) Murata GRM36COG101J050AD 10F 10%, +25V tantalum capacitors (CASE D) AVX TAJD106K025R Ferrite beads 600 at 100MHz, 500mA , 0.3 DCR Murata BLM21A601R 51.1 1% resistors (0402) 100 1% resistors (0402) SMA connectors (edge-mounted) Not installed 2-pin headers 2-pin headers Not installed 3-pin header Test point hooks MAX105ECS (80-pin TQFP-EP) MAX105 PC board MAX105 data sheet MAX105 EV kit data sheet PART MAX105ECS MAX107ECS PART MAX105EVKIT
Ordering Information
TEMP. RANGE 0C to 70C IC PACKAGE 80 TQFP-EP*
*Exposed pad
14
ADC Selection Table
SPEED (Msps) 800 400
6
2
L1-L4 R1-R6 R7-R32 J1-J6 JU1, JU2 JU4-JU55 JU3 AVCC, AGND, OVCC, OGND U1 None None None
4 6 26 6 0 52 0 4 1 1 1 1
Component Suppliers
SUPPLIER AVX Murata PHONE 803-946-0690 814-237-1431 FAX 803-626-3123 814-238-0490
Note: Please indicate that you are using the MAX105 when contacting these component suppliers.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX105 Evaluation Kit Evaluates: MAX105/MAX107
Quick Start
Test Equipment Required
* DC power supplies: Digital +3.3V, 510mA Analog +5.0V, 350mA Generator with low phase-noise for clock input (e.g., HP8662A, HP8663A, or equivalent) Two signal generators for analog signal inputs (e.g., HP8662A, HP8663A, or equivalent) Logic analyzer or data-acquisition system (e.g., HP16500C series, HP16517A 1.25Gbps state module for single-ended evaluation. User-selected analog bandpass filters (e.g., TTE Elliptical Bandpass Filter, or equivalent) Digital Voltmeter Baluns (e.g., MA/COM H-9-SMA) 50 terminators with SMA connectors remove the 100 termination resistors R7-R32 to increase the logic signal swing. Reflections are absorbed by the back-terminated LVDS drivers. Note: Two state modules are required to monitor both I and Q channel simultaneously. 5) Connect the logic analyzer clock to the DREADY+ output on the EV kit and set the logic analyzer to trigger on the falling edge of the DREADY+ signal. 6) Connect a +5V power supply to the pad marked AV CC . Connect the supply's ground to the pad marked AGND. Note: MAX105 has separate AV CCI and AV CCQ supply pins. 7) Connect a +3.3V power supply to the pad marked OV CC . Connect the supply's ground to the pad marked OGND. Tie AGND and OGND together at the power supplies. Note: MAX105 has separate OVCCI and OVCCQ supply pins. 8) Turn on both power supplies, then the signal sources. Capture the digitized outputs from the MAX105 with the logic analyzer and transfer the digital record to a PC for data analysis.
* * *
* * * *
The MAX105 EV kit is a fully assembled and tested surface-mount board. Follow the steps below for board operation. Do not turn on power supplies or enable function generators until all connections are completed. 1) Connect a signal generator with low phase-jitter to the clock inputs CLK- and CLK+ through a balun (Figure 1). For a single-ended clock input (Figure 2), connect a 500mV (354mVRMS, +4dBm) amplitude from the signal generator to the CLK+ input and terminate the unused CLK- input with a 50 termination resistor to AGND. 2) For differential operation, connect a 380mV 270mVRMS (approximately -0.5dB FS) sine-wave test signal to connector A of the balun. Terminate connector B of the balun with a 50 terminator. Attach connector C of the balun to the analog input VINI+ (VINQ+). Attach connector D of the balun to the analog input VINI- (Figure 1). For single-ended operation, apply the test signal to either VINI+ (VINQ+) or VINI- (VINQ-) and terminate the unused input with a 50 resistor to AGND (Figure 2). For best results, use a narrow bandpass filter designed for the frequency of interest to reduce the harmonic distortion of the signal generator. 3) Phase-lock both the VINI and/or VINQ signal generators with the clock generator. 4) Connect a logic analyzer, such as the HP16500 with the HP16517 plug-in module to monitor the I or Q channel of the MAX105. Note that the podlets are single-ended to ground and you may need to
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Detailed Description
The MAX105 EV kit evaluates the performance of the MAX105 dual channel, 6-bit ADC at a maximum clock frequency of 800MHz (400MHz for MAX107). The MAX105 ADC can process differential or single-ended analog and clock inputs. The user may apply baluns to generate differential signals from a single-ended analog signal to the EV kit. The EV kit's PC board incorporates a four-layer board design to optimize the performance of the MAX105 in a 50 environment. Separate analog and digital ground planes minimize noise coupling between analog and digital signals. The EV kit requires a +5.0V power supply applied to the analog power plane, and a +3.3V power supply applied to the digital power plane. Access to the outputs is provided through the two-pin headers (Table 1) all around the edge of the board. A silkscreen on the PC board's top layer indicates reference designations.
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MAX105 Evaluation Kit Evaluates: MAX105/MAX107
Table 1. LVDS Outputs and Functional Description
LVDS OUTPUT SIGNALS P5I+, P5I- (MSB) P4I+, P4IP3I+, P3IP2I+, P2IP1I+, P1IP0I+, P0I- (LSB) A5I+, A5I- (MSB) A4I+, A4IA3I+, A3IA2I+, A2IA1I+, A1IA0I+, A0I- (LSB) P5Q+, P5Q- (MSB) P4Q+, P4QP3Q+, P3QP2Q+, P2QP1Q+, P1QP0Q+, P0Q- (LSB) A5Q+, A5Q- (MSB) A4Q+, A4QA3Q+, A3QA2Q+, A2QA1Q+, A1QA0Q+, A0Q- (LSB) DOR+, DORDREADY+, DREADYEV KIT HEADER LOCATION JU52, JU53 JU48, JU49 JU44, JU45 JU12, JU13 JU40, JU41 JU36, JU37 JU54, JU55 JU50, JU51 JU46, JU47 JU18, JU19 JU42, JU43 JU38, JU39 JU6, JU7 JU10, JU11 JU16, JU17 JU22, JU23 JU27, JU26 JU31, JU30 JU4, JU5 JU8, JU9 JU14, JU15 JU20, JU21 JU25, JU24 JU29, JU28 JU33, JU32 JU34, JU35 FUNCTIONAL DESCRIPTION
Primary in-phase differential outputs from MSB to LSB. "+" indicates the true value, "-" denotes the complementary outputs
Auxiliary in-phase differential outputs from MSB to LSB. "+" indicates the true value, "-" denotes the complementary outputs
Primary quadrature differential outputs from MSB to LSB. "+" indicates the true value, "-" denotes the complementary outputs
Auxiliary quadrature differential outputs from MSB to LSB. "+" indicates the true value, "-" denotes the complementary outputs
Out-of-range signal's true and complementary outputs Data Ready LVDS output latch clock. Output data changes on the rising edge of DREADY+
Power Supplies
The MAX105 EV kit requires separate analog and digital power supplies for best performance. A +3.3V 10% power supply is used to power the digital portion (OVCC) of the ADC. A separate +5.0V 5% power supply is used to power the analog portion (AVCC) of the ADC. Ferrite beads are used to filter out high-frequency noise at the analog power supply. At 100MHz, the ferrite beads have an impedance of 600.
(400MHz for MAX107).
I/Q Input Signals
The input signals are AC-coupled. The DC biasing level is internally set to the reference voltage V REF . The MAX105's analog input resistance is 2k per input. However, the EV kit's I/Q input resistance is set to 50 by an external resistor. For single-ended operation, apply a signal to one of the analog inputs and terminate the opposite complimentary input with a 50 resistor to ground. Note: When a differential signal is applied to the ADC, the positive and negative input pins of the ADC each receive half of the input signal supplied to the balun. A common mode voltage of +2.5V is established within the part and blocked by the AC-coupling capacitors.
Clock
The clock signals CLK are AC-coupled from the SMA connectors J3 and J4. The DC-biasing level is internally set to the reference voltage. The MAX105's clock input resistance is 5k. However, the EV kit's clock input resistance is set by an external resistor to 50. An ACcoupled, differential sine-wave signal may be applied to the CLK SMA connectors (Figure 3). The signal must not exceed a magnitude of 1.4VRMS. The typical clock frequency should be 800MHz for MAX105
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3
MAX105 Evaluation Kit Evaluates: MAX105/MAX107
Reference
An on-chip reference is provided with a nominal +2.5V output. This voltage is then processed to drive the resistor ladder in the ADC core. A buffered reference voltage is also used as the DC-bias voltage for the analog input.
Table 2. MAX105 EV kit Layers
LAYER DESCRIPTION Components, Headers, Connectors, Test Pads, AVCC, OVCC, AGND, OGND, Analog 50 microstrip lines. 100 Termination Resistors AGND, AGNDI, AGNDQ, AGNDR, OGND, OGNDI, OGNDQ AVCC, AVCCI, AVCCQ, AVCCR, OVCC, OVCCI, OVCCQ AGND, Components
Layer I, Top Layer
Demultiplexing and LVDS Outputs
Each ADC provides six differential outputs (two's complement code) at 800MHz, which fan out to 12 differential outputs at 400MHz after the on-chip demultiplexer. To interface with lower supply CMOS DSP chips, all outputs provide LVDS-compatible voltage levels. The LVDS outputs will have approximately 270mV swing differential with a common mode around 1.25V. The differential output impedance is roughly 100. For details, refer to IEEE standard 1596.3. *Note: To boost the output signal swing for singleended data capture with the HP16500C and HP16517A high-speed state module, all 100 termination resistors (R7-R32) should be removed.
Layer II, Ground Plane Layer III, Power Plane Layer IV, Bottom Layer
Out-of-Range (DOR) Signal
The out-of-range signal (DOR+, DOR-) flags high when either the I or Q input is below -FS or above +FS. The out-of-range signal has the same latency as the ADC output data or is demultiplexed the same way. For an 800MHz system DOR+ and DOR- are clocked at 400MHz.
Data Ready (DREADY) Output
In single-ended data capture mode the clock interface of the logic analyzer should be connected to the DREADY output at headers JU34 or JU35 on the EV kit. Since both the primary and auxiliary outputs change on the rising edge of DREADY, set the logic analyzer to trigger on the falling edge. DREADY and the data outputs are internally time aligned, which places the falling edge of DREADY in the approximate center of the valid data window, resulting in the maximum setup and hold time for the logic analyzer.
Special Layout Considerations Special effort was made in the board layout to separate the analog and digital portions of the circuit. 50 microstrip transmission lines are used for analog and clock inputs, as well as for all digital LVDS outputs. The power plane is separated into strips to provide isolation between different sections of the circuit (e.g., AVCCI and AVCCQ or OVCCI and OVCCQ). All differential outputs are properly terminated with 100 termination resistors between true and complementary digital outputs. The PC board comes in a circular shape to ensure the best possible trace length matching for the 50 microstrip lines. The electrical lengths of the 50 microstrip lines are matched to within a few picoseconds to minimize layout-dependent delays. The propagation delay on the MAX105 EV kit board is about 130ps/inch. The line width for a differential microstrip is 2.5mils with a ground plane height of 14mils which is a standard GETek core thickness. Table 2 shows PC board layers of the EV kit.
Board Layout
The MAX105 EV kit is a four-layer PC board design (Figure 4), optimized for high-speed signals. The board is constructed from low-loss GETek core material which has a relative dielectric constant of 3.9 (R = 3.9). The GETek material used in the MAX105 EV kit board offers improved high frequency and thermal properties over standard FR4 board material. All high-speed signals are routed with differential microstrip transmission lines.
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MAX105 Evaluation Kit Evaluates: MAX105/MAX107
HP8662A/3A SINE-WAVE SOURCE
BALUN BPF A B
C D EXTERNAL 50 TERMINATION TO AGND
HP8662A/3A SINE-WAVE SOURCE
BALUN BPF A B
C D
PHASELOCKED HP8662A/3A SINE-WAVE SOURCE 800MHz +4dBm BPF
EXTERNAL 50 TERMINATION TO AGND BALUN A B C D
VINI-
VINI+
VINQ- VINQ+ AVCC AGND +5V ANALOG AGND +3.3V DIGITAL DGND
CLK+ MAX105EVKIT CLKOUTPUTS
OVCC DGND
DREADY POWER SUPPLIES
EXTERNAL 50 TERMINATION TO AGND HP16500C LOGIC ANALYZER WITH HP16517A 1.25Gbps STATE MODULE
PC
GBIP
24 DATA DREADY+ OR DREADY-
Figure 1. Typical Evaluation Setup with Differential Analog Inputs, Differential Clock Drive, and Single-Ended Data Capture
HP8662A/3A SINE-WAVE SOURCE
BPF EXTERNAL 50 TERMINATION TO AGND
HP8662A/3A SINE-WAVE SOURCE
BPF
EXTERNAL 50 TERMINATION TO AGND VINIVINI+ VINQ- VINQ+ AVCC CLK+ MAX105EVKIT CLKOUTPUTS AGND OVCC DGND DREADY POWER SUPPLIES +5V ANALOG AGND +3.3V DIGITAL DGND
PHASELOCKED HP8662A/3A SINE-WAVE SOURCE 800MHz +4dBm EXTERNAL 50 TERMINATION TO AGND
GBIP PC
HP16500C LOGIC ANALYZER WITH HP16517A 1.25Gbps STATE MODULE
24 DATA DREADY+ OR DREADY-
Figure 2. Typical Evaluation Setup with Single-Ended Analog Inputs, Single-Ended Clock Drive, and Single-Ended Data Capture
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5
MAX105 Evaluation Kit Evaluates: MAX105/MAX107
50
AGND TO ADC CLK100pF
D SMA 180 SIGNAL SOURCE 50 A 0 B
0 C
0
50 SMA AGND TO ADC CLK+ 50 AGND 100pF
EXTERNAL CONNECTION
MAX105EVKIT
Figure 3. AC-Coupled, Differential Clock Drive
25mils 50
1oz. Cu LAYER NO. 1 (TOP)
14mils GETek CORE LAYER NO. 2 GETek PREPREG AS NEEDED LAYER NO. 3 14mils GETek CORE LAYER NO. 4 (BOTTOM) 50 25mils
Figure 4. PC Board Stacking
6
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MAX105 Evaluation Kit Evaluates: MAX105/MAX107
J7 C23 10F C24 0.01F L1 IND1 AVCCR
J8
L2 IND1
C25 0.01F
AVCCI
AGND
L3 IND1
C26 0.01F
JU54 AVCCQ
JU55
JU52
JU53
JU50
JU51
JU48
JU49
L4 IND1 OVCC J9 C29 10F C30 0.01F
C27 0.01F
R32 100 AVCC 80 79 A5I78 P5I+
R31 100
R30 100
R29 100
77 P5I-
76 A4I+
75 A4I-
74 P4I+
73 P4I-
C28 0.01F
A5I+ JU1 1 TEMPS
JU2 AVCCR
2
REF
J10
3 C2 0.01F J1 AGND R1 51.1 C1 47pF
AVCCR
4
AGNDR
5 C4 100pF C3 100pF
AGNDI
AGND
6
VINI-
AGND J2 R2 51.1
7
VINI+
8 AVCCI C6 0.01F C5 47pF
AGNDI
AGND AGND AGND J3 R3 51.1
AGND C8 100pF C7 100pF AGND J4 R4 51.1 AGND R5 51.1 C12 100pF C11 100pF R6 51.1 AGND AVCCQ
9
AVCCI
10
CLK+
11
CLK-
12 C10 0.01F C9 47pF
AVCCQ
AGND J5
13
AGNDQ
AGND
14
VINQ+
AGND J6
15
VINQ-
16
AGNDQ
AGND AGND AVCC OVCC AGND C14 0.01F C13 47pF
17
SUB
18
AGND
19
AVCC
JU3
20
TESTB A5Q+ 21 A5Q22 P5Q+ 23 P5Q24 A4Q+ 25 A4Q26 P4Q+ 27 P4Q28
R7 100 JU4 JU5
R8 100 JU6 JU7
R9 100 JU8 JU9
R10 100 JU10 JU11
Figure 5a. MAX105 EV Kit Schematic _______________________________________________________________________________________ 7
MAX105 Evaluation Kit Evaluates: MAX105/MAX107
OVCC C22 47pF JU46 C21 0.01F JU47 JU44 JU45 C20 OVCC 47pF JU18
JU19
JU12
JU13
R28 100
R27 100
C19 0.01F
R14 100
R11 100
72
71
70
69
68
67
66
65
64
63
62
61
OVCCI
OGNDI
A3I+
A3I-
P3I+
P3I-
OGNDI OVCCI A2I+
A2I-
P2I+
P2IA1I+
60
JU42
59
A1I-
R26 100 JU43
P1I+
58
JU40
57
P1I-
R25 100 JU41
A0I+
56
JU38
55
A0I-
R24 100 JU39 X1 MTHOLE 1 X2 MTHOLE 1 X3 MTHOLE 1 X4 MTHOLE 1 X5 LOGO 1
P0I+
54
JU36
53
P0IU1 DREADY+
R23 100 JU37
52
MAX105
DREADY51
JU34 R22 100 JU35
50
D0R-
JU32 D0R+
49
R21 100
JU33
P0Q-
48
JU30
47
P0Q+
R20 100
JU31
A0Q-
46
JU28 A0Q+
45
R19 100 JU29
P1Q-
44
JU26 P1Q+
43
R18 100 JU27
A1Q-
42
JU24 A1Q+ OVCCQ OGNDQ
29 30 41
R17 100 JU25
A3Q+
31
A3Q32
P3Q+
33
34
P3Q- OVCCQ OGNDQ A2Q+ 35 36 37
A2Q38
P2Q+ 39
P2Q40
C16 OVCC 47pF
R12 100 JU14 JU15
R13 100 JU16 JU17
C18 OVCC 47pF
R15 100 JU20 JU21
R16 100 JU22 JU23
C15 0.01F
C17 0.01F
Figure 5b. MAX105 EV Kit Schematic (continued) 8 _______________________________________________________________________________________
MAX105 Evaluation Kit Evaluates: MAX105/MAX107
Figure 6. MAX105 EV Kit Component Placement Guide-- Component Side
Figure 7. MAX105 EV Kit PC Board Layout--Component Side
Figure 8. MAX105 EV Kit PC Board Layout--Inner Layer, Ground Plane
Figure 9. MAX105 EV Kit PC Board Layout--Inner Layer, Power Plane
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9
MAX105 Evaluation Kit Evaluates: MAX105/MAX107
Figure 10. MAX105 EV Kit PC Board Layout--Solder Side
Figure 11. MAX105 EV Kit Component Placement Guide-- Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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