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| Integrated Circuit Systems, Inc. ICS9148-49 Pentium/ProTM System Clock Chip General Description The ICS9148-49 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-03, -04 and -12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB 48MHz requirements. CPU frequencies up to 100MHz are supported. Features 3CPUs @2.5V, up to 100MHz. 7PCIs @3.3V(including 1 free running, 1 Early). 1-48MHz(@3.3V) fixed. 1 REF(3.3V, 14.318MHz), 1 IOAPIC(2.5V, 14.318MHz) Strong REF clock (1V/ns @ 50pf load) Excellent power management features including Power down, PCI and CPU stops Spread Spectrum for EMI control(0.5% down spread) Early PCI (3.0ns 250ps) Block Diagram Pin Configuration 28-pin SSOP (209mil body) Power Groups VDD1=REF0, X1, X2 VDD2=PCICLK_E , PCICLK_F , PCICLK(0:4) VDD3=48MHz VDDLC=CPUCLK(0:2) VDDLA=IOAPIC Frequency Table: SEL 100/66.6# Ground Groups PCI M Hz 33.3 33.3 1 0 CPU M Hz 100 66.6 GND1=REF0, X1, PLL CORE, X2, IOAPIC GND2=PCICLK_E, PCICLK_F, PCICLK(04) GND=CPUCLK GND3 = 48MHz Pentium is a trademark on Intel Corporation. 9148-49 Rev D 1/12/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-49 Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7,8,10,11 9 12 13 14 15 16 17 18 19 20 21 22,23,24 26 25 27 28 PIN NAME GND1 X1 X2 GND2 PCICLK_E PCICLK_F PCICLK (0:3) VDD2 PCICLK_4 SEL100/66.6# VDD3 48MHz GND3 SPREAD# PD# CPU_STOP# PCI_STOP# GND VDDLC CPUCLK (2:0) IOAPIC VDDLA VDD1 REF0 TYPE PWR IN OUT PWR OUT OUT OUT PWR OUT IN PWR OUT PWR IN IN IN IN PWR PWR OUT OUT PWR PWR OUT DESCRIPTION Ground for REF outputs, X1, X2. XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Early PCICLK. Leads PCICLK (0:4,_F) by 2ns 250ps. Not affected by PCI_STOP# Free Running PCI output. oNot affected by PCI_STOP# PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V PCI clock output. TTL compatible 3.3V Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Power for 48MHz Fixed CLK output @ 48MHz Ground for 48MHz Turns on Spread Spctrum when active. 0.5% down spread.1 Powers down chip. Internal PLLs, all output are turned off. Halt CPUCLK (2:0) at logic "0" level when input is low. Halts PCICLK (0:4) at logic "0" level when input low. Does not affect PCICLK_E 7 PCICLK_F Ground for PLL core Power for CPU outputs, nominally 2.5V CPU and Host clock outputs nominally 2.5V IOAPIC clock output 14.318MHz. Power for IOAPIC Power for REF outputs. 14.318MHz clock output/Latched input at power up. 2 ICS9148-49 CPU_STOP# Timing Diagram CPUS_TOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-49. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-49. 3. All other clocks continue to run undisturbed including SDRAMR. 4. PD# and PCI_STOP# are shown in a high (true) state. PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9148-49. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-49 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state. 3 ICS9148-49 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internal by the ICS9148-49 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated. 4 ICS9148-49 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL VIN = VDD Input High Current IIH VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0 V; Inputs with pull-up resistors Input Low Current IIL2 Operating CL = 0 pF; 66.6 MHz IDD3.3OP Supply Current CL = 0 pF; 100 MHz VDD = 3.3 V; Input frequency Fi Logic Inputs CIN 1 Input Capacitance X1 & X2 pins CINX 1 Transition Time Ttrans To 1st crossing of target Freq. 1 Settling Time Ts From 1st crossing to 1% target Freq. 1 Clk Stabilization TSTAB From VDD = 3.3 V to 1% target Freq. 1 MIN 2 VSS-0.3 -5 -200 12 27 MAX UNITS VDD+0.3 V 0.8 V A 0.1 5 A 2.0 A -100 70 100 mA 75 100 14.318 16 MHz 5 pF 36 45 pF 3 ms 2 ms 3 ms TYP Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN CL = 0 pF; 66.8 MHz Operating Supply IDD2.5OP Current CL = 0 pF;133 MHz IDD2.5OPD Power Down Current 1.5 TCPU-PCI(F,0:4) VT = 1.5 V / 1.25V; CPU leads Skew1 TCPU-PCI(E) VT = 1.5 V / 1.25V; PCI leads 180 1 TYP 17 27 5 3 200 MAX 50 50 100 4 250 UNITS mA A ns ps Guaranteed by design, not 100% tested in production. 5 ICS9148-49 Electrical Characteristics - CPU TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Output High Voltage VOH2B IOH = -12 mA 2 2.2 0.3 Output Low Voltage VOL2B IOL = 12 mA -20 Output High Current IOH2B VOH = 1.7 V 19 26 Output Low Current IOL2B VOL = 0.7 V 1 tr2B Rise Time VOL = 0.4 V, VOH = 2.0 V 1.2 1 tf2B VOH = 2.0 V, VOL = 0.4 V 1.2 Fall Time 1 dt2B Duty Cycle VT = 1.25 V 45 50 1 tsk2B Skew VT = 1.25 V 60 Jitter, Single Edge 1 VT = 1.25 V 200 tjsed2B 2 Displacement 1 tj1s2B VT = 1.25 V 65 Jitter, One Sigma 1 tjabs2B VT = 1.25 V Jitter, Absolute -300 160 1 2 MAX UNITS V 0.4 V -16 mA mA 1.6 ns 1.6 ns 55 % 175 ps 250 150 300 ps ps ps Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period. Electrical Characteristics - PCI TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA IOL = 9.4 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 Duty Cycle dt1 VT = 1.5 V 1 Skew tsk1 VT = 1.5 V Jitter, Single Edge 1 VT = 1.25 V tjsed2B 2 Displacement VT = 1.5 V tabs1a 1 Jitter, Absolute VT = 1.5 V tjabs1b 1 MIN 2.6 16 45 TYP 3 0.2 -30 25 1.7 1.6 51 200 200 MAX UNITS V 0.4 V -22 mA mA 2 ns 2 ns 55 % 500 ps 500 200 250 ps ps ps -250 Guaranteed by design, not 100% tested in production. 6 ICS9148-49 Electrical Characteristics - REF0 TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 50 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -12 mA Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 9 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr5 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf5 1 VT = 1.5 V Duty Cycle dt5 1 VT = 1.5 V Jitter, One Sigma tj1s5 1 VT = 1.5 V tjabs5 Jitter, Absolute 1 MIN 2.6 16 53 -5 TYP 2.7 0.3 -32 25 1.2 1.1 54 1 - MAX UNITS V 0.4 V -22 mA mA 2 ns 2 ns 55 % 3 % 5 % Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -12 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V 1 tr2B VOL = 0.4 V, VOH = 2.0 V Rise Time 1 tf2B Fall Time VOH = 2.0 V, VOL = 0.4 V 1 dt2B Duty Cycle VT = 1.25 V Jitter, One Sigma Jitter, Absolute1 1 1 MIN 2 19 45 -6 TYP 2.2 0.3 -20 26 1.2 1.2 50 2 4.5 MAX UNITS V 0.4 V -16 mA mA 1.6 ns 1.6 ns 55 % 3 6 % % tj1s1 tjabs1b VT = 1.5 V VT = 1.5 V Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48M TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF PARAMETER SYMBOL CONDITIONS IOH = -11 mA Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr11 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 Duty Cycle1 Jitter, One Sigma Jitter, Absolute1 1 1 MIN 2.4 12 TYP 3 0.2 -22 20 2.2 1.9 50 2 4.5 MAX UNITS V 0.4 V -18 mA mA 2.5 ns 2.5 ns 55 3 6 % % % Dt1 Tj1s1 Tjabs1 VT = 1.5 V VT = 1.5 V VT = 1.5 V 45 -6 Guaranteed by design, not 100% tested in production. 7 ICS9148-49 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic 8 ICS9148-49 SYMBOL MIN. A A1 A2 b c D E e H L N 0.068 0.002 0.066 0.010 0.004 0.205 0.301 0.025 0 COMMON DIMENSIONS NOM. 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4 MAX. 0.078 0.008 0.070 0.015 0.008 0.212 0.311 0.037 8 VARIATIONS N 14 16 20 24 28 30 MIN. 0.239 0.239 0.278 0.318 0.397 0.397 D NOM. 0.244 0.244 0.284 0.323 0.402 0.402 MAX. 0.249 0.249 0.289 0.328 0.407 0.407 Dimensions in inches Ordering Information ICS9148F-49 Example: 28 Pin SSOP Package ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. |
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