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| Preliminary Technical Data FEATURES Powered from 3.15 V to 26V Precision Current Sense Amplifier Precision Voltage Input 12-Bit ADC for Current and Voltage Readback Alert output allow basic P-MOS hotswap up to 26V SETV input for setting over current alert threshold Programmable over-current filtering via TIMER pin CLRB Input Pin I2C Fast Mode compliant interface (400KHz max) 10-lead MSOP package Digital Power Monitor with Alert Output and Clear Pin ADM1192 FUNCTIONAL BLOCK DIAGRAM ADM1192 Vcc + V Mux 0 12-Bit ADC 1 SDA I2C SCL ADR A SENSE Current Sense Amplifier I + ALERT SETV Comparator ALERT APPLICATIONS Power Monitoring/Power Budgeting Central office Equipment Telecommunication and Data communication Equipment PC/Servers 3.15V - 26V GND CLRB TIMER Figure 1. APPLICATIONS DIAGRAM R SENSE P-Channel FET GENERAL DESCRIPTION Vcc SENSE The ADM1192 is an integrated current sense amplifier that offers digital current and voltage monitoring via an on-chip 10bit ADC, communicated through an I2C interface. SETV CONTROLLER ALERT ADM1192 SDA SCL TIMER GND CLRB ADR SDA SCL CLRB An internal current sense amplifier senses voltage across the sense resistor in the power path via the VCC and SENSE pins. A 12-bit ADC is configured to be able to measure the current seen in the sense resistor, and also the supply voltage on the VCC pin. An industry standard I2C interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by an I2C command. Alternatively the ADC can run continuously and the user can read the latest conversion data whenever it is required. Up to 4 unique I2C addresses can be created by the way the ADR pin is connected. A SETV pin is also included. A voltage applied to this pin is internally compared to the output voltage on the current sense amplifier. When the output of SETV comparator asserts the current sense amplifier ouput exceeds the SETV voltage. This event is detected at the Alert block. The Alert block then charges up the external TIMER capacitor with a fixed current. When this timing cycle is complete the ALERT output asserts. P=VI Figure 2. A basic P-MOS hotswap circuit can be implemented with the Alert output. The value of the TIMER capacitor should be set so that the charging time of this capacitor is much longer than the period where a higher than nominal inrush current may be flowing. The Alert output can also be used as a flag to warn a microcontroller or FPGA of an overcurrent condition. Alert outputs of multiple ADM1192 devices can be tied together and used as a combined alert. The ADM1192 is packaged in a 10-lead MSOP package. Rev. PrF May 2006 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved. ADM1192 TABLE OF CONTENTS Preliminary Technical Data REVISION HISTORY 05/06--Revision PrF: Initial Version Rev. PrF| Page 2 of 15 Preliminary Technical Data ADM1192--SPECIFICATIONS VVCC = 3.15V to 26V, TA = -40C to +85C, Typical Values at TA = +25C unless otherwise noted. Table 1. Parameter VCC Pin Operating Voltage Range, VVCC Supply Current, ICC Undervoltage Lockout, VUVLO Undervoltage Lockout Hysteresis, VUVLOHYST CLRB Pin Low Input Voltage, VCLRBLOW Pin Input Current for Logic 0 Input, ICLRBLOW High Input Voltage, VCLRBHIGH Pin Input Current for Logic 1 Input, ICLRBHIGH Maximum Leakage Current, , ICLRBLEAKMAX ALERT Pin Output low voltage, VALERTOL Maximum sink current, IALERTMAX Input Current, IALERT SENSE Pin Input Current ISENSE TIMER Pin Pull-Up Current (Overcurrent Fault), ITIMERUPPMOC Pull-Down Current, ITIMERDN Pin Threshold High, VTIMERH SETV Pin Overcurrent Trip Threshold, VSENSEOC Valid Input Range Input Current, ISETVLEAK ADR Pin Set address to 00, VADRLOWV Set address to 01, RADRLOWZ Set address to 10, IADRHIGHZ Set address to 11, VADRHIGHV Input current for 00 decode, IADRLOW Input current for 11 decode, IADRHIGH MONITORING ACCURACY1 Current Sense Absolute Accuracy Min 3.15 1.6 2.8 25 Typ Max 26 3 Units V mA V mV V A V A A V mA A A A A V mV V A A V k A V A A % % % % % % % %/C mV % % Conditions ADM1192 VVCC Rising 0.8 -40 2 -22 3 TBD 0.05 -2 -1 -1 -48 1.235 97.5 -1 0.5 0 135 -1 2 -40 TBD -2.3 TBD -2.5 TBD -2.8 -3.5 3 -22 0.8 165 +1 5.5 10 -60 100 1.3 100 1 +1 -72 1.365 102.5 1.9 1 10 VCLRB = 0V to 0.8V VCLRB = 2.0V to 5.5V 0.2 IALERT = -100A Maximum sink current allowed to flow in ALERT pin 0 output state VALERT = VCC; in Alert Condition VSENSE = VVCC (18.125 * VSENSE) > VSETV, VTIMER = 1V Normal Operation, VTIMER = 1V TIMER rising VSETV = 1.8125V; VSENSEOC = VVCC - VSENSE VSETV < 1.9V VSETV > 3.15V Low state Resistor to ground state, load pin with specified resistance for 01 decode Open state, maximum load allowed on ADR pin for 10 decode High state VADR = 2.0 V to 5.5 V VADR = 0 V to 0.8 V VSENSE = 75 mV VSENSE = 75 mV, @ 0C to +70C VSENSE = 50mV VSENSE = 50 mV, @ 0C to +70C VSENSE = 25mV VSENSE = 25mV, @ 0C to +70C VSENSE = 12.5 mV, @ 25C 150 TBD +2.2 TBD +2.5 TBD +2.8 +3.5 0.01 105 Current Sense Accuracy, TC VSENSE for ADC full-scale Voltage Sense Accuracy -1.5 -1.5 +1.5 +1.5 Rev. PrF| Page 3 of 15 VVCC = 3.15 V to 5.5V (VRANGE = 1) VVCC = 10.8 V to 26V (VRANGE = 1) ADM1192 Parameter VCC for ADC full-scale, low range VCC for ADC full-scale, high range I2C Timing3 Low level input voltage, VIL High level input voltage, VIH Low level output voltage on SDA, VOL Output fall time on SDA from VIHMIN to VILMAX Maximum width of spikes suppressed by input filtering on SDA and SCL pins Input current, II, on SDA/SCL when not driving out a logic low Input capacitance on SDA/SCL SCL clock frequency, fSCL LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition, tSU;STA SDA output data hold time, tHD;DAT Set-up time for a stop condition, tSU;STO Bus free time between a STOP and a START condition, tBUF Capacitive load for each bus line 1 Preliminary Technical Data Min Typ 6.656 26.6282 Max Units V V V V V ns ns A pF kHz ns ns ns ns ns ns pF Conditions VRANGE = 1 VRANGE = 0 0.99 2.31 20+0.1CB 50 -10 5 400 600 1300 600 100 600 1300 400 0.4 250 250 +10 IOL = 3mA CB = bus capacitance from SDA to GND Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error and ADC error. The maximum operating voltage is limited to VVCC =13.2 V which corresponds to an ADC code of 508. 3 The following conditions apply to all timing specifications: VBUS =3.3V, TA =25C. All timings refer to VIHMIN and VILMAX. 2 Rev. PrF| Page 4 of 15 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC Pin SENSE Pin TIMER Pin CLRB Pin SETV Pin ALERT Pin SDA, SCL Pins ADR Pins Power Dissipation Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 30 V 30 V -0.3 V to +6 V -0.3 V to +6 V 30V 30 V -0.3 V to +6 V -0.3 V to +6 V TBD -65C to +125C -40C to +85C 300C 150C ADM1192 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Ambient temperature = 25C, unless otherwise noted. ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrF| Page 5 of 15 ADM1192 PIN CONFIGURATIONS Vcc 1 SENSE 2 SETV 3 TIMER 5 Figure 3. Pin Configurations Preliminary Technical Data 10 ALERT CLRB ADR SCL ADM1192ARM TOP VIEW 9 8 GND 4 (NOT TO SCALE) 7 SDA 6 PIN FUNCTIONAL DESCRIPTIONS Table 3. Pin No. 1 2 Name VCC SENSE Description Positive supply input pin. The operating supply voltage range is between 3.15 V to 26 V. An undervoltage lockout (UVLO) circuit resets the ADM1192 when a low supply voltage is detected. Current sense input pin. A sense resistor between the VCC and SENSE pins generates a voltage across a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this voltage before it is digitized by the ADC. Input Pin. The voltage driven onto this pin will be compared to the output of the internal current sense amplifier. The lower the voltage on the SETV, the lower the current level that will cause a the ALERT output to assert. Chip Ground Pin Timer Input Pin. An external capacitor CTIMER sets the timing period for masking overcurrent conditions. This timing period should be sufficient to allow the load charge up completely with maximum current at startup without tripping an overcurrent fault. I2C Clock Pin. Open-drain output requires an external resistive pull-up. I2C Data I/O Pin. Open-drain output requires an external resistive pull-up. I2C Address Pin. This pin can be tied low, tied high, left floating or tied low through a resistor to set four different I2C addresses. Clear Pin. A latched overcurrent condition can be cleared by pulling this pin low. Alert Output Pin. Active high. This pin asserts when an overcurrent condition is present. 3 SETV 4 5 GND TIMER 6 7 8 9 10 SCL SDA ADR CLRB ALERT Rev. PrF| Page 6 of 15 Preliminary Technical Data VOLTAGE AND CURRENT READBACK The ADM1192 contains the components to allow voltage and current readback over an I2C bus. The voltage output of the current sense amplifier and the voltage on the VCC pin are fed into a 12-bit ADC via a multiplexer. The device can be instructed to convert voltage and/or current at any time during operation via an I2C command. When all conversions are complete the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. ADM1192 IDENTIFYING THE ADM1192 ON THE I2C BUS The ADM1192 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address. The five MSBs of the address are set to 01011, the two LSBs are determined by the state of the ADR pin. There are four different configurations available on the ADR pin which correspond to four different I2C addresses for the two LSBs. These are explained in Table 4 below. This scheme allows four ADM1192 devices to operation on a single I2C. Table 4. Setting I2C Addresses via the ADR Pin ADR Configuration Low state Resistor to GND Floating (unconnected) High state Address 0x68 0x69 0x6A 0x6B SERIAL BUS INTERFACE Control of the ADM1192 is carried out via the serial System Management Bus (I2C). This interface is compatible with fastmode I2C (400 kHz max). The ADM1192 is connected to this bus as a slave device, under the control of a master device. 2. GENERAL I2C TIMING and show timing diagrams for general read and write operations using the I2C. The I2C specification defines specific conditions for different types of read and write operation, which are discussed later. The general I2C protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 3. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the ninth clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. Rev. PrF| Page 7 of 15 ADM1192 1 SCL SDA 0 1 0 1 1 A1 A0 R/W ACK. BY SLAVE 9 1 D7 D6 D5 D4 D3 9 1 Preliminary Technical Data 9 D2 D1 D0 ACK. BY SLAVE 9 START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 FRAME 2 COMMAND CODE D0 ACK. BY SLAVE D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE STOP BY MASTER FRAME 3 DATA BYTE FRAME N DATA BYTE Figure 4. General I2C Write Timing Diagram 1 SCL 0 0 A1 A0 R/W ACK. BY SLAVE D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY MASTER 9 1 9 SDA 1 1 1 START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 FRAME 2 DATA BYTE 9 1 9 D1 D0 ACK. BY MASTER D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. STOP BY MASTER FRAME 3 DATA BYTE FRAME N DATA BYTE Figure 5. General I2C Read Timing Diagram tLOW SCL tR tF tHD;STA tHD;STA tHIGH tHD;DAT tSU;DAT tSU;STA tSU;STO SDA tBUF P S S P Figure 6. Serial Bus Timing Diagram Rev. PrF| Page 8 of 15 Preliminary Technical Data WRITE AND READ OPERATIONS The I C specification defines several protocols for different types of read and write operations. The ones used in the ADM1192 are discussed below. The following abbreviations are used in the diagrams: Table 5. I2C abbreviations S P R W A N START STOP READ WRITE ACKNOWLEDGE NO ACKNOWLEDGE 2 ADM1192 WRITE COMMAND BYTE In this operation the master device sends a command byte to the slave device, as follows: 1. 2. 3. 4. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends the command byte. The command byte is identified by an MSB =0. (An MSB =1 indicates an Extended Register Write. See next section.) The slave asserts ACK on SDA. The master asserts a STOP condition on SDA to end the transaction. 1 2 3 4 56 SLAVE COMMAND S WA AP ADDRESS BYTE QUICK COMMAND This operation allows the master check if the slave is present on the bus. This entails the following: 1. 2. 3. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. 1 S 2 3 SLAVE WA ADDRESS 5. 6. Figure 8. Command Byte Write The seven LSBs of the command byte are used to configure and control the ADM1192. Details of the function of each bit are provided in . Figure 7. Quick Command Table 6. Command Byte Operations Bit C0 C1 C2 C3 C4 Default 0 0 0 0 0 Name V_CONT V_ONCE I_CONT I_ONCE VRANGE Function Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1192 will ACK and return all zeros in the returned data. Set to convert voltage once. Self-clears. I2C will NACK an attempted read until ADC conversion is complete. Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1192 will ACK and return all zeros in the returned data. Set to convert current once. Self-clears. I2C will NACK an attempted read until ADC conversion is complete. Selects different internal attenuation resistor networks for voltage readback. A "0" in C4 selects a 14:1 voltage divider. A "1" in C4 selects a 7:2 voltage divider. With an ADC full-scale of 1.902 V, the voltage at the VCC pin for an ADC full-scale result is 26.63 V for VRANGE = 0 and 6.66 V for VRANGE = 1. Unused Status Read. When this bit is set the data byte read back from the ADM1192 will be the STATUS byte. This contains the status of the device alerts. See Table14 for full details of the status byte. C5 C6 0 0 N/A STATUS_RD Rev. PrF| Page 9 of 15 ADM1192 WRITE EXTENDED BYTE In this operation the master device writes to one of the three extended registers of the slave device, as follows: 1. 2. 3. 4. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends the register address byte. The MSB of this byte is set to 1 to indicate an extended register write. The two LSBs indicate which of the three extended registers will be written to (see Table 7). All other bits should be set to 0. The slave asserts ACK on SDA. The master sends the command byte. The command byte is identified by an MSB = 0. (An MSB = 1 indicates an Extended Register Write. See next section.) The slave asserts ACK on SDA. 8. Preliminary Technical Data The master asserts a STOP condition on SDA to end the transaction. 1 S 2 3 4 5 6 78 SLAVE REGISTER REGISTER RA A NP ADDRESS DATA ADDRESS Figure 9. Command Byte Write Table 8, Table 9, and give details of each extended register. 5. 6. Table 7. Extended Register Addresses A6 0 0 0 A5 0 0 0 A4 0 0 0 A3 0 0 0 A2 0 0 0 A1 0 1 1 A0 1 0 1 Extended Register ALERT_EN ALERT_TH CONTROL 7. Table 8. ALERT_EN Register Operations Bit 0 1 2 3 4 Default 0 0 1 0 0 Name EN_ADC_OC1 EN_ADC_OC4 EN_OC_ALERT EN_OFF_ALERT CLEAR Function Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH register Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the ALERT_TH register Enables the OC_ALERT register. If an overcurrent condition is present and the TIMER pin has charged to 1.3V the OC_ALERT register will capture and latch this condition. Enable an ALERT if the HS operation is turned off by an operation which writes the SWOFF bit high. This allows software override the Alert output (and will turn on a PMOS FET controlled by Alert). Clears the OC_ALERT and ADC_ALERT status bits in the STATUS register. These may immediately reset if the source of the alert has not been cleared, or disabled with the other bits in this register. This bit selfclears to 0 after the STATUS register bits have been cleared. Table 9. ALERT_TH Register Operations Bit 7:0 Default FF Function The ALERT_TH register sets the current level at which an alert will occur. Defaults to ADC full-scale. ALERT_TH 8-bit number corresponds to the top 8-bits of the current channel data. Table 10. CONTROL Register Operations Bit 0 Default 0 Name SWOFF Function Force ALERT pin to de-assert. Can only be active if EN_OFF_ALERT bit is high (see Table 8). Rev. PrF| Page 10 of 15 Preliminary Technical Data READ VOLTAGE AND/OR CURRENT DATA BYTES The ADM1192 can be set up to provide information in three different ways (see Write Command Byte section above). Depending on how the device is configured the following data can be read out of the device after a conversion (or conversions): 1. Voltage and Current Readback. The ADM1192 will digitize both voltage and current. Three bytes will be read out of the device in the following format: Table 111. Byte 1 2 3 Contents Voltage MSBs Current MSBs LSBs B7 V11 I11 V3 B6 V10 I10 V2 B5 V9 I9 V1 B4 V8 I8 V0 B3 V7 I7 I3 B2 V6 I6 I2 B1 V5 I5 I1 B0 V4 I4 I0 ADM1192 5. 6. 7. 8. 9. 10. The master asserts ACK on SDA. The master receives the second data byte. The master asserts ACK on SDA. The master receives the third data byte. The master asserts NO ACK on SDA. The master asserts a STOP condition on SDA and the transaction ends. For the cases where the master is reading voltage only or current only, only two data bytes will be read and events 7 and 8 above will not be required. 1 2 3 4 5 6 7 8 9 10 SLAVE S R A DATA 1 A DATA 2 A DATA 3 N P ADDRESS 2. Voltage Readback. Figure 10. Three Byte Read fromADM1191 The ADM1192 will digitize voltage only. Two bytes will be read out of the device in the following format: Table 12. Byte Contents 1 Voltage MSBs 2 Voltage LSBs B7 B6 B5 B4 B3 B2 V11 V10 V9 V8 V7 V6 V3 V2 V1 V0 0 0 B1 V5 0 B0 V4 0 1 2 3 4 5 6 78 SLAVE REGISTER REGISTER S RA A NP ADDRESS DATA ADDRESS Figure 11. Two Byte Read fromADM1191 Read Status Register A single register of status data can also be read from the ADM1192. 1. 2. 3. 4. 5. The master device asserts a START condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives the status byte. The master asserts ACK on SDA. 1 2 3 4 5 SLAVE S R A DATA 1 A ADDRESS 3. Current Readback. The ADM1192 will digitize current only. Two bytes will be read out of the device in the following format: Table 13. Byte Contents 1 Current MSBs 2 Current LSBs B7 I11 I3 B6 I10 I2 B5 B4 B3 B2 I9 I8 I7 I6 I1 I0 0 0 B1 I5 0 B0 I4 0 The following series of events occur when the master receives three bytes (voltage and current data) from the slave device: 1. 2. 3. 4. The master device asserts a START condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives the first data byte. Figure 12. Status Read fromADM1191 Table 14 shows the ADM1192 status registers in detail. Note that bits 1, 3 and 5 are cleared by writing to bit 4 of the ALERT_EN register (CLEAR). Rev. PrF| Page 11 of 15 ADM1192 Table 14. Status Byte Operations Bit 0 1 2 3 4 5 Name ADC_OC ADC_ALERT OC OC_ALERT OFF_STATUS OFF_ALERT Preliminary Technical Data Function An ADC based overcurrent comparison has been detected on the last 3 conversions An ADC based overcurrent trip has happened, which has caused the ALERT. Cleared by writing to bit 4 of the ALERT_EN register. An overcurrent condition is present (i.e. the output of the current sense amplifier is greater than the voltage on the SETV input). An overcurrent condition has caused the Alert block to latch a fault on the ALERTB output has asserted. Cleared by writing to bit 4 of the ALERT_EN register. Set to 1 by writing to the SWOFF bit of the CONTROL register. An alert has been caused either by the SWOFF bit. Cleared by writing to bit 4 of the ALERT_EN register. Rev. PrF| Page 12 of 15 Preliminary Technical Data ALERT OUTPUT The Alert output is an open-drain pin with 30V tolerance. There are two uses for this output: 1. Overcurrent flag: The Alert pin can be connected to an general purpose logic input of a controller. Under normal operation the ADM1192 will drive this output low. When an overcurrent condition occurs the output will assert high. An external pull-up resistor should be used. R SENSE ADM1192 SETV PIN The SETV pin allows the user adjust the current level that trips the ALERT output. The output of the current sense amplifier is compared with the voltage driven onto the SETV pin. If the current sense amplifier output is higher than the SETV voltage then the output of the comparator will assert. By driving a different voltage onto the SETV pin the ADM1192 will detect an overcurrent condition at a different current level. When the output of the SETV comparator asserts this tells the ALERT block to begin charging the external TIMER capacitor with a 60uA charging current. When the voltage on the TIMER capacitor reaches 1.3V the charging cycle is complete. The ALERT output will then assert (go high). Different values of TIMER capacitor will generate different time delays between current faults occurring and the ALERT output asserting. When using the ALERT output to implement a hotswap circuit the TIMER capacitor should be chosen to generate a large enough startup delay to allow the maximum inrush current completely charge up the load without tripping an ALERT fault. 3.15V - 26V Vcc SENSE CONTROLLER ALERT ALERT ADM1192 SETV SDA SCL TIMER GND CLRB ADR SDA SCL CLRB P=VI Figure 13. Using the ALERTB output as an interrupt RSENSE ILOAD 2. Implementing a basic hotswap circuit: A basic P-MOS hotswap circuit can be created. The Alert output should be connected to the GATE pin of a P-MOS FET connected in series with the power path. A pull-up from GATE to source will ensure that the PMOS GATE will be pulled up and the device held off as soon as power is applied. When the ADM1192 powers up the GATE will be pulled low by the Alert output. A capacitor on the will determine the slew rate of the GATE at turn-on. Note that if a current fault occurs at any point in operation the Alert output will assert high, turning off the P-MOS FET. R SENSE Vcc SENSE + - A Current Sense Amplifier Applied Voltage SETV + ALERT Comparator ALERT 60uA 3.15V - 26V P-Channel FET TIMER 1.3V Vcc SENSE CONTROLLER ALERT Figure 15 . SETV operation ADM1192 SETV SDA SCL TIMER GND CLRB ADR SDA SCL CLRB P=VI Figure 14. PMOS hotswap implemenation Rev. PrF| Page 13 of 15 ADM1192 KELVIN SENSE RESISTOR CONNECTION When using a low-value sense resistor for high current measurement the problem of parasitic series resistance can arise. The lead resistance can be a substantial fraction of the rated resistance making the total resistance a function of lead length. This problem can be avoided by using a Kelvin sense connection. This type of connection separates the current path through the resistor and the voltage drop across the resistor. Figure 16 below shows the correct way to connect the sense resistor between the VCC and SENSE pins of the ADM1192. Preliminary Technical Data SENSE RESISTOR CURRENT FLOW FROM SUPPLY CURRENT FLOW TO LOAD KELVIN SENSE TRACES VCC SENSE ADM1175 Figure 16. Kelvin Sense Connections Rev. PrF| Page 14 of 15 Preliminary Technical Data OUTLINE DIMENSIONS 0.122 (3.10) 0.114 (2.90) 10 6 ADM1192 0.122 (3.10) 0.114 (2.90) 1 5 0.199 (5.05) 0.187 (4.75) PIN 1 0.0197 (0.50) BSC 0.120 (3.05) 0.112 (2.85) 0.037 (0.94) 0.031 (0.78) 0.006 (0.15) 0.002 (0.05) 0.012 (0.30) 0.006 (0.15) 0.043 (1.10) MAX SEATING PLANE 0.009 (0.23) 0.005 (0.13) 6o o 0 0.028 (0.70) 0.016 (0.40) 0.120 (3.05) 0.112 (2.85) Figure 13. 10-Lead MSOP Package (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model ADM1192-1ARMZ-R71 1 Brand M5M Temperature Range -40C to +85C Package Description MSOP-10 Package Outline RM-10 Z=PB-free part (c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05754-0-5/06(PrF) Rev. PrF| Page 15 of 15 |
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