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Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
DESCRIPTION
This is family of 4194304 - word by 64 - bit dynamic RAM module. This consists of four industry standard 4Mx16 dynamic RAMs in TSOP and one industry EEPROM in TSSOP. The mounting of TSOP on a card edge dual in line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module,suitable for easy interchange of addition of modules.
APPLICATION
Main memory unit for computer,Microcomputer memory,Refresh memory for CRT.
*:Applicable to self refresh version(MH4V645/6445AXJJ-5S,-6S) only
FEATURES
RAS CAS Address OE access access access access Cycle time time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) MH4V6445BXJJ-5,5S MH4V6445BXJJ-6,6S 50 60 13 15 25 30 13 15 84 104
single 3.3V 0.3V supply Low stand-by power dissipation 7.2mW- - - - - - - - - LVCMOS input level operating power dissipation MH4V6445BXJJ-5,5S - - - - 2016 mW(max.) MH4V6445BXJJ-6,6S - - - - 1872 mW(max.) Self refresh capability* Self refresh current - - - - 1600 uA(max.) All input, output LVTTL compatible and low capacitance Utilizes industry standard 4Mx16 RAMs in TSOP and industry standard EEPROM in TSSOP. Includes decoupling capacitor(0.22uFx4) Hyper page mode , Read-modify-write, CAS before RAS refresh,Hidden refresh capabilities. Early-write mode,OE and W to control output buffer impedance.
ADDRESS
Part No. MH4V6445BXJJ Row Add. Col Add. A0~A11 A0~A9 Refresh
/RAS only Ref,Normal R/W CBR Ref,Hidden Ref
Refresh Cycle Normal S-Version 4096/64ms 4096/128ms
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 1 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
PIN CONFIGURATION
PIN Number Front side Pin Name PIN Number Back side Pin Name PIN Number Front side Pin Name PIN Number Back side Pin Name
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 Vss /CAS0 /CAS1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss Reserved Reserved RFU Vcc RFU /WE /RAS0 NC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss /CAS4 /CAS5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss Reserved Reserved FRU Vcc RFU RFU RFU RFU
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
/OE Vss Reserved Reserved Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc /CAS2 /CAS3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
RFU Vss Reserved Reserved Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 A11 Vss NC NC Vcc /CAS6 /CAS7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc
RFU:Reserved Future Use NC,RFU,Reserved: NO CONNECTION
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MITSUBISHI ELECTRIC
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Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Block Diagram Address /OE /WE /RAS0 /CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D1 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D0
/CAS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /CAS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 /CAS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 SERIAL PD D3 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D2
Vcc
C1~C4
D0 to D3 D0 to D3
SCL
A0 A1 A2
SDA
Vss
Vss
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MITSUBISHI ELECTRIC
( 3 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
a number of other functions, e.g., Hyper page mode, /RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
FUNCTION
The MH4V6445BXJJ provide, in addition to normal read, write, and read-modify-write operations,
Table 1 Input conditions for each mode
Inputs Operation Read Write (Early write) Write (Delayed write) Read-modify-write /RAS-only refresh Hidden refresh /CAS before /RAS refresh Standby Self refresh * /RAS ACT ACT ACT ACT ACT ACT ACT NAC ACT /CAS ACT ACT ACT ACT NAC ACT ACT DNC ACT /W NAC ACT ACT ACT DNC NAC NAC DNC NAC Input/Output Refresh Remark Row Column /OE address address Input Output ACT APD APD OPN VLD YES Hyper DNC APD APD VLD OPN YES page mode DNC APD APD VLD IVD YES identical ACT APD APD VLD VLD YES DNC APD DNC DNC OPN YES ACT APD DNC OPN VLD YES DNC DNC DNC DNC OPN YES DNC DNC DNC DNC OPN NO DNC DNC DNC DNC OPN YES
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open *MH4V6445BXJJ-5S,-6S only
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 4 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Conditions With respect to Vss
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Ratings -0.5~4.6 -0.5~4.6 -0.5~4.6 50 4 0~ 70 -40~ 100 Unit V V V mA W C C
Ta=25C
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs
(Ta=0~ 70C, unless otherwise noted) (Note 1)
Min 3.0 0 2.0 -0.3
Limits Nom 3.3 0
Max 3.6 0 Vcc+0.3 0.8
Unit V V V V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL IOZ II Parameter
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0VVOUT3.6V 0VVIN3.6V, Other input pins=0V /RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open /RAS=/CASVcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open /CAS before /RAS refresh cycling tRC=min. output open
High-level output voltage Low-level output voltage Off-state output current Input current Average supply -5,-5S ICC1 (AV) current from Vcc operating (Note 3,4,5) -6,-6S ICC2 Supply current from Vcc , stand-by
Min 2.4 0 -10 -40
Limits Typ Max Vcc 0.4 10 40 560 520 4 2 480 440 560
Unit V V uA uA mA
mA mA
Average supply current -5,-5S ICC4(AV) from Vcc Hyper-Page-Mode (Note 3,4,5) -6,-6S
Average supply current -5,-5S from Vcc ICC6(AV) /CAS before /RAS refresh (Note 3,5) -6,-6S mode
mA 520
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH
CAPACITANCE
Symbol CI (A) CI C(CAS) C(DQ) C(SDA) C(SCL)
(Ta = 0~70C, Vcc = 3.3V0.3V, Vss = 0V, unless otherwise noted)
Parameter Input capacitance, address inputs
Input capacitance, clock inputs except CAS
Test conditions VI=Vss f=1MHZ Vi=25mVrms
Min
Input capacitance, CAS Input/Output capacitance,DATA Input/Output capacitance,SDA Input capacitance, SCL
Limits Typ Max 40 45 25 25 12 12
Unit pF pF pF pF pF pF
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MITSUBISHI ELECTRIC
( 5 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
otherwise noted , see notes 6,14,15)
SWITCHING CHARACTERISTICS (Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless
Symbol tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ tDOH Parameter (Note 7,8) Access time from /CAS (Note 7,9) Access time from /RAS (Note 7,10) Column address access time (Note 7,11) Access time from /CAS precharge (Note 7) Access time from /OE Output hold time /CAS high (Note 13) Output hold time /RAS high Output low impedance time from /CAS low (Note 7) (Note 12) Output disable time after /OE high (Note 12) Output disable time after /WE high (Note 12,13) Output disable time after /CAS high (Note 12,13) Output disable time after /RAS high Output hold time from /CAS low
Limits -5,-5S -6,-6S Min Max Min Max 13 15 50 60 25 30 28 33 13 15 5 5 5 5 5 5 13 15 13 15 13 15 13 15 5 5
-7,-7S Unit Min Max ns 20 ns 70 ns 35 ns 40 ns 20 5ns 5ns 5ns ns 20 ns 20 ns 20 ns 20 5ns
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /RAS clock such as /RAS-Only refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 100pF. The reference levels for measuring of output signals are 2.0(VOH)and 0.8(VOL). 8: Assumes that tRCDtRCD(max), tASCtASC(max) and tCPtCP(max). 9: Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRADtRAD(max) and tASCtASC(max). 11: Assumes that tCPtCP(max) and tASCtASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT 10uA) and is not reference to VOH(min) or VOL(max). 13: Output is disable after both /RAS and /CAS go to high
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Symbol tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT
Parameter Refresh cycle time Refresh cycle time(S-version ONLY) /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /RAS high to data Delay time, /CAS high to data Delay time, /OE high to data Transition time
(Note16)
(Note17) (Note18)
(Note19) (Note19) (Note20) (Note20) (Note20) (Note21)
Limits -5,-5S -6,-6S Min Max Min Max 64 64 128 128 30 40 14 37 14 45 5 5 0 0 8 10 10 12 25 30 0 0 10 0 0 13 8 10 8 10 0 0 0 0 13 15 13 15 13 15 1 50 1 50
Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max).
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 6 / 26 )
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Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Limits -5,-5S -6,-6S Unit -7,-7S Min Max Min Max Min Max 84 104 130 ns 50 10000 60 10000 70 10000 ns 8 10000 10 10000 13 10000 ns 35 40 55 ns 13 15 20 ns 0 0 0 ns (Note 22) 0 0 0 ns (Note 22) 0 0 10 ns 25 30 35 ns 13 18 23 ns 13 15 20 ns 13 15 20 ns
Read and Refresh Cycles
Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Parameter Read cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read Setup time after /CAS high Read hold time after /CAS low Read hold time after /RAS low Column address to /RAS hold time Column address to /CAS hold time /RAS hold time after /OE low /CAS hold time after /OE low Unit ns ns ns ns ns ns ns ns ns ns ns ns
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter Write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low (Note 24) Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after /W low Write pulse width Data setup time before /CAS low or /W low Data hold time after /CAS low or /W low Limits -5,-5S -6,-6S Unit -7,-7S Min Max Min Max Min Max 84 104 130 ns 50 10000 60 10000 70 10000 ns 8 10000 10 10000 13 10000 ns ns 35 40 55 13 15 20 ns 0 0 0 ns 8 10 13 ns 8 10 13 ns 8 10 13 ns 8 10 13 ns 0 0 0 ns ns 8 10 13 Unit ns ns ns ns ns ns ns ns ns ns ns ns
Read-Write and Read-Modify-Write Cycles
Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low /OE hold time after /W low (Note21) Limits -5,-5S -6,-6S Min Max Min Max 109 133 75 10000 89 10000 38 10000 44 10000 70 82 38 44 0 0 28 32 65 77 40 47 13 15 Unit -7,-7S Min Max 161 ns 107 10000 ns ns 57 10000 99 ns 57 ns ns 0 ns 42 92 ns ns 57 ns 20 Unit ns ns ns ns ns ns ns ns ns ns
(Note24) (Note24) (Note24)
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWDtCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.
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MITSUBISHI ELECTRIC
( 7 / 26 )
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Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /WE) (Note 25)
Symbol tHPC tHPRWC tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
/RAS low pulse width for read write cycle (Note26) /CAS high pulse width (Note27) /RAS hold time after /CAS precharge Delay time, /CAS precharge to /W low (Note24) Hold time to maintain the data Hi-Z until /CAS access /OE Pulse Width (Hi-Z control) /W Pulse Width (Hi-Z control) Delay time, /CAS low to /W low after read Delay time, Address to /W low after read Delay time, /CAS precharge to /W low after read Delay time, /CAS low to /OE high after read Delay time, Address to /OE high after read Delay time, /CAS prechargeto /OE high after read
Limits -5,-5S -6,-6S Unit -7,-7S Min Max Min Max Min Max 20 25 30ns 55 66 79ns 65 100000 77 100000 92ns 100000 8 13 10 16 10ns 16 28 33 40ns 43 50 62ns 7 7 7ns 7 7 7ns 7 7 7ns 28 32 42ns 40 47 72ns 43 50 82ns 13 15 20ns 25 30 35ns 28 33 40ns
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tRAS(min) is specified as two cycles of /CAS input are performed. 27: tCP(max) is specified as a reference point only.If tCPtCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 28)
Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Limits -5,-5S -6,-6S Min Max Min Max 5 5 10 10 10 10 10 10 -7,-7S Unit Min Max 5 ns 15 ns 5 ns 15 ns Unit ns ns ns ns
Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode.
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( 8 / 26 )
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Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item,line -5S / -6S. The other characteristics and requirements then below are same as normal device.
ELECTRIC CHARACTERISTICS (Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless
Symbol Parameter Test conditions
otherwise noted) (Note 2)
Min
Limits Typ Max 1600
Unit A
/RAS=/CAS<0.2V Average supply current ICC9(AV)* from Vcc Self-Refresh mode -5S,-6S /OE=/W=A0~A12(A11)=Vcc-0.2V or (Note 6) 0.2V output=Vcc-0.2V,0.2V or open
TIMING REQUIREMENTS
Symbol tRASS tRPS tCHS
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits -5S Min Max Min 100 104 - 50 100 84 - 50 -6S Max Unit -7S Min Max us 100 ns 130 ns - 50
Parameter CBR Self Refresh RAS low pulse width CBR Self Refresh RAS high precharge time CBR Self Refresh RAS hold time
Unit us ns ns
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 128 ms and tSN 128 ms. tNS Self refresh period
DISTRIBUTED REFRESH < 128 ms > DISTRIBUTED REFRESH < 128 ms >
tSN
(2) In case of burst refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 16ms and tSN 16 ms. tSN tNS Self refresh period
BURST REFRESH < 128 ms > BURST REFRESH < 128 ms >
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 9 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
(Note 29)
Timing Diagrams Read Cycle
tRC tRAS VIH VIL tCSH tCRP VIH /CAS VIL tRAD tASR Address VIH VIL tRAH tASC tCAH
ROW ADDRESS
tRP
/RAS
tRCD
tRSH tCAS
tCRP
tRAL tCAL
tASR
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ
DQ (OUTPUTS)
tRRH tRCH
/W
tCDD tRDD
DQ (INPUTS)
tREZ tOHR
DATA VALID
tWEZ tOFF tOHC
VOH Hi-Z VOL tRAC tDZO VIH tOEA tOCH tOEZ tODD Hi-Z
/OE VIL tORH
Note 29
Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max) Indicates the invalid output.
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 10 / 26 )
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Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Early Write Cycle
tWC tRAS VIH /RAS VIL tCSH tCRP VIH /CAS VIL tASR VIH Address VIL tASR tRAH tASC tCAH
COLUMN ADDRESS ROW ADDRESS
tRP
tRCD
tRSH tCAS
tCRP
ROW ADDRESS
tWCS VIH /W VIL tDS VIH
tWCH
tDH
DQ (INPUTS)
DATA VALID
VIL
DQ (OUTPUTS)
VOH Hi-Z VOL
VIH /OE VIL
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 11 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Delayed Write Cycle
tWC tRAS VIH VIL tCSH tCRP VIH /CAS VIL tASR tRAH tASC tCAH tASR
ROW ADDRESS
tRP
/RAS
tCRP tRSH tCAS
tRCD
VIH Address VIL
ROW ADDRESS
COLUMN ADDRESS
tCWL tRCS /W VIH VIL tWCH tDZC
DQ (INPUTS)
tRWL tWP
tDS Hi-Z tCLZ
tDH
DATA VALID
VIH VIL
DQ (OUTPUTS)
VOH Hi-Z VOL tDZO tOEZ tODD tOEH Hi-Z
/OE
VIH VIL
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( 12 / 26 )
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Preliminary
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MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH /RAS VIL tCSH tCRP VIH /CAS VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tCRP tRP
VIH Address VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH /W VIL
tAWD tCWD tRWD
tCWL tRWL tWP
tDS tDZC
DQ (INPUTS)
tDH
VIH VIL tCAC tAA tCLZ
Hi-Z
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID
Hi-Z tODD tOEH tOEZ
/OE
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 13 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS VIH /RAS VIL tCSH tCRP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL VIH /W VIL tDZC tCAL tCAL
tRRH tRCH
tWEZ tRDD tCDD tCAC tAA tCLZ Hi-Z tCAC tAA tDOH
DATA VALID-1 DATA VALID-2
DQ (INPUTS)
VIH VIL tCAC tAA tDOH tREZ tOHR tOFF tOHC
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL tOEA tOCH
tCPA
tCPA tOEZ
/OE
VIH tODD
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 14 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS VIH /RAS VIL tCSH tCRP VIH /CAS VIL tCAL tASR VIH Address VIL tRAH tASC tCAH tASC tCAH tASC tCAL tCAH tRCD tCAS tCP tHPC tCAS tRSH tCP tCAS
tRP
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tWCS VIH /W VIL tDS
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
tDS
tDH
tDS
tDH
DQ (INPUTS)
VIH VIL
DATA VALID-1
DATA VALID-2
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL
VIL /OE VIH
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
(15 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read-Write,Read-Modify-Write Cycle
tRAS VIH /RAS VIL tCSH tCRP VIH /CAS VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP tHPRWC tCAS
tRP
tRWL tCRP
tASR
ROW ADDRESS
VIH Address VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tAWD tRCS VIH /W VIL tRWD tDZC VIH VIL Hi-Z tCAC tAA tCLZ
DQ (OUTPUTS)
tAWD tCWL tWP tRCS tCWD tWP
tCWD
tCPWD tDS tDH
DATA VALID-1
tDZC tDS Hi-Z tCAC tAA tCLZ
tDH
DATA VALID-2
DQ (INPUTS)
VOH Hi-Z VOL tRAC tDZO VIH tOEA
DATA VALID-1
Hi-Z tODD tOEZ tCPA tDZO tOEA
DATA VALID-2
Hi-Z tODD tOEH tOEZ
/OE
VIL
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 16 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRAS VIH VIL tCSH tCRP tRCD VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tASC tCAH tASC tCAH tASC tCAH tCAS tCP tHPC tCAS tCP tHPRWC tCAS tCWL tRWL
tRP
/RAS
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL /W VIH VIL tDZC
tWCS
tWCH tCAL
tCPWD tAWD tCWD tWP
tDS
tDH
tDZ
C
tDS
tDH
DQ (INPUTS)
VIH VIL tCAC tAA tCLZ
DATA VALID-2
DATA VALID-3
tAA tCAC tWEZ
DATA VALID-1
tCLZ
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL
tCPA tOEA tOEZ tOCH tDZO tOEA tOEZ tOEH
/OE
VIH tODD tODD
Note30: /OE=L; /W Hi-Z control /OE=H; OE Hi-Z control
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 17 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
VIH /RAS VIL tHPC VIH /CAS VIL tCP tASC VIH Address
COLUMN-1 COLUMN-2 COLUMN-3
tCAS tCAH tASC
tCAS tCAH tASC tCAH
VIL tCAL tRCH tWCS VIH tCAL tWCH
/W VIL tHPWD VIH Hi-Z VIL
tHCWD tHAWD tDS
DATA VALID-2
tDH tDZC
DQ (INPUTS)
tCAC tAA tCPA tWEZ
tCAC tAA tCPA tCLZ
Hi-Z
DQ (OUTPUTS)
VOH VOL tHCOD tHAOD VIL tHPOD
DATA VALID-1
Hi-Z tOEA
DATA VALID-3
tOEZ tODD
tDZC
/OE
VIH
Note30: /OE=L; /W Hi-Z control /OE=H; OE Hi-Z control
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 18 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS VIH /RAS VIL tCSH tCRP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS
tRRH tRCH
VIH /W VIL tWEZ tDZC tRDD tCDD tCAC tAA tCLZ
DQ (OUTPUTS)
DQ (INPUTS)
VIH VIL tCAC tAA tDOH
DATA VALID-1 DATA VALID-1 DATA VALID-2
Hi-Z
tCAC tAA tCLZ Hi-Z tCPA
tREZ tOHR tOFF tOHC
DATA VALID-3
VOH Hi-Z VOL tRAC tDZO VIL tOEA
tOEZ tOCH tOEA
tCPA tCHOL
tOEZ
tOEZ
/OE
VIH tOEPE tOEPE tODD
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 19 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS VIH VIL tCSH tCRP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
/RAS
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS VIH VIL tDZC tWPE tRCH tRCS /W
tRRH tRCH
tRDD tCDD tCAC tAA
DQ (INPUTS)
VIH VIL tCAC tAA tCLZ tCAC tAA tDOH
DATA VALID-1
Hi-Z
tWEZ
DATA VALID-2
tCLZ Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL tOEA tOCH
tCPA
tCPA tOEZ
/OE
VIH tODD
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 20 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS /RAS VIH VIL tRPC tCRP /CAS VIH VIL tASR tRAH tASR tCRP tRP
Address
VIH VIL
ROW ADDRESS
ROW ADDRESS
/W
VIH VIL
DQ (INPUTS)
VIH VIL
DQ (OUTPUTS)
VOH VOL
Hi-Z
VIH /OE VIL
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 21 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
/CAS before /RAS Refresh Cycle
tRC tRP /RAS VIH VIL tRPC tCSR /CAS VIH VIL tCPN tCHR tRAS tRAS
tRC tRP
tRPC
tCSR
tCHR
tRPC
tCRP
tASR Address VIH VIL tRRH tRCH /W VIH VIL tRCS
ROW ADDRESS COLUMN ADDRESS
DQ (INPUTS)
VIH VIL tREZ tOHR tOFF tOHC Hi-Z
DQ (OUTPUTS)
VOH VOL tOEZ VIH
/OE VIL
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 22 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 30)
tRC tRAS /RAS VIH VIL tCRP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tRCS
tRAL
tRRH tRCH
/W
VIH VIL tDZC tCDD tRDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ Hi-Z VOL tRAC tDZO VIH tOEA tORH tOEZ tODD
DATA VALID
tREZ tOHR tOFF tOHC Hi-Z
DQ (OUTPUTS)
VOH
/OE
VIL
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 23 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Self Refresh Cycle
tRP /RAS VIH VIL
tRASS
tRPS
tRPC tRPC tCSR /CAS VIH VIL tCPN tASR VIH Address VIL tRRH tRCH /W VIH VIL tRDD tCDD
DQ (INPUTS)
tCHS
tCRP
ROW ADDRESS
tRCS
VIH VIL
Hi-Z tREZ tOHR tOFF tOHC
DQ (OUTPUTS)
VOH VOL tOEZ VIH tODD
Hi-Z
/OE VIL
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 24 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Outline
67.6
3.63MAX
20
3.3 3.7
23.2 29 23.2
4.6
32.8 32.8
25.40
1.00
MIT-DS-0233-0.0
MITSUBISHI ELECTRIC
( 25 / 26 )
24/Jul./1998
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
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