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IDT29FCT52AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL REGISTERED TRANSCEIVER
FEATURES:
* * * *
IDT29FCT52AT/BT/CT
* * * *
A, B, and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 64mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permit "live insertion" Available in SOIC, SSOP, and QSOP packages
DESCRIPTION:
The IDT29FCT52T is an 8-bit registered transceiver built using an advanced dual metal CMOS technology. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-state output enable signals are provided for each register. Both A outputs and B outputs are guaranteed to sink 64mA.
FUNCTIONAL BLOCK DIAGRAM
CPA CEA A0 A1 A2 A3 A4 A5 A6 A7 D0 CE D1 D2 D3 D4 D5 D6 D7 A Reg. CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
OEB B0 B1 B2 B3 B4 B5 B6 B7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE OEA B Reg.
D0 D1 D2 D3 D4 D5 D6 CP D7 CPB CEB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
AUGUST 2000
DSC-5483/1
(c) 2000 Integrated Device Technology, Inc.
IDT29FCT52AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +7 -65 to +150 -60 to +120 Unit V C mA TSTG IOUT
B7 B6 B5 B4 B3 B2 B1 B0 OEB CPA CEA GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC A7 A6 A5 A4 A3 A2 A1 A0 OEA CPB CEB
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by =0.5V unless otherwise noted. 2. All device terminals.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
SOIC/ SSOP/ QSOP TOP VIEW
REGISTER FUNCTION TABLE (1)
(Applies to A or B Register)
D X L H Inputs CP X CE H L L Internal Q NC L H Function Hold Data Load Data
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care NC = No Change = LOW-to-HIGH Transition
OUTPUT CONTROL (1)
Internal OE H L L Q X L H Y-Outputs Z L H Function Disable Outputs Enable Outputs
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
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IDT29FCT52AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name A0-7 B0-7 CPA CEA OEB CPB CEB OEA I/O I/O I/O I I I I I I Description Eight bidirectional lines carrying the A Register inputs or B Register outputs. Eight bidirectional lines carrying the B Register inputs or A Register outputs. Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions. Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When OEB is HIGH, the B0-7 outputs are in the high-impedance state. Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions. Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When OEA is HIGH, the A0-7 outputs are in the high-impedance state.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State Output pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VCC = Max., VI = VCC (Max.) VCC = Min., IIN = -18mA -- VCC = Max., VIN = GND or VCC VI = 2.7V VI = 0.5V VI = 2.7V VI = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 Unit V V A A A A V mV A
OUTPUT DRIVE CHARACTERISTICS
VOH VOL IOS IOFF Output HIGH Voltage Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5) VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Max., VO = GND(3) VCC = Max., VIN or VO 4.5V IOH = -8mA IOH = -15mA IOL = 64mA 2.4 2 -- -60 -- 3.3 3 0.3 -120 -- -- -- 0.55 -225 1 V V mA A
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
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IDT29FCT52AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OEA or OEB = GND One Input Togging 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEA or OEB = GND One Bit Togging at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEA or OEB = GND Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
Test Conditions(1)
Min. --
Typ.(2) 0.5 0.15
Max. 2 0.25
Unit mA mA/ MHz
VIN = VCC VIN = GND
--
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
1.5
3.5
mA
VIN = 3.4V VIN = GND VIN = VCC VIN = GND
--
2
5.5
--
3.8
7.3(5)
VIN = 3.4V VIN = GND
--
6
16.3(5)
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IDT29FCT52AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
29FCT52AT Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW Parameter Propagation Delay CPA, CPB to Ax, Bx Output Enable Time OEA or OEB to Ax, Bx Output Disable Time OEA or OEB to Ax, Bx Set-up Time, HIGH or LOW Ax, Bx to CPA, CPB Hold Time, HIGH or LOW Ax, Bx to CPA, CPB Set-up Time, HIGH or LOW CEA, CEB to CPA, CPB Hold Time, HIGH or LOW CEA, CEB to CPA, CPB Clock Pulse Width HIGH or LOW(3) 3 -- 3 -- 3 -- ns 2 -- 2 -- 2 -- ns 3 -- 3 -- 3 -- ns 2 -- 1.5 -- 1.5 -- ns 2.5 -- 2.5 -- 2.5 -- ns 1.5 10 1.5 7.5 1.5 6.5 ns Condition(1) CL = 50pF RL = 500 1.5 10.5 1.5 8 1.5 7 ns Min.(2) 2 Max. 10 29FCT52BT Min.(2) 2 Max. 7.5 29FCT52CT Min.(2) 2 Max. 6.3 Unit ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This limit is guaranteed but not tested.
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IDT29FCT52AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 VIN Pulse G enerator D.U.T. 50pF R
T
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
V OU T
500 C
L
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA INPUT tSU TIMING INPUT ASYNCHRO NOUS CONTROL PRESET CLEAR ETC. SYNCHRON OUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIG H PULSE
Octal link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH O UTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
Octal link
DISABLE 3V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW SW ITCH CLO SED tPZH OUTPUT NORMALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V tPLZ
1.5V 0V 3.5V VOL VOH
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT29FCT52AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT29FCT XXXX Device Type X Package
SO PY Q
Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package
52AT 52BT 52CT
Octal Registered Transceiver
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for Tech Support: logichelp@idt.com (408) 654-6459
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