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HCC4724B HCF4724B
8 BIT ADDRESSABLE LATCH
.SERI .STORAGEREGI .CANFUNCTI .STANDARDI .100%TESTEDFORQUI .MAXI .NOI .5V,10V,AND15VPARAMETRI .MEETSALLREQUI .MULTI .A/
APPLICATION -LINE DECODERS D CONVERTERS
AL DATA INPUT - ACTIVE PARALLEL OUTPUT STER CAPABILITY - MASTER CLEAR ON AS DEMULTIPLEXER ZED, SYMMETRICAL OUTPUT CHARACTER ESCENT CURRENT AT 20V MUM INPUT CURRENT OF 1A AT 18V (full package-temperature range), 100nA AT 18V AND 25oC SE MARGIN (full package-temperature range) = 1V AT VDD = 5V, 2V AT VDD = 10V, 2.5V AT VDD = 15V C RATINGS REMENTS OF JEDEC TENTATIVE STANDARD N. 13A, " STANDARD SPECIFICATIONS FOR DESCRIPTION OF ' B ' SERIES CMOS DEVICES "
EY (Plastic Package)
F (Ceramic Package)
M1 (Micro Package)
C1 (Chip Carrier)
ORDER CODES : HCC4724BF HCF4724BM1 HCF4724BEY HCF4724BC1
PIN CONNECTIONS DESCRIPTION The HCC/HCF4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at low level. When WRITE DISABLE is high, data entry is inhibited however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic " 0 " level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer ; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic " 0 " level.
September 1988 1/14
HCC/HCF4724B
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATING
Symbol VDD * Vi II Ptot Parameter Supply Voltage: HCC Types HCF Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package Temperature Range Operating Temperature: HCC Types HCF Types Storage Temperature Value -0.5 to +20 -0.5 to +18 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -40 to +85 -65 to +150 Unit V V V mA mW mW
o o o
Top Tstg
C C C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Parameter Supply Voltage: HCC Types HCF Types Input Voltage Operating Temperature: HCC Types HCF Types Value 3 to 18 3 to 15 0 to VDD -55 to +125 -40 to +85 Unit V V V
o o
C C
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HCC/HCF4724B
LOGIC DIAGRAM
Definition of WRITE DISABLE ON Time
MODE SELECTION
TYPE A B WD 0 0 R 0 1 Addressed Latch Follows Data Follows Data (Active High 8-Channel Demultiplexer) Unaddressed Latch Hold Previous State Reset to "0"
C D
1 1
0 1
Hold Previous State Reset to "0" Reset to "0"
WD = WRITE DISABLE R= RESET
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HCC/HCF4724B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Test Conditios Symbol IL Parameter Quiescent Current VI (V) 0/5 HCC Types 0/10 0/15 0/20 HCF Types V OH Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Output Drive Current 0/5 HCC Types 0/5 0/10 0/15 0/5 HCF Types 0/5 0/10 0/15 IOL Output Sink Current HCC Types HCF Types IIH, IIL CI Input Leakage Current Input Capacitance 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0/5 0/10 0/15 0/5 0/10 0/15 5/0 10/0 15/0 VIH 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.4 0.5 1.5 Any Input Any Input <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 5 10 15 5 10 15 5 10 15 18 -2 -0.64 -1.6 -4.2 -1.8 -0.61 -1.5 -4 0.64 1.6 4.2 0.61 1.5 4 0.1 3.5 7 11 1.5 3 4 -1.6 -0.51 -1.3 -3.4 -1.6 -0.51 -1.3 -3.4 0.51 1.3 3.4 0.51 1.3 3.4 -3.2 -1 -2.6 -6.8 -3.2 -1 -2.6 -6.8 1 2.6 6.8 1 2.6 6.8 10-5 5 0.1 7.5 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.15 -0.36 -0.9 -2.4 -1.3 -0.42 -1.1 -2.8 0.36 0.9 2.4 0.42 1.1 2.8 1 A pF mA mA TLOW * Min. Max. 5 10 20 100 20 40 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 V V Value 25 oC Min. Typ. Max. 0.04 0.04 0.04 0.08 0.04 0.04 0.04 5 10 20 100 20 40 80 4.95 9.95 14.95 0.05 0.05 0.05 V V THIGH * Min. Max. 150 300 600 3000 150 300 600 A Unit
VOL
V IL
IOH
* TLOW = -55 oC for HCC device: -40 oC for HCF device. * THIGH = +125 oC for HCC device: +85 oC for HCF device. The Noise Margin for both "1" and "0" level is: 1V min. with VDD = 5 V, 2 V min. with VDD = 10 V, 2.5 V min. with VDD = 15 V
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HCC/HCF4724B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 o C, C L = 50 pF, RL = 200 K, o typical temperature coefficent for all VDD values is 03 %/ C, all input rise and fall times= 20 ns)
Symbol tPLH tPHL tPLH tPHL tPHL Parameter Propagation Delay Time Data to Output Propagation Delay Time Write Disable to Output Propagation Delay Time Reset to Output Propagation Delay Time Address to Output Transition Time Any Output Test Conditions VDD (V) (See Figure 1) 5 10 15 (See Figure 1) 5 10 15 (See Figure 1) 5 10 15 (See Figure 1) 5 10 15 5 10 15 (See Figure 1) 5 10 15 (See Figure 1) 5 10 15 (See Figure 1) 5 10 15 (See Figure 1) 5 10 15 (See Figure 1) 5 10 15 Any Input Min. Value Typ. 200 75 50 200 80 60 175 80 65 225 100 75 100 50 40 100 50 40 200 100 65 75 40 25 50 25 20 75 40 25 5 Max. 400 150 100 400 160 120 350 160 130 450 200 150 200 100 80 200 100 80 400 200 125 150 75 50 100 50 35 150 75 50 7.5 Unit
ns
ns
ns
tPLH tPHL tTLH tTHL tW
ns
ns
Minimum Pulse Width Data Minimum Pulse Width Address Minimum Pulse Width Reset
ns
ns
ns
ts
Minimum Setup Time Data to Write Disable Minimum Holf Time Data to Write Disable Input Capacitance
ns
tH
ns pF
CIN
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HCC/HCF4724B
Figure 1: Master Timing Diagram
TYPICAL APPLICATIONS A/D Converter
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HCC/HCF4724B
Multiple Selection Decoding - 4 x 4 Crosspoint Switch
1 of 6 Decoder/Demultiplexer
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HCC/HCF4724B
Typical Output Low (sink) Current Characteristics Minimum Output Low (sink) Current Characteristics
Typical Output High (source) Current Characteristics
Minimum Output High (source) Current Characteristics
Typical Propagation Delay Time (data to Qn) vs Load Capacitance
Typical Transition Time vs Load Capacitance
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HCC/HCF4724B
Typical Dynamic Power Dissipation vs Address Cycle Time
TEST CIRCUITS Quiescent Device Current. Noise Immunity.
Input Leakage Current.
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HCC/HCF4724B
Plastic DIP16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
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HCC/HCF4724B
Ceramic DIP16/1 MECHANICAL DATA
mm MIN. A B D E e3 F G H L M N P Q 7.8 2.29 0.4 1.17 0.22 0.51 0.38 17.78 2.79 0.55 1.52 0.31 1.27 10.3 8.05 5.08 0.307 0.090 0.016 0.046 0.009 0.020 3.3 0.015 0.700 0.110 0.022 0.060 0.012 0.050 0.406 0.317 0.200 TYP. MAX. 20 7 0.130 MIN. inch TYP. MAX. 0.787 0.276
DIM.
P053D
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HCC/HCF4724B
SO16 (Narrow) MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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HCC/HCF4724B
PLCC20 MECHANICAL DATA
mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180
DIM.
P027A
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HCC/HCF4724B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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