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DM74ALS174 * DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
September 1986 Revised February 2000
DM74ALS174 * DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.
Features
s Advanced oxide-isolated ion-implanted Schottky TTL process s Pin and functional compatible with LS family counterpart s Typical clock frequency maximum is 80 MHz s Switching performance guaranteed over full temperature and VCC supply range
Ordering Code:
Ordering Code DM74ALS174M DM74ALS174SJ DM74ALS174N DM74ALS175M DM74ALS175SJ DM74ALS175N Package Number M16A M16D N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
DM74ALS174 DM74ALS175
(c) 2000 Fairchild Semiconductor Corporation
DS006112
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DM74ALS174 * DM74ALS175
Function Table
Inputs Clear L H H H Clock X L D X H L X Q L H L Q0 Outputs Q (Note 1) H L H Q0
H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care = Transition from LOW-to-HIGH Level Q0 = the level of Q before the indicated steady-state input conditions were established Note 1: applies to DM74ALS175 only
Logic Diagrams
DM74ALS174 DM74ALS175
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2
DM74ALS174 * DM74ALS175
Absolute Maximum Ratings(Note 2)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 77.9C/W 107.3C/W 7V 7V 0C to +70C -65C to +150C
Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol Parameter Min Nom Max Units
VCC VIH VIL IOH IOL tW
Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width Clock HIGH or LOW Clear LOW
4.5 2
5
5.5 0.8 -0.4 8
V V V mA mA ns
10 10 10 6 0 0 0 50 70
tSETUP
Setup Time (Note 3)
Data Input Clear Inactive State
ns ns MHz C
tHOLD fCLOCK TA
Data Hold Time (Note 3) Clock Frequency Free Air Operating Temperature
Note 3: The symbol indicates that the rising edge of the clock is used as reference.
3
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DM74ALS174 * DM74ALS175
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25C. Symbol VIK VOH VOL II IIH IIL IO ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current at Max Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current IOH = -400 A VCC = 4.5V to 5.5V VCC = 4.5V VCC = 5.5V, VIN = 7V VCC = 5.5V, VIH = 2.7V VCC = 5.5V, VIN = 0.4V VCC = 5.5V, VO = 2.25V VCC = 5.5V Clock = 4.5V Clear = GND D Input = GND DM74ALS174 DM74ALS175 -30 11 8 IOL = 8 mA Conditions VCC = 4.5V, IIN = -18 mA VCC - 2 VCC - 1.6 0.35 0.5 0.1 20 -0.1 -112 19 mA 14 Min Typ Max -1.5 Units V V V mA A mA mA
Switching Characteristics
over recommended operating free air temperature range Symbol fMAX tPLH Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output From Clear (175 Only) tPHL Propagation Delay Time HIGH-to-LOW Level Output From Clear tPLH Propagation Delay Time LOW-to-HIGH Level Output From Clock tPHL Propagation Delay Time HIGH-to-LOW Level Output From Clock 5 17 ns 3 15 ns 8 23 ns RL = 500 CL = 50 pF VCC = 4.5V to 5.5V 5 18 ns Conditions Min 50 Max Units MHz
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4
DM74ALS174 * DM74ALS175
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
5
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DM74ALS174 * DM74ALS175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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DM74ALS174 * DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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