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| 1.25-GHz PLL with Prescaler 2.5-GHz PLL with Prescaler PMB 2308 B6HF PMB 2309 B6HF General Description The PMB 2308, PMB 2309 are Phase Locked Loop (PLL) synthesizers with programmable frequency dividers for use in mobile communication equipment. It is fabricated using Siemens B6HF silicon bipolar process. The circuit consists of high speed dual modulus divider, shift register, programmable counter (A-, N- and R-counter), phase detector with charge pump and a control logic block. Since the high speed dual modulus divider is able to handle frequencies of up to 1.25 (2.5) GHz, there is no need to add a dedicated external prescaler. The switching signals for the dividing ratio 16/17 (32/33) is generated by the A-counter. The A-counter and the N-down-counter are programmable via the 3-wire bus. They are clocked by the dual modulus divider output signal. The carry output of the N-counter is connected to the frequency input of the phase detector and is controlling the loading of the programmed A-/N-counter start values. The 11 bit R-counter is also programmable and is serving as reference frequency divider. Its carry output is connected to the reference frequency input of the phase detector and is controlling the loading of the programmed counter start value. The phase detector is of PFD-type (phase and frequency sensitive). It has a linear output characteristic in the 0 phase error region. The control logic handles phase detector output polarity, charge pump output current and software-generated powerdown (all circuit parts except the shift registers and data latches). Applications All mobile communication analog and digital systems as RFand IF synthesizers Type PMB 2308-R PMB 2309-R Features * * * * * * * * Package P-TSSOP-16-1 (Shrink, SMD) P-TSSOP-16-1 (Shrink, SMD) * * * * * * * * Integrated prescaler Low operating current Different power-down modes High input sensitivity, high input frequency Fast phase detector without dead zone Linearization of the phase detector output by current sources Large dividing ratios for small channel spacing PLL PMB 2308 PMB 2309 max. freq. 1.25 GHz 2.5 GHz prescaler: :16/:17 :32/:33 A-counter 0 to 15 0 to 31 N-counter 16 to 4095 32 to 2047 R-counter 3 to 2047 3 to 2047 Serial control (3-wire bus: data, clock, enable) for fast programming (fmax = 10 MHz) Switchable polarity and phase detector current programmable 1 port output (TTL push-pull) External current setting for phase detector output Lock detect output with gated pulse (quasi-digital lock detect) Operating voltage 2.7 V to 5.5 V P-TSSOP-16 package Temperature range - 30 C to 85 C Siemens Aktiengesellschaft 1 1.25-GHz PLL with Prescaler 2.5-GHz PLL with Prescaler PMB 2308 PMB 2309 RF1 RF1 Divider /16 / 17 (/32 / 33) f VCOA CP 4 (5) Bit CY A1-Counter D0 ... D3 LD CP 12 (11) Bit N- Counter LD CY D4 ... D15 1 Bit Latch (Idle) CLK DA EN 1 Bit Adress 3 Bit Latch Control & Test 4 Bit Latch A-Counter 12 Bit Latch MSB (17 + 1) Bit Shift Register 3 Bit Latch Charge Pump Shifted First MSB 11 Bit Latch R- Counter LD RI CP R0 ... R10 11 Bit R- Counter CY f REF f VCON V CC 1 GND 1 CT0, CT1, P0 Control & Test CP0 ... CP2 Phase Detector Power Down V CC2 GND 2 PON PD LD I REF Port ITB08471 Block Diagram Siemens Aktiengesellschaft 2 |
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