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FIN1049 LVDS Dual Line Driver with Dual Line Receiver
March 2003 Revised March 2003
FIN1049 LVDS Dual Line Driver with Dual Line Receiver
General Description
This dual Driver-Receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The Driver accepts LVTTL inputs and translates them to LVDS outputs. The Receiver accepts LVDS inputs and translates them to LVTTL outputs. The LVDS levels have a typical differential output swing of 350mV which provide for low EMI at ultra low power dissipation even at high frequencies. The FIN1049 can accept LVPECL inputs for translating from LVPECL to LVDS. The En and Enb inputs are ANDed together to enable/disable the outputs. The enables are common to all four outputs. A single line driver and single line receiver function is also available in the FIN1019.
Features
s Greater than 400 Mbps data rate s 3.3V power supply operation s Low power dissipation s Fail safe protection for open-circuit conditions s Meets or exceeds the TIA/EIA-644-A LVDS standard s 16-pin TSSOP package saves space s Flow-through pinout simplifies PCB layout s Enable/Disable for all outputs s Industrial operating temperature range:
-40C to +85C
Ordering Code:
Order Number FIN1049MTC Package Number MTC16 Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pin Descriptions
Pin Name RIN1+, RIN2+ RIN1-, RIN2- Description Non-Inverting LVDS Inputs Inverting LVDS Inputs
Connection Diagram
DOUT1+, DOUT2+ Non-Inverting Driver Outputs DOUT1-, DOUT2- Inverting Driver Outputs EN, ENb ROUT1, ROUT2 DIN2, DIN2 VCC GND Driver Enable Pins for All Outputs LVTTL Output Pins for ROUT1 and ROUT2 LVTTL Input Pins for DIN1 and DIN2 Power Supply (3.3V) Ground
(c) 2003 Fairchild Semiconductor Corporation
DS500846
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FIN1049
Function Table
Inputs EN H H L L H
H = HIGH Logic Level L = LOW Logic Level or OPEN X = Don't Care Z = High Impedance Note 1: Any unused Receiver Inputs should be left Open.
Outputs (LVTTL) ENb L H H L L ROUT1 ON Z Z Z H ROUT2 ON Z Z Z H
Inputs (LVDS) (Note 1) RIN#+ RIN#-
Outputs (LVDS) DOUT#+ ON Z Z Z DOUT#- ON Z Z Z
Open Current Fail Safe Condition
Functional Diagram
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FIN1049
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) LVDS DC Input Voltage (VIN) LVDS DC Output Voltage (VOUT) Driver Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) ESD (Human Body Model) ESD (Machine Model) 260C
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V
Continuous 10mA
Recommended Operating Conditions
Supply Voltage (VCC) Magnitude of Differential Voltage (|VID|) Operating Temperature (TA) 100mV to VCC 3.0V to 3.6V
-65C to +150C
150C
-40C to +85C
>7000V >250V
Note 2: The "Absolute Maximum Ratings": are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions Min Typ (Note 3) 0.0 -100 VID/2 0.0 VCC - (VID/2) 20.0 2.0 GND VIN = 0V or VCC VIK = -18mA -1.5 250 RL = 100, Driver Enabled, See Figure 2 1.125 1.25 -0.7 350 450 35.0 1.375 25.0 DOUT+ = 0V & DOUT- = 0V, Driver Enabled VOD = 0V, Driver Enabled VCC = 0V, VOUT = 0V or VCC Driver Disabled, DOUT+ = 0V or VCC or DOUT- = 0V or VCC CMOS/LVTTL Output DC Specifications (ROUT1, ROUT2) VOH VOL IOZ ICC ICCZ CIND COUT CINT Output High Voltage Output Low Voltage Disabled Output Leakage Current Power Supply Current (Note 4) Power Supply Current Input Capacitance Output Capacitance Input Capacitance IOH = -2mA, VID = 200mV IOL = 2mA, VID = 200mV Driver Disabled, ROUTn = 0V or VCC Drivers Enabled, Any Valid Input Condition Drivers Disabled LVDS Input LVDS Output LVTTL Input 3.0 4.0 3.5 2.7 0.250 10.0 25.0 10.0 V V A mA mA pF pF pF -9.0 -9.0 20.0 10.0 VCC 0.8 20.0 35.0 Max Units
LVDS Input DC Specifications (RIN1+, RIN1-, RIN2+, RIN2-) See Figure 1 and Table 1 VTH VTL VIC IIN VIH VIL IIN Differential Input Threshold HIGH Differential Input Threshold LOW Common Mode Voltage Range Input Current Input High Voltage (LVTTL) Input Low Voltage (LVTTL) Input Current (EN, ENb, DIN1, DIN2, RINx+, and RINx-) VIK VOD VOD VOS VOS IOS IOSD IOFF IOZD Input Clamp Voltage Output Differential Voltage VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage Offset Magnitude Change from Differential LOW-to-HIGH Short Circuit Output Current Power-Off Input or Output Current Disabled Output Leakage Current A V mV mV V mV mA mA A A VCM = 1.2V, 0.05V, 2.35V VID = 100mV, VCC = 3.3V VCC = 0V or 3.6V, VIN = 0V or 2.8V CMOS/ LVTTL Input DC Specifications (EN, ENb, DIN1, DIN2) V V mV mV V mA
LVDS Output DC Specifications (DOUT1+, DOUT1-, DOUT2+, DOUT2-)
Note 3: All typical values are at TA = 25C and with VCC = 3.3V. Note 4: Both driver and receiver inputs are static. All LVDS outputs have 100 load. None of the outputs have any lumped capacitive load.
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FIN1049
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions Switching Characteristics - LVDS Outputs tPLHD tPHLD tTLHD tTHLD tSK(P) tSK(LH), tSK(HL) tSK(PP) tPZHD tPZLD tPHZD tPLZD fMAXD tPHL tPLH tSK1 tSK2 tSK3 tLHR tHLR tPHZ tPLZ tPZH tPZL fMAXT Part-to-Part Skew (Note 7) Differential Output Enable Time from Z-to-HIGH Differential Output Enable Time from A-to-LOW Differential Output Disable Time from HIGH-to-Z Differential Output Disable Time from LOW-to-Z Maximum Frequency (Note 8) Propagation Delay HIGH-to-LOW Propagation Delay LOW-to-HIGH Pulse Skew Channel-to-Channel Skew Part-to-Part Skew Transition Time LOW-to-HIGH Transition Time HIGH-to-LOW Disable Time HIGH-to-Z Disable Time LOW-to-Z Enable Time Z-to-HIGH Enable Time Z-to-LOW Maximum Frequency (Note 9) See Figure 7 See Figures 9, 10 See Figure 3 Switching Characteristics - LVTTL Outputs Measured from 20% to 80% signal VID = 200mV; Distributed Load CL = 15pF and 50; RL = 1K; VOS = 1.2V; See Figures 7, 8 0.5 0.5 0.0 0.0 0.0 0.1 0.1 2.2 1.3 1.8 0.9 200 0.25 0.18 4.5 3.5 3.0 1.4 1.0 1.0 35.0 50.0 3.5 3.5 400 500 1.0 1.4 1.4 8.0 8.0 7.0 7.0 ns ns ps ps ns ns ns ns ns ns ns MHz 200 See Figures 5, 6 Differential Propagation Delay LOW-to-HIGH Differential Propagation Delay HIGH-to-LOW Differential Output Rise Time (20% to 80%) Differential Output Fall Time (80% to 20%) Pulse Skew |tPLH - tPHL| Channel-to-Channel Skew (Note 6) See Figures 3, 4 0.2 0.2 2.0 2.0 1.0 1.0 0.35 0.35 1.0 6.0 6.0 3.0 3.0 ns ns ns ns ns ns ns ns ns ns ns MHz Min Typ (Note 5) Max Units
Note 5: All typical values are at TA = 25C and with VCC = 3.3V. Note 6: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 7: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 8: fMAX generator input conditions: tr = tf < 1ns (10% to 90%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45% / 55%, VOD > 250mV, all channels switch. Note 9: fMAXT generator input conditions: tr = tf < 1ns (10% to 90%), 50% duty cycle, VID = 200mV, VCM = 1.2V. Output criteria: duty cycle = 45% / 55%, VOH > 2.7V. VOL < 0.25V, all channels switching.
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FIN1049
Required Specifications
1. Human Body Model ESD and Machine Model ESD should be measured using MIL-STD-883C method 3015.7 standard. 2. Latch-up immunity should be tested to the EIA/JEDEC Standard Number 78 (EIA/JESD78).
Note: CL = 15pF, includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) VIA 1.25 1.15 VCC VCC - 0.1 0.1 0.0 1.75 0.65 VCC VCC - 1.1 1.1 0.0 VIB 1.15 1.25 VCC - 0.1 VCC 0.0 0.1 0.65 1.75 VCC - 1.1 VCC 0.0 1.1 Resulting Differential Input Voltage (mV) VID 100 Resulting Common Mode Input Voltage (V) VIC 1.2 1.2 VCC - 0.05 VCC - 0.05 0.05 0.05 1.2 1.2 VCC - 0.55 VCC - 0.55 0.55 0.55
-100
100
-100
100
-100
1100
-1100
1100
-1100
1100
-1100
Note: RL = 100
FIGURE 2. LVDS Output Circuit for DC Test
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FIN1049
Required Specifications
(Continued)
Note A: RL = 100 Note B: ZO = 50 and CT = 15 pF Distributed
FIGURE 3. LVDS Output Propagation Delay and Transition Time Test Circuit
FIGURE 4. LVTTL Input to LVDS Output AC Waveform
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FIN1049
Required Specifications
(Continued)
Note A: RL = 100 Note B: ZO = 50 and CT = 15 pF Distributed Note: R1 = 1000, RS = 950 Note: VTST = 2.4V
FIGURE 5. LVDS Output Enable / Disable Delay Test Circuit
FIGURE 6. LVDS Output Enable / Disable Timing Waveforms
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FIN1049
Required Specifications
(Continued)
Note A: ZO = 50 and CT = 15 pF Distributed Note: RL = 100 and RS = 950
FIGURE 7. LVTTL Output Propagation Delay and Transition Time Test Circuit
FIGURE 8. LVDS Input to LVTTL Output Propagation Delay and Transition Time Waveforms
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FIN1049
Required Specifications
(Continued)
Note A: ZO = 50 and CT = 15 pF Distributed Note: RL = 100, R1 = 1000, and RS = 950
FIGURE 9. LVTTL Output Enable / Disable Test Circuit
FIGURE 10. LVTTL Output Enable / Disable Timing Waveforms
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FIN1049 LVDS Dual Line Driver with Dual Line Receiver
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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