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| 14/12/10-Bit, 1200 MSPS D/A Converters Preliminary Technical Data FEATURES * * * * * * * * * * 1.8/3.3 V Single Supply Operation AD9736 SFDR > 53 dBc to fOUT = 600 MHz AD9736 IMD > 65 dBc to fOUT = 600 MHz AD9736 DNL = 1.0 LSB AD9736 INL = 2.0 LSB Low power: 380 mW (IOUTFS = 20 mA; fOUT = 330 MHz) LVDS data interface with on-chip 100 terminations Analog Output: Adjustable 10-30mA (RL=25 to 50 ) On-Chip 1.2 V Reference 160 pin BGA Package AD9736/AD9735/AD9734 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS * * * * * Instrumentation Automatic Test Equipment RADAR Avionics Wideband Communications Systems: - Point-to-Point Wireless - LMDS - PA Linearization Figure 1. Functional Block Diagram PRODUCT HIGHLIGHTS Ultra-low Noise and Intermodulation Distortion (IMD) enable high quality synthesis of wideband signals at intermediate frequencies up to 600 MHz. LVDS receivers support Double Data Rate (DDR) input format, with the maximum conversion rate of 1200 MSPS. Manufactured on a CMOS process, the AD9736 family uses a proprietary switching technique that enhances dynamic performance. The current output(s) of the AD9736 family can be easily configured for various single-ended or differential circuit topologies. PRODUCT DESCRIPTION The AD9736, AD9735, and AD9734 are high performance, high frequency DACs that provide sample rates of up to 1200 MSPS, permitting multi-carrier generation up to their Nyquist frequency. The AD9736 is the 14 bit member of the family, while the AD9735 and the AD9734 are the 12 and 10 bit members, respectively. They include a serial port interface (SPI) that provides for programming many internal parameters and also enables read-back of status registers. They use a reduced specification LVDS interface to minimize data interface that may degrade performance. The output current can be programmed over a range of 10mA to 30mA. The AD9736 family is manufactured on a 0.18m CMOS process and operates from 1.8V and 3.3V supplies for a total power consumption of 380mW in bypass mode. It is supplied in a 160 pin BGA package for reduced package parasitics. Rev. PrC 4/05/2004 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD9736/AD9735/AD9734 TABLE OF CONTENTS AD9736/35/34--Specifications .............................................................3 DC SPECIFICATIONS ......................................................................3 DIGITAL SPECIFICATIONS............................................................4 Preliminary Technical Data AC SPECIFICATIONS .......................................................................5 EXPLANATION OF TEST LEVELS ................................................6 REVISION HISTORY Revision PrA: Initial Version Revision PrB: Updated data based on initial evaluation results Revision PrC: Updated data for web display and ongoing evaluation results Rev. PrC | Page 2 of 8 Preliminary Technical Data AD9736/35/34--SPECIFICATIONS1 DC SPECIFICATIONS AD9736/AD9735/AD9734 (VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED) AD9736 Parameter RESOLUTION ACCURACY Integral Nonlinearity (DNL) Differential Nonlinearity (INL) Offset Error Gain Error (With Internal Reference) Gain Error (Without Internal Reference) ANALOG OUTPUTS Full Scale Output Current Output Compliance Range Output Resistance Output Capacitance Offset TEMPERATURE DRIFT Gain Reference Voltage REFERENCE ANALOG SUPPLY VOLTAGES Internal Reference Voltage Output Current VDDA33 VDDA18 VDDD33 DIGITAL SUPPLY VOLTAGES POWER CONSUMPTION VDDD18 VDDCLK Bypass Mode FIR Filter Enabled Standby Power 3.13 1.70 3.13 1.70 1.70 10 1.0 TBD TBD TBD TBD TBD 1.2 100 3.3 1.8 3.3 1.8 1.8 380 550 3.47 1.90 3.47 1.90 1.90 3.13 1.70 3.13 1.70 1.70 Temp Test Level Min Typ 14 2.0 1.0 TBD 0.5 0.5 20 30 10 1.0 TBD TBD TBD TBD TBD 1.2 100 3.3 1.8 3.3 1.8 1.8 380 550 3.47 1.90 3.47 1.90 1.90 3.13 1.70 3.13 1.70 1.70 TBD 0.5 0.5 20 30 10 1.0 TBD TBD TBD TBD TBD 1.2 100 3.3 1.8 3.3 1.8 1.8 380 550 3.47 1.90 3.47 1.90 1.90 TBD 0.5 0.5 20 30 Max Min AD9735 Typ 12 Max Min AD9734 Typ 10 Max Bits LSB LSB % FSR % FSR % FSR mA V k pF ppm/C ppm/C ppm/C V nA V V V V V mW mW mW Unit Table 1: DC Specifications 1 Specifications subject to change without notice Rev. PrC | Page 3 of 8 AD9736/AD9735/AD9734 DIGITAL SPECIFICATIONS1 Preliminary Technical Data (VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED) Parameter Temp Test Level AD9736,35,34 Min Input voltage range, Via or Vib Input differential threshold Input differential hysteresis Receiver differential input impedance LVDS input rate LVDS data Bit Error Rate Input voltage range, Via or Vib Input differential threshold Input differential hysteresis Receiver differential input impedance Maximum Clock Rate Output voltage high, Voa or Vob Output voltage low, Voa or Vob Output differential voltage Output offset voltage Output impedance, single ended LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT-) Ro mismatch between A & B Change in |Vod| between `0' and `1' Change in Vos between `0' and `1' Output current - Driver shorted to ground Output current - Drivers shorted together Power-off output leakage Maximum Clock Rate Differential peak-to-peak Voltage Common Mode Voltage Maximum Clock Rate Maximum Clock Rate (SCLK) Maximum Pulse width high Maximum pulse width low 825 -100 25 80 1200 10-9 825 -100 25 80 600 1375 1025 180 1150 80 200 100 220 1250 120 10 25 25 3 3 TBD 600 800 400 1200 40 TBD TBD 1575 100 120 Typ Max 1575 100 120 mV mV mV MSPS Err/Bit mV mV mV MHz mV mV mV mV % mV mV mA mA mA MHz mV mV MHz MHz ns ns Unit LVDS DATA INPUTS (DB[13:0]+, DB[13:0]-) LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN-) DAC CLOCK INPUT (CLK+, CLK-) SERIAL PERIPHERAL INTERFACE Table 2: Digital Specifications 1 LVDS Drivers and Receivers are compliant to the IEEE-1596 Reduced Range Link, unless otherwise noted Rev. PrC | Page 4 of 8 Preliminary Technical Data AC SPECIFICATIONS AD9736/AD9735/AD9734 (VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED) AD9736 Parameter Maximum Update Rate Output Settling Time (tst) (to 0.025%) DYNAMIC PERFORMANCE Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) Output Noise (IoutFS=20mA) fDAC = 1200 MSPS, fOUT = 50 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 1200 MSPS, fOUT = 100 MHz fDAC = 1200 MSPS, fOUT = 316 MHz fDAC = 1200 MSPS, fOUT = 550 MHz fDAC = 1200 MSPS, fOUT = 50 MHz Two Tone Intermodulation Distortion (IMD) fDAC = 1200 MSPS, fOUT = 100 MHz fDAC = 1200 MSPS, fOUT = 316 MHz fDAC = 1200 MSPS, fOUT = 550 MHz fDAC = 1200 MSPS, fOUT = 50 MHz Noise Spectral Density (NSD) fDAC = 1200 MSPS, fOUT = 100 MHz fDAC = 1200 MSPS, fOUT = 316 MHz fDAC = 1200 MSPS, fOUT = 550 MHz Temp Test Level Min Typ 1200 TBD TBD TBD TBD 80 77 63 55 85 84 74 65 -165 -164 -158 -155 Max Min AD9735 Typ 1200 TBD TBD TBD TBD Max Min AD9734 Typ 1200 TBD TBD TBD TBD Max Unit MSPS ns ns ns pA/rtHz dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBm/Hz dBm/Hz Table 3: AC Specifications Rev. PrC | Page 5 of 8 AD9736/AD9735/AD9734 EXPLANATION OF TEST LEVELS TEST LEVEL I II III IV V VI 100% production tested. Preliminary Technical Data 100% production tested at +25C and guaranteed by design and characterization at specified temperatures. Sample Tested Only Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at +25C and guaranteed by design and characterization for industrial temperature range. Rev. PrC | Page 6 of 8 Preliminary Technical Data 1 0.8 0.6 0.4 Error - LSB 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 2048 4096 6144 8192 Code 10240 12288 14336 16384 AD9736/AD9735/AD9734 TPC1. AD9736, Typical INL 0.5 0.3 0.1 Error - LSB -0.1 -0.3 -0.5 -0.7 0 2048 4096 6144 8192 Code 10240 12288 14336 16384 TPC2. AD9736, Typical DNL 3rd Order IMD With Respect to Fout (20mA FS) 800MSPS 90 85 80 IMD - [dBc] 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 550 600 Fout - [MHz] 1GSPS 1.2GSPS TPC3. AD9736, 3rd Order IMD vs. Fout and Sample Rate Rev. PrC | Page 7 of 8 AD9736/AD9735/AD9734 NSD Comparison With 1-Tone and 8-Tones at 1.2GSPS 1 Tone -150 -152 -154 -156 NSD - dBm/Hz 8 Tones Preliminary Technical Data -160 -162 -164 -166 -168 -170 0 100 200 300 400 500 600 700 Fout - Mhz TPC4. AD9736, Noise Spectral Density vs Fout at 1.2GSPS In- Band SFDR With Respect to Fout (20mA FS) 800MSPS 90 85 80 SFDR - [dBc] 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 550 600 Fout - [MHz] 1GSPS 1.2GSPS TPC5. AD9736, In Band SFDR vs Fout Rev. PrC | Page 8 of 8 PR04862-0-4/04(PrC) -158 |
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