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| OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. SN54/74LS273 * * * * 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q7 20 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11 OCTAL D FLIP-FLOP WITH CLEAR LOW POWER SCHOTTKY 20 1 J SUFFIX CERAMIC CASE 732-03 1 MR PIN NAMES 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND 20 1 N SUFFIX PLASTIC CASE 738-03 LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. CP D0 - D7 MR Q0 - Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 20 1 DW SUFFIX SOIC CASE 751D-03 NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC TRUTH TABLE MR L H H CP X Dx X H L Qx L H L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM 11 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q 1 MR VCC = PIN 20 GND = PIN 10 = PIN NUMBERS Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 FAST AND LS TTL DATA 5-1 SN54/74LS273 FUNCTIONAL DESCRIPTION The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 27 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl fMAX tPHL tPLH tPHL Parameter P Maximum Input Clock Frequency Propagation Delay, MR to Q Output Propagation Delay, Clock to Output Min 30 Typ 40 18 17 18 27 27 27 Max Unit Ui MHz ns ns Test C di i T Conditions Figure 1 Figure 2 Figure 1 FAST AND LS TTL DATA 5-2 SN54/74LS273 AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tw ts th trec Parameter P Pulse Width, Clock or Clear Data Setup Time Hold Time Recovery Time Min 20 20 5.0 25 Typ Max Unit Ui ns ns ns ns Test C di i T Conditions Figure 1 Figure 1 Figure 1 Figure 2 AC WAVEFORMS 1/f max tW CP 1.3 V ts(H) D * 1.3 V tPLH Qn 1.3 V tPHL *The shaded areas indicate when the input is permitted to *change for predictable output performance. MR 1.3 V th(L) 1.3 V 1.3 V tPHL 1.3 V tPLH Qn CP Qn tPLH tW 1.3 V trec 1.3 V tPHL 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V th(H) 1.3 V ts(L) Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time DEFINITION OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. FAST AND LS TTL DATA 5-3 |
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