View TUA6012_288303.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Components for Entertainment Electronics
2 Band TV Tuner TUA 6012, TUA 6014 Mixer-Oscillator-PLL
Data Sheet 1998-09-01
Edition 1998-09-01 This edition was realized using the software system FrameMaker(R) Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
TUA 6012, TUA 6014 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 5 6 12 20 24 30 Current Version: 1998-09-01 04.98 Subjects (major changes since last revision) Editorial Update
Feature list updated Application description modified I2C-Bus Interface description modified Max. value of parameter IPOH changed Test circuit modified Limit values for channel 6 beat and channel A-5 beat added
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA=25C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1998-09-01 Published by Siemens AG, Semiconductor Group Copyright (c) Siemens AG 1998. All rights reserved. Terms of delivery and right to change design reserved.
TUA 6012 TUA 6014
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 3 3.1 3.2 3.3 4 4.1 4.2 4.3 5 5.1 5.2 6 6.1 6.2 6.3 7 Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixer-Oscillator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Allocation Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UHF/VHF Bandswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Divider Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Converter Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC and RF Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement of Crystal Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . Equivalent I/O-Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 12 13 14 14 15 15 15 15 16 17 17 18 19 24 24 25 26
Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application Circuit 1, PAL (evaluation board) . . . . . . . . . . . . . . . . . . . . . . . . 27 Application Circuit 2, NTSC (Evaluation Board) . . . . . . . . . . . . . . . . . . . . . . 28 Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Admittance VHF Mixer Input Y0 = 20 ms (symmetrical and single ended) . . Input Impedance UHF Mixer Input Z0 = 50 (symmetrical) . . . . . . . . . . . . Output Admittance IF Output Y0 = 20 ms (symmetrical) . . . . . . . . . . . . . . . 29 29 30 30
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Semiconductor Group
4
1998-09-01
2 Band TV Tuner Mixer-Oscillator-PLL
TUA 6012 TUA 6014
BIPOLAR 1 1.1 Overview Features
General * Suitable for NTSC and PAL tuners * Full ESD protection Mixer/Oscillator * * * * High impedance mixer input for VHF Low impedance mixer input for UHF 4 pin oscillator for VHF 4 pin oscillator for UHF PLL * PLL with short lock-in time; no asynchronous divider stage * High voltage VCO tuning output * Fast I2C Bus * 4 NPN bandswitch buffers * Internal VHF/UHF switch * Lock-in flag * Power-down reset * Programmable reference divider ratio (64, 80, 128) * Programmable charge pump current P-TSSOP-28-1
Type TUA 6012XS TUA 6014XS TUA 6014-K TUA 6014-S
Semiconductor Group
Ordering Code Q67006-A5234-A701 Q67036-A1001-A701 Q67036-A1006-A702 Q67036-A1020-A701
5
Package P-TSSOP-28-1 P-TSSOP-28-1 P-TSSOP-28-1 P-TSSOP-28-1
1998-09-01
TUA 6012 TUA 6014
1.2
Functional Description
The TUA6012, TUA6014 devices combine a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV tuners. The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 900 MHz in increments of 50 kHz, 62.5 kHz or 31.25 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The device has four output ports, two of them (P0 and P1) can also be used as TTL input ports. A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C Bus. The mixer-oscillator block includes two balanced mixers (double balanced mixer with high-impedance input for VHF low, VHF high and low-impedance input for UHF), two frequency and amplitude-stable balanced oscillators for VHF low, VHF high and UHF, a low-noise reference voltage source and a band switch. 1.3 Application
The ICs are suitable for PAL and NTSC tuners in TV- and VCR-sets or cable set-top receivers for analog TV and Digital Video Broadcasting.
Semiconductor Group
6
1998-09-01
TUA 6012 TUA 6014
1.4
Pin Configuration
MIXU MIXU MIXV MIXV V VCC IFout IFout GND D SDA SCL CAS ADC P3 Q
1 2 3 4 5 6 7 TUA 6012XS 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
OU-B2 OU-C1 OU-C2 OU-B1 OV-B2 OV-C1 OV-C2 OV-B1 GND A TUNE CHGPMP P0/I0 P1/I1 P2
UEP10669
OU-B2 OU-C1 OU-C2 OU-B1 OV-B2 OV-C1 OV-C2 OV-B1 GND A TUNE CHGPMP P0/I0 P1/I1 P2
28 1 27 2 26 3 25 4 24 5 23 6 TUA 6014XS 22 7 TUA 6014-K 21 8 TUA 6014-S 20 9 19 10 18 11 17 12 16 13 15 14
MIXU MIXU MIXV MIXV V VCC IFout IFout GND D SDA SCL CAS ADC P3 Q
UEP10670
Figure 1
Semiconductor Group 7 1998-09-01
TUA 6012 TUA 6014
1.5
Pin Definitions and Functions Function
Pin No. Symbol TUA 6014 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 TUA 6012 28 OU-B2 27 OU-C1 26 OU-C2 25 OU-B1 24 OV-B2 23 OV-C1 22 OV-C2 21 OV-B1 20 GNDA 19 TUNE 17 P0/I0 16 P1/I1 15 P2 14 Q 13 P3 12 ADC 11 CAS 10 SCL 9 8 SDA GNDD
UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B1 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C2 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C1 UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B2 VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B1 VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C2 VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C1 VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B2 Analog Ground VCO tuning voltage output Port output/TTL input Port output/TTL input Port output 4 MHz low-impedance crystal oscillator input Port output ADC input Chip address select Clock input for the I2C Bus Data input/output for the I2C Bus Digital Ground
8 1998-09-01
18 CHGPMP Charge pump output/loop filter
Semiconductor Group
TUA 6012 TUA 6014
1.5
Pin Definitions and Functions (cont'd) Function
Pin No. Symbol TUA 6014 22 23 24 25 26 27 28 TUA 6012 7 6 5 4 3 2 1 IFout IFout
Inverse open collector mixer output, high-impedance, symmetrical to IFout Open collector mixer output, high-impedance, symmetrical to IFout Positive supply voltage VHF low or VHF high mixer input, high-impedance, symmetrical to MIXV VHF low or VHF high mixer input, high-impedance, symmetrical to MIXV UHF mixer input, low-impedance, symmetrical to MIXU UHF mixer input, low-impedance, symmetrical to MIXU
VVCC
MIXV MIXV MIXU MIXU
Semiconductor Group
9
1998-09-01
TUA 6012 TUA 6014
1.6
Block Diagram
MIXU MIXU MIXV MIXV V VCC IFout 28 (1) 27 (2) 26 (3) 25 (4) 24 (5) 23 (6)
IFout GND D SDA SCL CAS ADC P3 Q 22 (7) 21 (8) 20 (9) 19 (10) 18 (11) 17 (12) 16 (13) 15 (14)
2 C-Bus Interface
Mixer UHF Mixer VHF Progr. Divider Isolation Amplifier Isolation Amplifier
ADC
Crystal Oscillator
Ref.Divider
Oscillator UHF
Oscillator VHF
PhaseDet. & ChgPmp
/O-Ports
1 (28) 2 (27) 3 (26) 4 (25) 5 (24) 6 (23) 7 (22) 8 (21) 9 (20) 10 (19) 11 (18) 12 (17) 13 (16) 14 (15)
OU-B2 OU-C1 OU-C2 OU-B1 OV-B2 OV-C1 OV-C2 OV-B1 GND A TUNE CHGPMP P0/I0 P1/I1 P2
UEB10671
The pin numbers given in parenthesis refer to the TUA 6012XS.
Figure 2
Semiconductor Group 10 1998-09-01
TUA 6012 TUA 6014
2 2.1
Circuit Description Mixer-Oscillator Block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for VHF low and/or VHF high band and UHF, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switching in the tuner front-end is done by using two, three or four port outputs. In the selected band the signal passes a tuner input stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of VHF low/VHF high a high-impedance input and in case of UHF a lowimpedance input. The VHF low/VHF high input can be used unsymmetrically by capacitively grounding one of the input pins. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency and is available at the balanced high-impedance output pair (IFout/IFout). 2.2 PLL Block
The mixer-oscillator signal VCO/VCO is internally DC-coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency/phase detector to a reference frequency fref = 4 MHz / reference divider ratio (fref = 31.25 kHz, 50 kHz or 62.5 kHz). This frequency is derived from a unbalanced, lowimpedance 4 MHz crystal oscillator (pin Q) divided by reference divider ratio (programmable reference divider ratio = 128, 80 or 64). The phase detector has two outputs, UP and DOWN that drive two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of selfdischarge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments. If the VCO is not working the PLL locks to a tuning voltage of 33 V. By means of control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example.
Semiconductor Group
11
1998-09-01
TUA 6012 TUA 6014
The software-switched ports P0, P1, P2 and P3 are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / reference divider ratio) and Cy (divided input signal) to P0 and P1 respectively. P0, P1 are bidirectional. The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f = IP (KVCO / fQ) (C1 + C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see "Application Circuits" on page 27). As the charge pump pulses at 62.5 kHz (= fref), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains lock. 2.3
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C Bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C Bus. The data from the processor pass through an I2C-Bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table "Bit Allocation" (see "Bit Allocation Read/Write" on page 13) should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In
Semiconductor Group 12 1998-09-01
TUA 6012 TUA 6014
each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag. Four different chip addresses can be set by appropriate DC level at pin CAS (see "Address Selection" on page 15). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and if VVCC falls below 3.2 V. It will be reset at the end of a READ operation. 2.3.1 Bit Allocation Read/Write Byte Write Data Address byte Progr. divider byte 1 Progr. divider byte 2 Control byte 1 Control byte 2 Read Data Address byte Status byte 1 1 0 x 0 I1 0 I0 MA1 MA0 1 A2 A1 A0 A A POR FL 1 0 n7 1 x 1 n14 n6 5I x 0 n13 n5 T1 x 0 n12 n4 T0 x 0 n11 n3 1 P3 MA1 MA0 0 n10 n2 n9 n1 n8 n0 A A A A A MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Ack Remarks
RSA RSB OS P2 P1 P0
Semiconductor Group
13
1998-09-01
TUA 6012 TUA 6014
2.3.2 Description of Symbols Symbol MA0, MA1 n14 to n0 5I Description Address selection bits (see "Address Selection" on page 15) Programmable divider bits: N = 214 * n14 + 213 * n13 + ... + 23 * n3 + 22 * n2 + 21 * n1 + n0 Charge pump current: Bit = 0 : Charge pump current = 50 A Bit = 1 : Charge pump current = 220 A Test bits (see "Test Modes" on page 15) Reference divider bits (see "Reference Divider Ratio" on page 15) Tuning amplifier control bit: Bit = 0 : Enable VTUNE Bit = 1 : Disable VTUNE
T1, T0 RSA, RSB OS
PO, P1, P2, P3 NPN ports control bits Bit = 0 : NPN open-collector output is inactive, TTL inputs at P0, P1 Bit = 1 : NPN open-collector output is active UHF/VHF bandswitch (see "UHF/VHF Bandswitch" on page 14) A0, A1, A2 I0, I1 FL POR x ADC bits (see "A/D Converter Levels" on page 15) Input data from P0/I0, P1/I1 PLL lock flag Bit = 1 : Loop is locked Power-on reset flag Flag is set at power-on and reset at the end of READ operation don`t care
2.3.3 UHF/VHF Bandswitch IC is in UHF Mode P0 TUA 6012XS TUA 6014XS TUA 6014-K TUA 6014-S x x x x P1 1 1 x x Ports Pn P2 x x 1 x P3 x x x 1
Semiconductor Group
14
1998-09-01
TUA 6012 TUA 6014
2.3.4 Address Selection Voltage at CAS (0...0.1) * VVCC Open circuit (0.4...0.6) * VVCC (0.9...1) * VVCC 2.3.5 Test Modes Test Mode Normal operation Charge pump output, CHGPMP is in high-impedance state P1 = Cy output, P0 = fref output TTL-inputs I1/I0 are Cy / fref inputs of phase detector 2.3.6 Reference Divider Ratio Reference Divider Ratio 80 128 64 2.3.7 A/D Converter Levels Voltage at ADC (0...0.15) * VVCC (0.15...0.3) * VVCC (0.3...0.45) * VVCC (0.45...0.6) * VVCC (0.6...1) * VVCC A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 RSA x 0 1 RSB 0 1 1 T1 0 0 1 1 T0 0 1 0 1 MA1 0 0 1 1 MA0 0 1 0 1
Semiconductor Group
15
1998-09-01
TUA 6012 TUA 6014
2.3.8 I2C-Bus Timing Diagram
Addressing
Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte
SDA SCL
MA1 MA0 R/W
Telegram examples: Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop
Abbreviations: Start = Start Condition Addr = Address Byte DR1 = Prog. Divider Byte 1 DR2 = Prog. Divider Byte 2 CW1 = Control Byte 1 CW2 = Control Byte 2 Stop = Stop Condition
UED10672
Figure 3
Semiconductor Group 16 1998-09-01
TUA 6012 TUA 6014
3 3.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. 5.5 125 - 40 125 125 V C C K/W - 0.3 Unit Test Conditions
Parameter 1) Supply voltage Junction temperature Storage temperature Thermal resistance (junction to ambient) PLL CHGPMP
VVCC TJ TStg RthSA
VCHGPMP ICHGPMP VQ Crystal oscillator pins Q IQ VSDA Bus input/output SDA ISDA(L) Bus output current SDA VSCL Bus input SCL Chip address switch CAS VCAS VTUNE VCO tuning output
(loop filter) Port outputs P0...P3 Total port output current Mixer-Oscillator Mix inputs VHF/HYPER Mix inputs UHF VCO base voltage VCO collector voltage IF output
- 0.3
3 1
V mA V mA V mA V V V V mA mA V V mA V V V V Open collector
VVCC
-5 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -1
VVCC
5
VVCC VVCC
35
VP IP(L)
IP(L)
VVCC
15 20
tmax = 0.1 s at 5.5 V tmax = 0.1 s at 5.5 V
VMIXV VMIXU IMIXU VB VC VIFout VIFout
- 0.3 -5 - 0.3
3 2 6 3
VVCC
6 6
Semiconductor Group
17
1998-09-01
TUA 6012 TUA 6014
3.1
Absolute Maximum Ratings (cont'd) Symbol Limit Values min. max. 1 kV Unit Test Conditions
Parameter 1) ESD-Protection 2) All pins
1)
VESD
All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin. According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
2)
Ambient Temperature under bias: TA = - 20 C to + .....
Note: The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result.
3.2 Operating Range Symbol Limit Values min. Supply voltage Mixer output voltage Programmable divider factor VHF mixer input frequency range UHF mixer input frequency range VHF oscillator frequency range UHF oscillator frequency range Ambient temperature max. 5.5 5.5 32767 500 900 560 950 85 MHz MHz MHz MHz C V V Open collector 4.5 4.5 256 40 350 75 380 - 20 Unit Test Conditions
Parameter
VVCC VIFout VIFout
N
fMIXV fMIXU fOV fOU Tamb
Note: Within the operational range the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed.
Semiconductor Group
18
1998-09-01
TUA 6012 TUA 6014
3.3
AC/DC Characteristics Symbol Limit Values min. typ. max. Unit Test Conditions
Parameter Digital Unit PLL
Crystal Oscillator Connection Q Crystal frequency Crystal resistance Oscillation frequency Input impedance HIGH output current LOW output current Tristate current Output voltage HIGH output current LOW output voltage
fQ RQ fQ ZQ ICPH ICPL ICPZ VCP ITH VTL
3.2 10
4.0
4.8 100
4.00025
MHz Series resonance Series resonance MHz fQ = 4 MHz
3.99975 4.000
- 500 90 22 1.0
- 700
- 900
fQ = 4 MHz
5I = 1, VCP = 2 V 5I = 0, VCP = 2 V T0 = 1, VCP = 2 V Locked
Charge Pump Output CHGPMP 220 300 A 50 1 2.5 10 0.5 75 A nA V A V
Drive Output TUNE (open collector)
VTH = 33 V, OS = 1 ITL = 1.0 mA, T0 = 1
I2C-Bus
Bus Inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current HIGH output current LOW output voltage Edge Speed SCL, SDA Rise time Fall time Clock Timing SCL Frequency
VIH VIL IIH IIL IOH VOL tr tf fSCL
3 0 - 10
5.5 1.5 10
V V A A
VIH = VS VIL = 0 V VOH = 5.5 V IOL = 3 mA
Bus Output SDA (open collector) 10 0.4 300 300 0 400 A V ns ns kHz
Semiconductor Group
19
1998-09-01
TUA 6012 TUA 6014
3.3
AC/DC Characteristics (cont'd) Symbol Limit Values min. typ. max. s s s s s s s s 200 0 50 400 mV ns pF 0.6 1.3 0.6 0.6 0.6 1.3 0.1 0 Unit Test Conditions
Parameter HIGH pulse width LOW pulse width Start Condition Set-up time Hold time Stop Condition Setup time Bus free Data Transfer Setup time
tH tL tsusta thsta tsusto tbuf
tsudat thdat Hold time Input hysteresis SCL, SDA Vhys tsp Pulse width of spikes
which are suppressed Capacitive load for each bus line HIGH output current LOW output voltage TTL Port Inputs P0, P1 HIGH input voltage LOW input voltage HIGH input current LOW input current ADC Port Input HIGH input current LOW input current Power on Reset POR = 1
CL
Port Outputs P0, P1, P2, P3 (open collector)
IPOH VPOL VPIH VPIL IPIH IPIL IADCH IADCL VVCC
2.7
1 0.5
A V V
VPOH = 5 V IPOL = 15 mA
0.8 10 - 10 10 - 10 2.6 3.2 3.6
V A A A A V
VPIH = 5.5 V VPIL = 0 V
Semiconductor Group
20
1998-09-01
TUA 6012 TUA 6014
3.3
AC/DC Characteristics (cont'd) Symbol Limit Values min. typ. max. 50 - 50 A A Unit Test Conditions
Parameter
Address Selection Input CAS HIGH input current LOW input current Analog Unit Mixer-Oscillator Mixer current Mixer output impedance
ICASH ICASL
VCASH = 5 V VCASL = 0 V
IIF-V/IF-U RIFout, RIFout
4 13
6 20
8 27
mA k Parallel equivalent circuit, fIF = 38.9 MHz (see Figure 11) Parallel equivalent circuit, fIF = 38.9 MHz (see Figure 11)
CIFout, CIFout
0.35
0.5
0.7
pF
VHF Low and VHF High Band Section Current consumption Mixer gain
IVCC GMIXV
28 1
38 4
48 7
mA dB
fRF = 43.25 to 463.25 MHz, fIF =
33.4 to 58.75 MHz
Mixer noise figure Mixer input impedance
FMIXV RMIXV
1
5 2
8 3
dB k
fRF = 43.25 to
463.25 MHz Parallel equivalent circuit, fMIXV = 300 MHz (see Figure 9) Parallel equivalent circuit, fMIXV = 300 MHz (see Figure 9)
CMIXV
1
3
pF
Oscillator drift, PLL unlocked
fOscV fOscV fOscV
400 500 100
kHz kHz kHz
VS = 5 V 10%
T = 25 C
t = 5 s up to 15 min
after switching on
Semiconductor Group
21
1998-09-01
TUA 6012 TUA 6014
3.3
AC/DC Characteristics (cont'd) Symbol Limit Values min. typ. 108 108 max. dBV f = 10 kHz fRF = 48.25 MHz dBV f = 10 kHz fRF = 399.25 MHz dBc 100 100 - 50 Unit Test Conditions
Parameter Oscillator pulling, PLL unlocked
VMIXV VMIXV
N + 5 pulling, PLL unlocked
VMIXV
fRF = 48.25 MHz, fRF1 = 48.25 MHz, PRF = PRF1 =
80 dBV
VMIXV
- 50
dBc
fRF = 399.25 MHz, fRF1 = 437.25 MHz, PRF = PRF1 =
80 dBV
Oscillator phase noise UHF Section Current consumption Mixer gain
L(fM)VHF - 80
- 86
dBc/ fM = 10 kHz, Hz application circuit 1 52 17 mA dB
IVCC GMIXU
30 11
41 14
fRF = 367.25 to 863.25 MHz, fIF =
33.4 to 58.75 MHz
Mixer noise figure
FMIXU FMIXU
6 7 14 20
9 10 26
dB dB
fRF = 367.25 to
615.25 MHz
fRF = 623.25 to
863.25 MHz Serial equivalent circuit, fMIXU = 600 MHz (see Figure 10) Serial equivalent circuit, fMIXU = 600 MHz (see Figure 10)
Mixer input impedance
RMIXU
LMIXU
3
6
9
nH
Semiconductor Group
22
1998-09-01
TUA 6012 TUA 6014
3.3
AC/DC Characteristics (cont'd) Symbol fOscU fOscU fOscU Limit Values min. typ. max. 400 800 100 100 100 - 50 108 108 kHz kHz kHz Unit Test Conditions
Parameter Oscillator drift, PLL unlocked
VS = 5 V 10%
T = 25 C
t = 5 s up to 15 min
after switching on
Oscillator pulling, PLL unlocked
VMIXU VMIXU
dBV f = 10 kHz fRF = 375.25 MHz dBV f = 10 kHz fRF = 847.25 MHz dBc
N + 5 pulling, PLL unlocked
VMIXU
fRF = 471.25 MHz, fRF1 = 510.25 MHz, PRF = PRF1 =
80 dBV
VMIXU
- 50
dBc
fRF = 847.25 MHz, fRF1 = 886.25 MHz, PRF = PRF1 =
80 dBV
Oscillator phase noise Rejection at the IF Output Channel 6 beat Channel A-5 beat
1) 2)
L(fM)UHF - 80
- 86
dBc/ fM = 10 kHz, Hz application circuit 1 dBc dBc
INTCH6
60
66 69
VRFpix = VRFsnd =
80 dBV 1)
INTCHA-5 63
VRFpix = 80 dBV 2)
Channel 6 beat is the interfering product of fRFpix, fRFsnd - fOSC of channel 6 at 42 MHz. Channel A-5 beat is the interfering product of fRFpix + fRFsnd - fOSC of channel A-5, fBEAT = 45.5 MHz. The possible mechanisms are: fOSC - 2 fIF or 2 fRFpix - fOSC . For the measurement VRF = 80 dBV.
*
*
Supply Voltage Ambient Temperature
VVCC = 5 V Tamb = 25 C
Semiconductor Group
23
1998-09-01
TUA 6012 TUA 6014
4 4.1
Test Circuit DC and RF Parameter Measurement
R Gen = 50
UHF VHF
R Load = 50 V VCC
IFout
SDA SCL CAS ADC
P3
1:1
1:1 2)
1)
4 MHz 22 pF 22 pF 1 nF 25 24 23 10 47 nF 100 pF 18 pF
22 pF
22 pF 50
2.2 pF 28 27
1 nF 26
22
21
20
19
18
17
16
15
TUA 6014XS, TUA 6014-K, TUA 6014-S
1
2
3
4
5
6
7
8
9
10
22 nF
11
12
13
14
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.2 pF 2.2 pF 2.2 pF 2.2 pF
P0 / I0 P1 / I1 P2 22 k
3.9 pF 4.7 pF
100 pF 100 pF BB 639C
4.7 nF
BB 639C
470 pF
33 k
33 k
1 k
33 k 4.7 nF
22 k
22 k
+33 V
1 nF
1) 2)
UES10676
Not for noise measurement 1:2 transformer for noise measurement
Note: Circuitry is also valid for TUA 6012XS (circuit has to be flipped)
Figure 4
Semiconductor Group 24 1998-09-01
TUA 6012 TUA 6014
4.2
Measurement of Crystal Oscillator Frequency
V VCC
5V
Test mode:
T1 = HIGH T2 = LOW
Q 18 pF 4 MHz
VCC
P0
5 k
TUA 6012XS TUA 6014XS TUA 6014-K TUA 6014-S
f REF
5 k
Counter
f Q = f REF * Reference Divider Ratio f VCO = f CY * N N: divider ratio
P1
f CY
Counter
GND D
UES10677
Figure 5
Semiconductor Group 25 1998-09-01
TUA 6012 TUA 6014
4.3
Equivalent I/O-Schematic
1 (28) 2 (27) 3 (26) 4 (25) 5 (24) 6 (23) 7 (22) 8 (21) 9 (20) 10 (19) 11 (18) 12 (17) 13 (16) 14 (15)
28 (1) 27 (2) 26 (3) 25 (4) 24 (5) 23 (6) 22 (7) 21 (8) 20 (9) 19 (10) 18 (11) 17 (12) 16 (13) 15 (14)
The pin numbers in the parenthesis refer to the TUA 6012XS
UES10678
Figure 6
Semiconductor Group 26 1998-09-01
TUA 6012 TUA 6014
5 5.1
Application Circuits Application Circuit 1, PAL (evaluation board)
R Gen = 75
UHF VHF 47 pF
1:1
1)
R Load = 75 V VCC
IFout 12 pF 27 pF
SDA SCL CAS ADC
P3
220 220 4 MHz 100 pF 100 pF 4.7 nF 4.7 nF
1:2
22 pF
2)
L5
L6
4.7 nF
22 pF
18 pF
2.2 pF 1 nF 28 27 26 1 nF 25 24 23
47
22
21
20
19
18
17
16
15
TUA 6014XS, TUA 6014-K, TUA 6014-S
1
2
3
4
5
6
7
8
9
10
22 nF
11
12
13
14
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.7 pF 2.2 pF 2.2 pF 2.7 pF
P0 / I0 P1 / I1 P2 22 k 1 k 220
L3 L1
4.7 pF 4.7 pF 82 pF
L4
2.2 pF 100 pF
3.3 k 4.7 nF
BA 592 2.7 k 1 k 100 k 33 k 4.7 nF BB 639C 2.2 k 2.2 k +33 V 1 nF 4.7 nF 4.7 nF
1 F
BB 639C 470 pF L2 4.7 k 4.7 k
4.7 nF
1)
TOKO B4F Type 617DB-1023 TOKO B4F Type 617PT-1026
RF - Bands: 43.25 to 126.25 MHz 133.25 to 423.25 MHz 423.25 to 863.25 MHz
2)
L1: L2: L3: L4:
2 turns, 0.5 mm, 2.5 mm 4 turns, 0.5 mm, 2.5 mm 3 turns, 0.5 mm, 3 mm 10 turns, 0.5 mm, 3 mm
L5: 16 turns, 0.3 mm, 4 mm L6: 16 turns, 0.3 mm, 4 mm
Note: Circuitry is also valid for TUA 6012XS (circuit has to be flipped)
UES10679
Figure 7
Semiconductor Group 27 1998-09-01
TUA 6012 TUA 6014
5.2
Application Circuit 2, NTSC (Evaluation Board)
R Gen = 75
UHF VHF 18 pF 27 pF 1:1 1)
22 pF 22 pF
R Load = 75 V VCC
IFout
SDA SCL CAS ADC
P3
220 220 4 MHz 100 pF 100 pF 4.7 nF 4.7 nF
27 pF
1:2 2)
L5
L6
4.7 nF
18 pF
2.2 pF 1 nF 28 27 26 1 nF 25 24 23
47
22
21
20
19
18
17
16
15
TUA 6014XS, TUA 6014-K, TUA 6014-S
1
2
3
4
5
6
7
8
9
10
22 nF
11
12
13
14
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.7 pF 2.2 pF 2.2 pF 2.7 pF
P0 / I0 P1 / I1 P2 22 k 1 k 220
L3 L1
4.7 pF 4.7 pF 82 pF
L4
2.2 pF 100 pF
3.3 k 4.7 nF
BA 592 2.7 k 1 k 100 k 33 k 4.7 nF BB 639C 2.2 k 2.2 k +33 V 4.7 nF 4.7 nF 4.7 nF
1 F
BB 639C 470 pF L2 4.7 k 4.7 k
4.7 nF
1)
TOKO B4F Type 617DB-1023 TOKO B4F Type 617PT-1026
RF - Bands: 55.25 to 127.25 MHz 133.25 to 361.25 MHz 367.25 to 801.25 MHz
2)
L1: L2: L3: L4:
2 turns, 0.5 mm, 2.5 mm 4 turns, 0.5 mm, 2.5 mm 3 turns, 0.5 mm, 3 mm 10 turns, 0.5 mm, 3 mm
L5: 15 turns, 0.3 mm, 4 mm L6: 15 turns, 0.3 mm, 4 mm
UES10680
Note: Circuitry is also valid for TUA 6012XS (circuit has to be flipped)
Figure 8
Semiconductor Group 28 1998-09-01
TUA 6012 TUA 6014
6 6.1
Electrical Diagrams Input Admittance VHF Mixer Input Y0 = 20 ms (symmetrical and single ended)
1.5 2 3 4 5 10 20 20 10 5 4 3
1 0.9 0.8 0.7
0.6
0.5 0.4 0.3 0.2 0.1
5
3
2
1
0.3 0.2
0.1
40 MHz R se 500 MHz
40 MHz R diff 500 MHz 0.2 0.3
0.4 2 1.5 0.7 1 0.9 0.8 0.6 0.5
UED10673
Figure 9
Semiconductor Group 29 1998-09-01
TUA 6012 TUA 6014
6.2
Input Impedance UHF Mixer Input Z0 = 50 (symmetrical)
0.6 0.7 0.8 0.9 1 1.5 2 3 900 MHz 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 2 0.7 0.8 0.9 1 1.5
UED10674 0.1 0.2 0.3
0.5 0.4 0.3
R diff 500 MHz 300 MHz
1 2 3 5
4 5 10 20 20 10 5 4 3
Figure 10 6.3 Output Admittance IF Output Y0 = 20 ms (symmetrical)
1.5 2 3 4 5 10 20 20 10 5 4 3 0.4 2 1.5 0.7 1 0.9 0.8 0.6 0.5
UED10675
1 0.9 0.8 0.7
0.6
0.5 0.4 0.3 0.2 0.1
5
3
2
1
0.3 0.2
0.1
30 MHz 60 MHz 0.1 0.2 0.3
Figure 11
Semiconductor Group 30 1998-09-01
TUA 6012 TUA 6014
7
Package Outlines P-TSSOP-28-1 (Plastic Thin Shrink Small Outline Package)
GPS05867
Figure 12
Semiconductor Group
31
1998-09-01

▲Up To Search▲

Price & Availability of TUA6012

	To Download TUA6012 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .