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LM2502 Mobile Pixel Link (MPL) Transceiver
ADVANCE INFORMATION
January 2004
LM2502 Mobile Pixel Link (MPL) Transceiver
General Description
The LM2502 device is a dual link Transceiver that adapts existing CPU / video busses to a low power current-mode serial MPL link. The Master Transceiver resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Transceiver located near the display module. Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted on the Master, the MD1/0 and MC signals are powered down to save current. The LM2502 implements the physical layer of the MPL Standard (MPL-0). The MPL logic layer is currently in definition.
Features
n n n n n n 320 Mbps Dual Link Raw Throughput MPL Physical Layer (MPL-0) Pin selectable Master / Slave mode Frequency Reference Transport Complete LVCMOS / MPL Translation CPU Interface Modes: -- 16-bit data path -- Intel or Motorola Interface Link power down mode reduces quiescent power under 10 A (actual TBD) Dual Display Support (CS1* & CS2*) Via-less MPL interconnect feature 3.0V Supply Voltage Interfaces to 1.7V to 3.3V Logic
n n n n n
System Benefits
n n n n n Small Interface Low Power Low EMI Frequency Reference Transport Intrinsic Level Translation
Typical Application Diagram
20093301
Ordering Information
NSID LM2502GR Package Type 49(40) lead FBGA style, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch Package ID GRA49A
(c) 2004 National Semiconductor Corporation
DS200933
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LM2502
Connection Diagram
20093319
TOP VIEW (not to scale)
TABLE 1. Ball Assignment Ball # A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 Master D0 D1 D2 VDDA INTR MD1 MC D3 D4 D5 VSSA M/S* Mode MD0 D6 D7 CS2* MF1 VDDIO VSSIO Slave D0 D1 D2 VDDA NC MD0 MC D3 D4 D5 VSSA M/S* Mode MD1 D6 D7 CS2* MF1 VDDIO VSSIO Ball # D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 Master VSScore VDDcore D8 D9 CS1* D10 D11 D12 VSSIO MF0 PD* D13 D14 D15 VDDIO A/D CLK Slave VSScore VDDcore D8 D9 CS1* D10 D11 D12 VSSIO MF0 PD* D13 D14 D15 VDDIO A/D CLK
PLLCON2 PLLCON2
PLLCON1 PLLCON1
PLLCON0 PLLCON0
Table is for REV B ES Silicon, see note.
Note: ES units REV A does not implement the swap function - A6 = MD1, B7 = MD0. ES units REV B implements the swap function - A6 = MD0, B7 = MD1.
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LM2502
Pin Descriptions
Pin Name No. of Pins 2 1 1 1 I/O, Type Description Master MPL Data Line Driver/Receiver MPL Clock Line Driver Master/Slave* High for Master Mode Power_Down* Input, H = Active L = Power Down Mode Multi-function Input Zero (0): If MODE = 0 (MOT mode) E input pin, data is latched on E High-to-Low transition or E may be static High and Data is latched on CS* Low-to-High edge If MODE = 1 (Intel mode) Read Enable input pin, active low. Read data is driven when both RD* and CS* are Low. Multi-function Input One (1): If Mode = 0 (MOT mode) Read/Write* pin, Read High, Write* Low If Mode = 1 (Intel mode) Write* enable input pin, active Low. Write data is latched on the Low-to-High transition of either WR* or CS* (which ever occurs first). ChipSelect1* - Input H = Ignored L = Active ChipSelect2* - Input H = Ignored L = Active Address/Data - Input H = Data L = Address (Command) Data Bus - Inputs/Outputs INTR is asserted when the read data is ready and de-asserted upon a second CPU Read cycle. Clock Input Slave MPL Data Receiver/Line Driver MPL Clock Receiver Master/Slave* Low for Slave Mode Power_Down* Output, H = Link Active L = Link in Power_Down Mode Multi-function Output Zero (0): If MODE = 0 (MOT mode) E output pin, static High. If MODE = 1 (Intel mode) Read Enable output pin, active Low.
MPL SERIAL BUS PINS MD[1:0] MC M/S* PD* IO, MPL IO, MPL I, LVCMOS IO, LVCMOS IO, LVCMOS
CONFIGURATION/PARALLEL BUS PINS
MF0 (E or RD*)
1
MF1 (R/W* or WR*)
1
IO, LVCMOS
Multi-function Output One (1): If Mode = 0 (MOT mode) Read/Write* pin, Read High, Write* Low If Mode = 1 (Intel mode) Write* enable output pin, active Low.
CS1*
1
IO, LVCMOS IO, LVCMOS IO, LVCMOS IO, LVCMOS O, LVCMOS IO, LVCMOS I, LVCMOS I, LVCMOS
ChipSelect1* - Output H = Ignored L = Active ChipSelect2* - Output H = Ignored L = Active Address/Data - Output H = Data L = Address (Command) Data Bus - Outputs/Inputs No Connect - leave open on board
CS2*
1
A/D (RS or A0) D[15:0] INTR
1
16 1
CLK
1
Clock Output (Frequency Reference) - no phase relationship to data - frequency reference only. Mode Input Pin High = Intel Mode, Low = MOT Mode Clock Divisor Configuration Input Pins
Mode
1
Mode Input Pin High = Intel Mode, Low = MOT Mode PLL Configuration Input Pins
PLL_CON [2:0]
3
3
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LM2502
Pin Descriptions
Pin Name No. of Pins 1 1 1 1 2 2
(Continued) I/O, Type Description Master Power Supply Pin for the MPL Interface. 2.9V to 3.3V Ground Pin for the MPL Interface, also known as MG (MPL Ground) Power Supply Pin for the digital core. 2.9V to 3.3V Ground Pin for the digital core. Power Supply Pin for the parallel interface. 1.7V to 3.3V Ground Pin for the parallel interface. Slave
POWER/GROUND PINS VDDA VSSA VDDcore VSScore VDDIO VSSIO Power Ground Power Ground Power Ground
Note: I = Input, O = Output, IO = Input/Output, VDDIO VDD (VDDA = VDDcore). Do not float input pins.
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LM2502
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDDA) Supply Voltage (VDD) Supply Voltage (VDDIO) LVCMOS Input/Output Voltage MPL Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 4 Seconds ESD Ratings: HBM, 1.5 k, 100pF 2 kV -0.3V to +TBDV -0.3V to +TBDV -0.3V to +TBDV -0.3V to (VDDIO +0.3V) TBD +150C -65C to +150C +260C
EIAJ, 0, 200 pF TBD Package Derate TBD Package above 25C
200V TBD W TBD mW/C
Maximum Package Power Dissipation Capacity at 25C
Recommended Operating Conditions
Min Typ Max Supply Voltage VDDA to VSSA VDDcore to VSScore VDDIO to VSSIO Clock Frequency Ambient Temperature 2.9 2.9 1.7 8 0 25 3.0 3.0 3.3 3.3 3.3 20 70 V V V MHz C Units
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol MPL IOH IOMS IOL IB VIH VIL IIH IIL VOH VOL IOS IOZ VCL ICC Logic High Current Mid Scale Current Logic Low Current Current Bias Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Low Level Output Voltage High Level Output Voltage Low Level Output Short-Circuit Current Output TRI-STATE Current Clamp Voltage Total Supply Current -- Enabled Master Slave ICCZ Supply Current -- Disable Power_Down Mode VDDIO VDD/VDDA VDDIO VDD/VDDA IOH = -2 mA IOL = 2 mA VOUT = 0V TBD -5 TBD TBD TBD TBD TBD TBD TBD 0.8 IB 2.8 IB 3.0 IB 2.0 IB 1.0 IB IB VDDIO +0.3 0.3 VDDIO 0 0 +1 +1 0.2 VDDIO TBD +5 -1.5 TBD TBD TBD TBD TBD 1.2 IB 3.3 IB A A A A Parameter Conditions Min Typ Max Units
LVCMOS (1.7V to 3.3V Operation) 0.7 VDDIO -0.3 -1 -1 0.8 VDDIO V V A A V V mA A V A mA A A A
SUPPLY CURRENT
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LM2502
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol tSET tHOLD tRISE tFALL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 SERIAL BUS TIMING tDVBC tDVAC tRVAC POWER UP TIMING t1 t2 t3 t4 t0 tPAZ PD* to MC L-H (Master) MC Pulse Width HIGH (Master) MC H-L to Idle State (Master) PD*-Out Delay (Slave) Master PLL Lock Time Disable Time to Power Down Clock Output Frequency Duty Cycle Transition Time CL = 7 pF 50 Figure 10 1 TBD ms Figure 9 Slave-to-Master Master-to-Slave TBD TBD TBD ns ns ns Parameter Set Up Time Hold Time Rise Time Fall Time Outputs, CL = 15 pF Figures 14, 15, 16, 17 Table 4. WRITE -- MOT 6800 P Interface Parameters, Table 5. READ -- 6800 P Interface Parameters, Table 6. READ -- 80xx P Interface Parameters, Table 7. READ -- Intel P Interface Parameters Inputs Conditions Min 5 5 Typ 2 2 4 4 TBD TBD Max Units ns ns ns ns PARALLEL BUS TIMING
MPL POWER OFF TIMING TBD s
SLAVE CLOCK OUTPUT F CLKDC tT MHz % ns
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LM2502
Input Timing Requirements
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol f tCP CLKDC tT Parameter Clock Frequency Clock Period Clock Duty Cycle Clock Transition Times (Rise or Fall, 10%-90%) 45 50 55 6 Conditions Min 8 Typ Max 20 Units MHz ns % ns MASTER R EFERENCE CLOCK (CLK)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VDDIO = 1.8V and VDD = VDDA = 3.0V and TA = 25C. Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise specified.
Timing Diagrams
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FIGURE 1. Serial Data Valid -- Master to Slave
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FIGURE 2. Serial Data Valid -- Slave to Master
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FIGURE 3. Slave Output Timing
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LM2502
Application Information
The LM2502 provides a swap function of MPL MD lines depending upon the state of the M/S* pin. This facilitates a straight through MPL interface design eliminating the needs for via and crossovers as shown on Figure 4. See also Connection Diagram and Table 1. Ball Assignment. Feature is supported on ES Rev B and Production Silicon.
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FIGURE 4. MPL Interface Layout
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FIGURE 5. LM2502 PWR (VDD) and GND (VSS) Balls
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LM2502
Functional Description
BUS OVERVIEW The LM2502 is a dual link Transceiver configurable part that supports a 16-bit CPU (68xx or 80xx) style interface. The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termination is provided internal to the MPL receiver. A maximum raw throughput of 320 Mbps is possible. When the protocol overhead is taken into account, a maximum data throughput of 256 Mbps is possible. The MPL interface is designed for use with common 50 lines using standard materials and connectors. Lines may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 0.1 meters.
SERIAL BUS TIMING Data valid is relative to both edges as shown in Figure 7. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, and Skew between data lines is TBD.
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FIGURE 7. Dual Link Timing (WRITE)
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FIGURE 8. Dual Link Timing (READ) SERIAL BUS PHASES There are four bus phases on the MPL serial bus. These are determined by the state of the MC and MD lines. The MPL bus phases are shown in Table 2. Link Phases.
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FIGURE 6. MPL Point-to-Point Bus
TABLE 2. Link Phases Name OFF (O) IDLE (I) Active (A) Data Out WRITE Data In READ LINK-UP (LU) Master MC State 0 A A A MDn State 0 L X X Phase Description Link is Off Data is Static (Low) Data Out (Write) -- includes command, Data Out Phases Data In (Read) -- includes command, TA', Data In, and TA" phases Master initiated Link-Up Pre-Phase A, I or LU A or LU LU, A, or I LU, A, or I Post-Phase LU A or O A, I, or O A, I, or O
H
-
O
A, I, or O
Notes on MC/MD Line State: 0 = no current (off) L = Logic Low -- The higher level of current on the MC and MD lines H = Logic High -- The lower level of current on the MC and MD lines X = Low or High A = Active Clock
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LM2502
Functional Description
SERIAL BUS START UP TIMING
(Continued)
In the Serial Bus OFF phase, Master transmitters for MD0, MD1 and MC are turned off such that zero current flows over the MPL lines. In addition, both the Master and the Slave are internally held in a low power state. When the Master's PD* input pin is de-asserted (driven High) the Master enables its PLL and waits for enough time to pass for its PLL to lock. After the Master's PLL is locked (t0 = 4,096 CLK Cycles), the Master will perform an MPL start up sequence. The MPL start up sequence gives the Slave an opportunity to optimize the current sources in its transceiver and to emerge from its low power state. The Master begins the sequence by driving the MC line logically Low for 11 CLK cycles (t1). During this part of the sequence the Slave's transceiver samples the MC current flow and adjusts itself to interpret that amount of current as a logical Low. Next the Master drives the MC line logically HIGH for 11 CLK cycles (t2). On the Low-to-High transition of the MC - point B - the Slave
latches the current source configuration. This optimized configuration is held as long as the MPL remains up. Next, the Master drives both the MC and the MD lines to a logical Low for another 11 CLK cycles (t3), after which it begins to toggle the MC line at a rate determined by its PLL Configuration pins. The Master will continue to toggle the MC line as long as its PD* pin remains de-asserted (High). At this point the MPL bus may remain in IDLE phase, enter the ACTIVE phase or return to the OFF phase. Data transmission is not gated by the Slave PD* output signal. Active data will occur at the Slave output latency delays (Master + line + Slave) after the data is applied to the Master input. Possible start points are shown by the "C" arrow in Figure 9. After seven subsequent MC cycles the Slave will start toggling its CLK pin at a rate configured by its CLK Divisor pins. The Slave then waits an additional 17 CLK cycles before de-asserting its PD* Output pin (t4). In the Figure 9 example, an IDLE bus phase is shown until point C, after which the bus is active and the High start bit on MD initiates the transfer of information.
20093305
FIGURE 9. Bus Power Up Timing OFF PHASE In the OFF phase, both Master and Slave MPL transmitters are turned off with zero current flowing on the MC and MD lines. Figure 10 shows the transition of the MPL bus into the OFF phase. If an MPL line is driven to a logical Low (high current) when the OFF phase is entered it may temporarily pass through as a logical High (low current) before reaching the zero line current state.
20093306
FIGURE 10. Bus Power Down Timing
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LM2502
Functional Description
(Continued)
The link may be powered down by asserting the Master's PD* input pin (Low). This causes the Master to immediately put the link to the OFF Phase and internally enter a low power state. When the Slave detects a lack of current flow on the MC it will immediately also enter a low power state and assert its PD* output pin (Low). To avoid loss of data the Master's PD* input should only be asserted after the MPL bus has been in the IDLE state for at least 5 MC clock cycles. This gives the Slave enough time to complete any write operations received from the MPL bus. CPU INTERFACE COMPATIBILITY The CPU Interface mode provides compatibility between a CPU Interface and a small form factor (SFF) Display or other fixed I/O port application. Two options are allowed: TABLE 3. Modes Mode 0 1 Description MOT 68xx Interface (E, R/W*), 16-bit support Intel 80xx Interface (WR*, RD*), 16-bit support
It is not required that both the Master and the Slave to be configured in the same mode. For example the Master may be configured as an 80xx interface while the Slave is configured for an 68xx interface. Control information is carried over both MD lines. MD0 carries the D0-7 data bits while MD1 the D8-15 data bits. See Figure 11. WRITE TRANSACTION The WRITE transaction consists of two MC edges of control information followed by 8 MC edges of write data. Since WRITE transactions transfer information on both edges of MC it takes 5 MC cycles to complete a write transaction. The MD0 line carries the Start bit (High), the A/D (Address/Data) bit and then the data payload of 8 bits (D0-7). The MD1 line carries the R/W* bit (Read/Write*), the CS1/2 bit and then the data payload of 8 bits (D8-15). The data payload is sent least significant bit (LSB) first. The CS1/2 bit denotes which Chipset pin was active. CS1/2 = HIGH designates that CS1* is active (Low). CS1/2 = LOW designates that CS2* is active (Low). CS1* and CS2* LOW is not allowed.
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FIGURE 11. Dual MD Link WRITE Transaction READ TRANSACTION The READ transaction is variable in length. It consists of four sections. In the first section the Master sends a READ_Command to the slave. This command is sent in a single MC cycle (2 edges) and uses a similar format to the 1st cycle of the WRITE transaction. The MD0 line carries the Start bit (High) and the A/D (Address/Data) bit. The MD1 line carries the R/W* bit (High for reads) and the CS1/2 bit. In the second section (TA') the MD lines are turned around, such that the Master becomes the receiver and Slave becomes the transmitter. The Slave must drive the MD lines low by the 14th clock edge. It may then idle the line at the Logic Low state or drive the line High to indicate that read data transmission is starting. This ensures that the MD lines are a stable LOW state and that the Low-to-High transition of the "Start" bit is seen by the Master.
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LM2502
Functional Description
(Continued)
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FIGURE 12. READ_Command and TA' The third section consists of the transfer of the read data from the Slave to the Master. Note that the READ_Data operates on single-edge clocking (Rising Edge ONLY). Therefore the back channel data signaling rate is 12 of the forward channel (Master-to-Slave direction). When the Slave is ready to transmit data back to the Master it drives the MD lines High to indicate start of read data, followed by 8 MC cycles of the actual read data payload. As in the WRITE command MD0 carries D0-7 and MD1 carries D8-5. The fourth and final section (TA") occurs after the read data has been transferred from the Slave to the Master. In the fourth section the MD lines are again turned around, such that the Master becomes the transmitter and the Slave becomes the receiver. The Slave drives the MD lines Low for 1 bit with and then turns off. The MD lines are off momentarily to avoid driver contention. The Master then drives the MD line Low for 1 bit time and then idles the bus until the next transaction is sent.
20093309
FIGURE 13. READ_Data and TA"
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LM2502
Functional Description
CPU MODE -- WRITE -- MOT68xx
(Continued)
20093310
FIGURE 14. WRITE -- MOT 6800 P Interface
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LM2502
Functional Description
No. T1 T2 T3 T4 T5 T6 T7 T8 T9 MasterIN MasterIN MasterIN Master Slave SlaveOUT SlaveOUT SlaveOUT SlaveOUT
(Continued)
TABLE 4. WRITE -- MOT 6800 P Interface Parameters Parameter Data Setup Time before ChipSelect* Low-High (or E High-Low) Data Hold after ChipSelect* Low-High (or E High-Low) ChipSelect* Recovery Time Master Latency Slave Latency Data Valid before ChipSelect* High-Low CS* Low Pulse Width Data Valid before ChipSelect* Low-High Data Valid after ChipSelect* Low-High Min TBD 0 Typ 3.6 TBD TBD 4 8 1 3 4 1 Max Units ns ns MC Cycles MC Cycles MC Cycles MC Cycles MC Cycles MC Cycles MC Cycles
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FIGURE 15. READ -- 6800 P Interface
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LM2502
Functional Description
No. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 MasterIN MasterIN Master Slave Slave Slave Slave Slave Slave Master Master MasterOUT MasterOUT MasterOUT MasterOUT MasterOUT Set Up Time Hold Time
(Continued)
TABLE 5. READ -- 6800 P Interface Parameters Parameter Min Typ 3.6 0 4 5 1 6 3.6 0 6 1 18.6 TBD 3.6 4 TBD 0 Max Units ns ns MC Cycles MC Cycles MC Cycles MC Cycles ns ns MC Cycles MC Cycles ns ns ns MC Cycles MC Cycles MC Cycles
Master Latency Slave Latency ChipSelect* Delay ChipSelect Low Pulse Width Data Set Up Time Data Hold Time Slave Read Latency INTR Delay Data Delay Data Valid after Strobe CS* or E active pulse width INTR De-assert Recovery Time INTR Response
For the MOT CPU 68xx mode, the Master accepts data on the CS* Low-to-High transition or the E High-to-Low transition, which ever come first. The Slave output only uses the CS* pin for data strobe/latch, as the E signal is held constantly High.
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LM2502
Functional Description
(Continued)
INTEL Mode (mode = 1)
20093312
FIGURE 16. WRITE -- 80xx P Interface TABLE 6. READ -- 80xx P Interface Parameters No. T1 T2 T3 T4 T5 T6 T7 T8 T9 MasterIN MasterIN MasterIN Master Slave SlaveOUT SlaveOUT SlaveOUT SlaveOUT Parameter Data Setup before ChipSelect* High Data Hold after ChipSelect* High ChipSelect* Recovery Time Master Latency Slave Latency Data Valid before ChipSelect* High-to-Low CS* Pulse Width Low Data Valid before ChipSelect* Low-to-High Data Valid after ChipSelect* Low-to-High 0 Min Typ 3.6 TBD TBD 4 8 1 3 4 1 Max Units ns ns ns MC Cycles MC Cycles MC Cycles MC Cycles MC Cycles MC Cycles
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LM2502
Functional Description
(Continued)
20093313
FIGURE 17. READ -- INTEL P Interface TABLE 7. READ -- Intel P Interface Parameters No. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 MasterIN MasterIN Master Slave Slave Slave Slave Slave Slave Master Master MasterOUT MasterOUT MasterOUT MasterOUT MasterOUT Set Up Time Hold Time Master Latency Slave Latency ChipSelect* Delay ChipSelect Low Pulse Width Data Set Up Time Data Hold Time Slave Read Latency INTR Delay Data Delay Data Valid after Strobe RD* active pulse width INTR De-assert Recovery Time INTR Response 0 Parameter Min Typ 3.6 0 4 5 1 6 3.6 0 6 1 18.6 TBD TBD 4 TBD Max Units ns ns MC Cycles MC Cycles MC Cycles MC Cycles ns ns MC Cycles MC Cycles ns ns MC Cycles MC Cycles MC Cycles MC Cycles
To account for the latency through the MPL link, a dual READ operation is required by the host. The first read returns invalid data (all Low). Once data has returned to the Master LM2502, the INTR signal is asserted to inform the host to initiate a second read operation. When the Master LM2502 sees the Read signal/CS* combination, it will de-assert the INTR signal and Valid data is presented.
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LM2502
Functional Description
(Continued)
20093314
FIGURE 18. Back-to-Back WRITE Operations -- 68xx Mode
20093315
FIGURE 19. Slave WRITE and Slave READ Operation
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LM2502
LM2502 Features and Operation
POWER DOWN/OFF A Master configured device may be powered by the PD* pin. A Low on this pin will power down the entire device and turn off the line current to MD0, MD1, and MC. The Slave device senses this MC state and also powers down. In this state the following outputs are driven to: Master: INTR = Low Slave: PD* = L, AD = DATAn = CLK = Low, CS1* = CS2* = MF0 = MF1 = High UN-USED/OPEN PINS Unused inputs must be tied to the proper input level -- do not float them. Unused outputs should be left open to minimize power dissipation. PHASE-LOCKED LOOP When the LM2502 is configured as a Master, a PLL is provided to generate the serial link clock. The Phase-locked loop system generates the serial data clock at several mul-
tiples of the input clock. The PLL operates with an input clock between 8 and 20MHz. See Table 8. PLL_CON Settings below, Multiplier/Divisor times CLK rate must also be less than 80 MHz. The 80 MHz limitation is based on the semiconductor process used on this implementation -- it is not an MPL limitation. Line rate should also be selected such that it is faster the input load rate when bursting data across the link. Otherwise 8/10 X Line rate must be greater than the input load rate to the Master. At the maximum raw data rate of 320 Mbps, the maximum information rate is 256 Mbps. Thus the parallel load rate at the Master input must not exceed 16 Mega Transfers per second sustained (of 16 data bits). The Master can accommodate up to four words at a higher rate due to internal FIFOs. Configuration pins (PLL_CON[2:0], and M/S*) are used to determine the mode of which the part is operating in. In the Slave configuration the PLL block is disabled. The Slave PLL_CON pins are required to set up the proper divisor for the CLK pin. Slave PLL_CON[2:0] pins do not need to be set the same as the Master, this allows for clock multiplication / division to be supported for the output clock reference signal.
TABLE 8. PLL_CON Settings PLLCON2 0 0 0 0 1 1 1 1 PLLCON1 0 0 1 1 0 0 1 1 PLLCON0 0 1 0 1 0 1 0 1 Multiplier/Divisor CLK X 2 CLK X 4 CLK X 6 CLK X 7 CLK X 8 CLK X 9 CLK X 10 CLK/2 Maximum CLK Input (MC % 80 MHz) 20 MHz 20 MHz 13.3 MHz 11.43 MHz 10 MHz 8.89 MHz 8 MHz (TEST MODE)
RESET The LM2502 has two reset domains: Master and Slave. The PD* pin resets the Master logic and the lack of current flow on the MC resets the Slave logic. There is no internal power-on reset circuit, thus it is necessary to power up the Master with PD* asserted. MASTER/SLAVE SELECTION The M/S* pin is used to configure the device as either a Master or Slave device. When the M/S* pin is a Logic High, the Master configuration is selected. The Driver block is
enabled for the MC line, and the MD lines. When the M/S* pin is a Logic Low, the Slave configuration is selected. The Receiver block is enabled for the MC line, and the MD lines.
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LM2502 Mobile Pixel Link (MPL) Transceiver
Physical Dimensions
inches (millimeters) unless otherwise noted
Note: ES units may be offered in a footprint compatible 49 Ball FBGA package.
Preliminary Drawing 49 Ball MICRO ARRAY, 0.5mm pitch Order Number LM2502GR NS Package Number GRA49A
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