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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
FEATURES
* 4 LVCMOS/LVTTL outputs, 7 typical output impedance * Single LVCMOS/LVTTL clock input * CLK accepts the following input levels: LVCMOS or LVTTL * Output frequency range: 15.625MHz to 62.5MHz * Input frequency range: 15.625MHz to 62.5MHz * VCO range: 250MHz to 500MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Fully integrated PLL * Cycle-to-cycle jitter: 50ps (typical) * Output skew: 40ps (typical) * Static Phase Offset: TBD * Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS86004 is a high performance 1:4 LVCMOS/ LVTTL Clock Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS86004 has a fully integrated PLL and can be configured as zero delay buffer and has an input and output frequency range of 15.625MHz to 62.5MHz. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider.
ICS
BLOCK DIAGRAM
PLL_SEL /8, /16 0
PIN ASSIGNMENT
Q0 Q1 GND Q0 F_SEL VDD CLK GND VDDA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO Q2 GND Q3 VDDO MR FB_IN PLL_SEL
Q1 CLK PLL 1 Q2
FB_IN
1:1
Q3
ICS86004
16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm package body G Package Top View
MR F_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 86004BG www.icst.com/products/hiperclocks.html REV. A OCTOBER 14, 2003
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
Type Description Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. Power supply ground. Pulldown Frequency range select input. LVCMOS/LVTTL interface levels. Core supply pin. Pulldown LVCMOS/LVTTL clock input. Analog supply pin. Selects between the PLL and reference clock as input to the dividers. Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Output supply pins.
TABLE 1. PIN DESCRIPTIONS
Number 1, 3, 13, 15 2, 7, 14 4 5 6 8 9 10 11 12, 16 Name Q1, Q0, Q3, Q2 GND F_SEL VDD CLK VDDA PLL_SEL FB_IN MR VDDO
Output Power Input Power Input Power Input Input Input Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDD, VDDA, VDDO = 3.465V VDD, VDDA = 3.465V, VDDO = 2.625V VDD, VDDA, VDDO = 2.625V ROUT 5 Test Conditions Minimum Typical 4 51 51 TBD TBD TBD 7 12 Maximum Units pF K K pF pF pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1
Input F_SEL 0 1 Input/Output Frequency Range (MHz) Minimum Maximum 31.25 15.625 62.5 31.25
TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0
Input F_SEL 0 1 Output Ref /8 Ref /16
86004BG
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2
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 85 15 5 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage FB_IN, MR, PLL_SEL, F_SEL CLK FB_IN, MR, PLL_SEL, F_SEL CLK CLK, MR, FB_IN, F_SEL PLL_SEL CLK, MR, FB_IN, F_SEL PLL_SEL Test Conditions Minimum Typical 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO = 3.465V VDDO = 2.625V -5 -150 2.6 1.8 0.5 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V V
VIL
Input Low Voltage
IIH
Input High Current
IIL VOH
Input Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1 VDDO = 3.465V or 2.625V VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section, Output Load Test Circuit diagrams.
86004BG
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3
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 TBD TBD TBD Maximum 3.465 3.465 2.625 Units V V V mA mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 TBD TBD TBD Maximum 2.625 2.625 2.625 Units V V V mA mA mA
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tpLH t(O) tsk(o) tjit(cc) tL tR / tF Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Static Phase Offset; NOTE 2, 4 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter; NOTE 4 PLL Lock Time Output Rise/Fall Time Test Conditions F_SEL = 0 F_SEL = 1 PLL_SEL = 0V, f 250MHz PLL_SEL = 3.3V PLL_SEL = 0V Minimum 31.25 15.625 TBD TBD 40 50 1 600 Typical Maximum 62.5 31.25 Units MHz MHz ns ps ps ps mS ps %
odc Output Duty Cycle 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
86004BG
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
Test Conditions F_SEL = 0 F_SEL = 1 PLL_SEL = 0V, f 250MHz PLL_SEL = 2.5V PLL_SEL = 0V Minimum 31.25 15.625 TBD TBD TBD TBD TBD TBD Typical Maximum 62.5 31.25 Units MHz MHz ns ps ps ps mS ps %
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tpLH t(O) tsk(o) tjit(cc) tL tR / tF Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Static Phase Offset; NOTE 2, 4 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise/Fall Time
odc Output Duty Cycle TBD All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tpLH t(O) tsk(o) tjit(cc) tL tR / tF Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Static Phase Offset; NOTE 2, 4 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise/Fall Time Test Conditions F_SEL = 0 F_SEL = 1 PLL_SEL = 0V, f 250MHz PLL_SEL = 2.5V PLL_SEL = 0V Minimum 31.25 15.625 TBD TBD TBD TBD TBD TBD Typical Maximum 62.5 31.25 Units MHz MHz ns ps ps ps mS ps %
odc Output Duty Cycle TBD All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
86004BG
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5%
2.05V5% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VDD, VDDA
SCOPE
VDDO GND
Qx
LVCMOS
GND
LVCMOS
VDDO 2
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V5%
VDD, VDDA, VDDO
SCOPE
Q0:Q3
Qx
V
DDO
V
DDO
V
DDO
2
2
2
LVCMOS
GND
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
-1.25V5%
2.5VCORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
V
CLK
2
DDO
Qx
FB_IN
DDO
Qy
t(O)
2 tsk(o)
t(O) mean = Static Phase Offset (where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
OUTPUT SKEW
86004BG
STATIC PHASE OFFSET
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6
REV. A OCTOBER 14, 2003
V
tcycle n+1
VDD 2
VDD 2
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
VDDO
VDDO 2 t PW t PERIOD
VDDO 2
Q0:Q3
2
80% 20% tR
80% 20% tF
Clock Outputs
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
CLK
VDD 2
Q0:Q3
t
PD
VDDO 2
PROPAGATION DELAY
86004BG
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7
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS86004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F VDDA .01F 10 F 10
FIGURE 1. POWER SUPPLY FILTERING
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of using an ICS86004. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible.
R1 VDD
43 Zo = 50
Serial Termination R3 1K VDD U1 VDD 1 2 3 4 5 6 7 8 Q1 GND Q0 F_SEL VDD CLK GND VDDA VDDO Q2 GND Q3 VDDO MR FB_IN PLL_SEL 16 15 14 13 12 11 10 9 R11 43 Zo = 50 VDD R6 1K C16 10u C11 0.01u VDD Parallel Termination Zo = 50 R2 43
Ro ~ 7 Ohm Zo = 50 R8 LVCMOS 43 VDD R7 10
ICS86004
(U1-5)
VDD
(U1-12)
(U1-16)
R4 100
C1 0.1uF
C2 0.1uF
C3 0.1uF
Zo = 50 R5 100
VDD=3.3V
FIGURE 2. ICS86004 SCHEMATIC EXAMPLE
86004BG
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8
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86004 is: 2496
86004BG
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9
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PACKAGE OUTLINE - G SUFFIX 16 LEAD TSSOP
TABLE 6. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
86004BG
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10
REV. A OCTOBER 14, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
Marking ICS86004BG ICS86004BG Package 16 Lead TSSOP 16 Lead TSSOP on Tape and Reel Count 94 per tube 2500 Temperature 0C to 70C 0C to 70C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS86004BG ICS86004BGT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 86004BG
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REV. A OCTOBER 14, 2003

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